From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Tue, 6 Jul 2021 14:23:36 +0000 Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants and defines --- include/dt-bindings/clock/rk3228-cru.h | 1 + include/soc/rockchip/rockchip_sip.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index de550ea56..911824731 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -15,6 +15,7 @@ #define ARMCLK 5 /* sclk gates (special clocks) */ +#define SCLK_DDRCLK 64 #define SCLK_SPI0 65 #define SCLK_NANDC 67 #define SCLK_SDMMC 68 diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h index c46a9ae2a..34e653751 100644 --- a/include/soc/rockchip/rockchip_sip.h +++ b/include/soc/rockchip/rockchip_sip.h @@ -6,6 +6,7 @@ #ifndef __SOC_ROCKCHIP_SIP_H #define __SOC_ROCKCHIP_SIP_H +#define ROCKCHIP_SIP_ATF_VERSION 0x82000001 #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 @@ -16,5 +17,28 @@ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 +#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a +#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b + +#define ROCKCHIP_SIP_SHARE_MEM 0x82000009 +#define ROCKCHIP_SIP_SIP_VERSION 0x8200000a + +/* Rockchip Sip version */ +#define ROCKCHIP_SIP_IMPLEMENT_V1 (1) +#define ROCKCHIP_SIP_IMPLEMENT_V2 (2) + +/* SIP_ACCESS_REG: read or write */ +#define SECURE_REG_RD 0x0 +#define SECURE_REG_WR 0x1 + +/* Share mem page types */ +typedef enum { + SHARE_PAGE_TYPE_INVALID = 0, + SHARE_PAGE_TYPE_UARTDBG, + SHARE_PAGE_TYPE_DDR, + SHARE_PAGE_TYPE_MAX, +} share_page_type_t; #endif -- 2.25.1