From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 6 Apr 2022 01:04:45 +0200 Subject: dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs This cache controller is also used on the StarFive JH7100 and JH7110 SoCs. Signed-off-by: Emil Renner Berthing --- Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index bf3f07421f7e..41eb60da04a4 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -25,6 +25,8 @@ select: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache required: - compatible @@ -37,6 +39,8 @@ properties: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache + - starfive,jh7110-ccache - const: cache - items: - const: microchip,mpfs-ccache -- Armbian