From 864881b284ad9276b91dd95a2b60b8b7fb4e4847 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Thu, 16 Sep 2021 13:48:34 -0400 Subject: [PATCH 435/478] phy: rockchip: sync combophy driver with latest submission This syncs the combophy driver to the latest submission from rockchip. It renames the clocks and includes a fix for their submission. This will need changes to the devicetree for the clock renames. Signed-off-by: Peter Geis --- .../rockchip/phy-rockchip-naneng-combphy.c | 38 ++++++++++++++++--- 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index d28fe5728e7a..e399d79a62bb 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -411,7 +411,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) /* Configure PHY reference clock frequency */ for (i = 0; i < priv->num_clks; i++) { - if (!strncmp(priv->clks[i].id, "refclk", 6)) { + if (!strncmp(priv->clks[i].id, "ref", 6)) { refclk = priv->clks[i].clk; break; } @@ -448,6 +448,27 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) val |= 0x01; writel(val, priv->mmio + (0x0e << 2)); + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); @@ -484,7 +505,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) switch (rate) { case 24000000: - if (priv->mode == PHY_TYPE_USB3) { + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ val = readl(priv->mmio + (0x0e << 2)); val &= ~GENMASK(7, 6); @@ -519,7 +540,12 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) writel(0x32, priv->mmio + (0x11 << 2)); writel(0xf0, priv->mmio + (0xa << 2)); - + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(7, 4); + val |= 0x50; + writel(val, priv->mmio + (0x1f << 2)); } break; default: @@ -586,9 +612,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { }; static const struct clk_bulk_data rk3568_clks[] = { - { .id = "refclk" }, - { .id = "apbclk" }, - { .id = "pipe_clk" }, + { .id = "ref" }, + { .id = "apb" }, + { .id = "pipe" }, }; static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { -- 2.35.3