From f2a0a2819978f5d52b9b129d98c734bf4e7e7db8 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Wed, 2 Feb 2022 21:29:16 +0300 Subject: [PATCH 126/170] arm:dts:overlay: sun8i-h3-cpu-clock add overclock --- arch/arm/boot/dts/overlay/Makefile | 3 + .../sun8i-h3-cpu-clock-1.2GHz-1.3v.dts | 31 +++++++++ .../sun8i-h3-cpu-clock-1.368GHz-1.3v.dts | 67 +++++++++++++++++++ .../sun8i-h3-cpu-clock-1.3GHz-1.3v.dts | 61 +++++++++++++++++ 4 files changed, 162 insertions(+) create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile index d2e94f6b7..23f8c2048 100644 --- a/arch/arm/boot/dts/overlay/Makefile +++ b/arch/arm/boot/dts/overlay/Makefile @@ -60,6 +60,9 @@ dtbo-$(CONFIG_MACH_SUN7I) += \ dtbo-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-analog-codec.dtbo \ sun8i-h3-cir.dtbo \ + sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \ + sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \ + sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \ sun8i-h3-i2c0.dtbo \ sun8i-h3-i2c1.dtbo \ sun8i-h3-i2c2.dtbo \ diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts new file mode 100644 index 000000000..b07e694c7 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts @@ -0,0 +1,31 @@ +// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&cpu0_opp_table>; + + __overlay__ { + compatible = "operating-points-v2"; + opp-shared; + + // in order to match the existing DT cooling-maps, update the existing OP table in-place + // with the new voltages + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts new file mode 100644 index 000000000..e3fd7e5c8 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts @@ -0,0 +1,67 @@ +// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&cpu0_opp_table>; + + __overlay__ { + compatible = "operating-points-v2"; + opp-shared; + + // in order to match the DT cooling-maps, update the existing OP table in-place + // with the new voltages + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1224000000 { + opp-hz = /bits/ 64 <1224000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1368000000 { + opp-hz = /bits/ 64 <1368000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts new file mode 100644 index 000000000..413222831 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts @@ -0,0 +1,61 @@ +// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&cpu0_opp_table>; + + __overlay__ { + compatible = "operating-points-v2"; + opp-shared; + + // in order to match the DT cooling-maps, update the existing OP table in-place + // with the new voltages + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1224000000 { + opp-hz = /bits/ 64 <1224000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + }; +}; + -- 2.35.3