diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 7fcf340db6..723113b10b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -208,6 +208,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
 #define CCM_PLL1_CTRL_P(n)		(((n) & 0x3) << 16)
 #define CCM_PLL1_CTRL_EN		(0x1 << 31)
+#define CCM_PLL1_CTRL_LOCK		(0x1 << 28)
 
 #define CCM_PLL3_CTRL_M_SHIFT		0
 #define CCM_PLL3_CTRL_M_MASK		(0xf << CCM_PLL3_CTRL_M_SHIFT)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 86f08ab717..0c403204c5 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -158,15 +158,17 @@ void clock_set_pll1(unsigned int clk)
 	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
-	sdelay(200);
+
+	while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
+		;
 
 	/* Switch CPU to PLL1 */
 	if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
 		writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 		       &ccm->cpu_axi_cfg);
 	} else {
-		writel(AXI_DIV_3 << AXI_DIV_SHIFT |
-		       ATB_DIV_2 << ATB_DIV_SHIFT |
+		writel(AXI_DIV_4 << AXI_DIV_SHIFT |
+		       ATB_DIV_4 << ATB_DIV_SHIFT |
 		       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 		       &ccm->cpu_axi_cfg);
 	}