diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi new file mode 100644 index 000000000..a3f5ff4bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr3_odt_dis_freq = <100>; + phy_ddr3_odt_dis_freq = <100>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <666>; + phy_lpddr3_odt_dis_freq = <666>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <7>; + ddr3a0_ddr4a10_de-skew = <7>; + ddr3a3_ddr4a6_de-skew = <8>; + ddr3a2_ddr4a4_de-skew = <8>; + ddr3a5_ddr4a8_de-skew = <7>; + ddr3a4_ddr4a5_de-skew = <9>; + ddr3a7_ddr4a11_de-skew = <7>; + ddr3a6_ddr4a7_de-skew = <9>; + ddr3a9_ddr4a0_de-skew = <8>; + ddr3a8_ddr4a13_de-skew = <7>; + ddr3a11_ddr4a3_de-skew = <9>; + ddr3a10_ddr4cs0_de-skew = <7>; + ddr3a13_ddr4a2_de-skew = <8>; + ddr3a12_ddr4ba1_de-skew = <7>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <8>; + ddr3ba1_ddr4a15_de-skew = <7>; + ddr3ba0_ddr4bg0_de-skew = <7>; + ddr3ras_ddr4cke_de-skew = <7>; + ddr3ba2_ddr4ba0_de-skew = <8>; + ddr3we_ddr4bg1_de-skew = <8>; + ddr3cas_ddr4a12_de-skew = <7>; + ddr3ckn_ddr4ckn_de-skew = <8>; + ddr3ckp_ddr4ckp_de-skew = <8>; + ddr3cke_ddr4a16_de-skew = <8>; + ddr3odt0_ddr4a14_de-skew = <7>; + ddr3cs0_ddr4act_de-skew = <8>; + ddr3reset_ddr4reset_de-skew = <7>; + ddr3cs1_ddr4cs1_de-skew = <7>; + ddr3odt1_ddr4odt1_de-skew = <7>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <8>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq0_tx_de-skew = <8>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq1_tx_de-skew = <8>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq2_tx_de-skew = <8>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq3_tx_de-skew = <8>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq4_tx_de-skew = <8>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq5_tx_de-skew = <8>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq6_tx_de-skew = <8>; + cs0_dq7_rx_de-skew = <7>; + cs0_dq7_tx_de-skew = <8>; + cs0_dqs0_rx_de-skew = <6>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1_rx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <8>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq16_tx_de-skew = <8>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <8>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <8>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq20_tx_de-skew = <8>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq21_tx_de-skew = <8>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <7>; + cs0_dq23_tx_de-skew = <8>; + cs0_dqs2_rx_de-skew = <6>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <8>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <8>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <8>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi new file mode 100644 index 000000000..36890bb7f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3328-dram-default-timing.dtsi" +#include "rk3328.dtsi" + +/ { + model = "FriendlyElec boards based on Rockchip RK3328"; + compatible = "friendlyelec,nanopi-r2", + "rockchip,rk3328"; + + aliases { + ethernet1 = &r8153; + }; + + chosen { + bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0"; + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + mach: board { + compatible = "friendlyelec,board"; + machine = "NANOPI-R2"; + hwrev = <255>; + model = "NanoPi R2 Series"; + nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + status = "disabled"; + + led@1 { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk805 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; + + sdmmc_ext: dwmmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + status = "disabled"; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vccio_sd: sdmmcio-regulator { + compatible = "regulator-gpio"; + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + regulator-name = "vccio_sd"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_io>; + startup-delay-us = <2000>; + regulator-settling-time-us = <5000>; + enable-active-high; + status = "disabled"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_host_vbus: host-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_host_vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + dfi: dfi@ff790000 { + reg = <0x00 0xff790000 0x00 0x400>; + compatible = "rockchip,rk3328-dfi"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3328-dmc"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + auto-min-freq = <786000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "disabled"; + + ddr_power_model: ddr_power_model { + compatible = "ddr_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-798000000 { + opp-hz = /bits/ 64 <798000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1075000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-hs200-1_8v; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "disabled"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_phy>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,aal; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@0 { + reg = <0>; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */ + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-init-microvolt = <1075000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_18>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_dectn: sdmmc0-dectn { + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + <1 RK_PA0 1 &pcfg_pull_up_4ma>, + <1 RK_PA1 1 &pcfg_pull_up_4ma>, + <1 RK_PA2 1 &pcfg_pull_up_4ma>, + <1 RK_PA3 1 &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0ext { + sdmmc0ext_clk: sdmmc0ext-clk { + rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>; + }; + + sdmmc0ext_cmd: sdmmc0ext-cmd { + rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>; + }; + + sdmmc0ext_bus4: sdmmc0ext-bus4 { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_up_2ma>, + <3 RK_PA5 3 &pcfg_pull_up_2ma>, + <3 RK_PA6 3 &pcfg_pull_up_2ma>, + <3 RK_PA7 3 &pcfg_pull_up_2ma>; + }; + }; + + gmac-1 { + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* mac_txclk */ + <1 RK_PB4 2 &pcfg_pull_none_4ma>, + /* mac_rxclk */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PC3 2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 RK_PD1 2 &pcfg_pull_none_4ma>, + /* mac_clk */ + <1 RK_PC5 2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PC7 2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 RK_PB2 2 &pcfg_pull_none>, + /* mac_rxd0 */ + <1 RK_PB3 2 &pcfg_pull_none>, + /* mac_txd1 */ + <1 RK_PB0 2 &pcfg_pull_none_4ma>, + /* mac_txd0 */ + <1 RK_PB1 2 &pcfg_pull_none_4ma>, + /* mac_rxd3 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* mac_rxd2 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* mac_txd3 */ + <1 RK_PC0 2 &pcfg_pull_none_4ma>, + /* mac_txd2 */ + <1 RK_PC1 2 &pcfg_pull_none_4ma>, + + /* mac_txclk */ + <0 RK_PB0 1 &pcfg_pull_none>, + /* mac_txen */ + <0 RK_PB4 1 &pcfg_pull_none>, + /* mac_clk */ + <0 RK_PD0 1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 RK_PC0 1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 RK_PC7 1 &pcfg_pull_none>, + /* mac_txd2 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdmmc_ext { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>; + rockchip,default-sample-phase = <120>; + supports-sdio; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = ; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&u3phy { + vbus-supply = <&vcc_host_vbus>; + status = "okay"; +}; + +&u3phy_utmi { + status = "okay"; +}; + +&u3phy_pipe { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + r8153: device@2 { + compatible = "usbbda:8153"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts new file mode 100644 index 000000000..971397659 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include +#include "rk3328-nanopi-r2-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key1>; + + button@0 { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_en_drv>; + regulator-always-on; + regulator-name = "vcc_rtl8153"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + off-on-delay-us = <5000>; + enable-active-high; + }; +}; + +&mach { + hwrev = <0>; + model = "NanoPi R2S"; +}; + +&emmc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; +}; + +&leds { + status = "okay"; + + led@2 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "lan_led"; + }; + + led@3 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + linux,default-trigger = "stmmac-0:00:link"; + }; +}; + +&rk805 { + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&vccio_sd { + status = "okay"; +}; + +&io_domains { + vccio3-supply = <&vccio_sd>; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc_ext { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "disabled"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + gpio_key1: gpio-key1 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb30_en_drv: usb30-en-drv { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts new file mode 100644 index 000000000..5663ce078 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include "rk3328-nanopi-r2-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R2"; + compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; +}; + +&mach { + hwrev = <0x20>; + model = "NanoPi R2"; +}; + +&gmac2io { + pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>; +}; + +&rtl8211e { + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&pinctrl { + phy { + phy_intb: phy-intb { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h new file mode 100644 index 000000000..b065432e7 --- /dev/null +++ b/include/dt-bindings/clock/rockchip-ddr.h @@ -0,0 +1,63 @@ +/* + * + * Copyright (C) 2017 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H + +#define DDR2_DEFAULT (0) + +#define DDR3_800D (0) /* 5-5-5 */ +#define DDR3_800E (1) /* 6-6-6 */ +#define DDR3_1066E (2) /* 6-6-6 */ +#define DDR3_1066F (3) /* 7-7-7 */ +#define DDR3_1066G (4) /* 8-8-8 */ +#define DDR3_1333F (5) /* 7-7-7 */ +#define DDR3_1333G (6) /* 8-8-8 */ +#define DDR3_1333H (7) /* 9-9-9 */ +#define DDR3_1333J (8) /* 10-10-10 */ +#define DDR3_1600G (9) /* 8-8-8 */ +#define DDR3_1600H (10) /* 9-9-9 */ +#define DDR3_1600J (11) /* 10-10-10 */ +#define DDR3_1600K (12) /* 11-11-11 */ +#define DDR3_1866J (13) /* 10-10-10 */ +#define DDR3_1866K (14) /* 11-11-11 */ +#define DDR3_1866L (15) /* 12-12-12 */ +#define DDR3_1866M (16) /* 13-13-13 */ +#define DDR3_2133K (17) /* 11-11-11 */ +#define DDR3_2133L (18) /* 12-12-12 */ +#define DDR3_2133M (19) /* 13-13-13 */ +#define DDR3_2133N (20) /* 14-14-14 */ +#define DDR3_DEFAULT (21) +#define DDR_DDR2 (22) +#define DDR_LPDDR (23) +#define DDR_LPDDR2 (24) + +#define DDR4_1600J (0) /* 10-10-10 */ +#define DDR4_1600K (1) /* 11-11-11 */ +#define DDR4_1600L (2) /* 12-12-12 */ +#define DDR4_1866L (3) /* 12-12-12 */ +#define DDR4_1866M (4) /* 13-13-13 */ +#define DDR4_1866N (5) /* 14-14-14 */ +#define DDR4_2133N (6) /* 14-14-14 */ +#define DDR4_2133P (7) /* 15-15-15 */ +#define DDR4_2133R (8) /* 16-16-16 */ +#define DDR4_2400P (9) /* 15-15-15 */ +#define DDR4_2400R (10) /* 16-16-16 */ +#define DDR4_2400U (11) /* 18-18-18 */ +#define DDR4_DEFAULT (12) + +#define PAUSE_CPU_STACK_SIZE 16 + +#endif diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h new file mode 100644 index 000000000..171f41c25 --- /dev/null +++ b/include/dt-bindings/memory/rk3328-dram.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H + +#define DDR3_DS_34ohm (34) +#define DDR3_DS_40ohm (40) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (40) +#define DDR3_ODT_60ohm (60) +#define DDR3_ODT_120ohm (120) + +#define LP2_DS_34ohm (34) +#define LP2_DS_40ohm (40) +#define LP2_DS_48ohm (48) +#define LP2_DS_60ohm (60) +#define LP2_DS_68_6ohm (68) /* optional */ +#define LP2_DS_80ohm (80) +#define LP2_DS_120ohm (120) /* optional */ + +#define LP3_DS_34ohm (34) +#define LP3_DS_40ohm (40) +#define LP3_DS_48ohm (48) +#define LP3_DS_60ohm (60) +#define LP3_DS_80ohm (80) +#define LP3_DS_34D_40U (3440) +#define LP3_DS_40D_48U (4048) +#define LP3_DS_34D_48U (3448) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (60) +#define LP3_ODT_120ohm (120) +#define LP3_ODT_240ohm (240) + +#define LP4_PDDS_40ohm (40) +#define LP4_PDDS_48ohm (48) +#define LP4_PDDS_60ohm (60) +#define LP4_PDDS_80ohm (80) +#define LP4_PDDS_120ohm (120) +#define LP4_PDDS_240ohm (240) + +#define LP4_DQ_ODT_40ohm (40) +#define LP4_DQ_ODT_48ohm (48) +#define LP4_DQ_ODT_60ohm (60) +#define LP4_DQ_ODT_80ohm (80) +#define LP4_DQ_ODT_120ohm (120) +#define LP4_DQ_ODT_240ohm (240) +#define LP4_DQ_ODT_DIS (0) + +#define LP4_CA_ODT_40ohm (40) +#define LP4_CA_ODT_48ohm (48) +#define LP4_CA_ODT_60ohm (60) +#define LP4_CA_ODT_80ohm (80) +#define LP4_CA_ODT_120ohm (120) +#define LP4_CA_ODT_240ohm (240) +#define LP4_CA_ODT_DIS (0) + +#define DDR4_DS_34ohm (34) +#define DDR4_DS_48ohm (48) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60ohm (60) +#define DDR4_RTT_NOM_120ohm (120) +#define DDR4_RTT_NOM_40ohm (40) +#define DDR4_RTT_NOM_240ohm (240) +#define DDR4_RTT_NOM_48ohm (48) +#define DDR4_RTT_NOM_80ohm (80) +#define DDR4_RTT_NOM_34ohm (34) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/