From 3169742f1483d5340bedff8b2f35a210bad5f3ca Mon Sep 17 00:00:00 2001 From: ashthespy Date: Fri, 17 Jan 2020 16:22:13 +0100 Subject: [PATCH 10/23] arm64: dts: rockchip: add i2s_8ch for rk3308 --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 105 ++++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index d2613ec774c1..37ffedb99a2d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -605,6 +605,109 @@ dmac1: dma-controller@ff2d0000 { }; }; + i2s_8ch_0: i2s@ff300000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff300000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, + <&cru SCLK_I2S0_8CH_TX_SRC>, + <&cru SCLK_I2S0_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_sclkrx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_lrckrx + &i2s_8ch_0_sdi0 + &i2s_8ch_0_sdi1 + &i2s_8ch_0_sdi2 + &i2s_8ch_0_sdi3 + &i2s_8ch_0_sdo0 + &i2s_8ch_0_sdo1 + &i2s_8ch_0_sdo2 + &i2s_8ch_0_sdo3 + &i2s_8ch_0_mclk>; + status = "disabled"; + }; + + i2s_8ch_1: i2s@ff310000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff310000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>, + <&cru SCLK_I2S1_8CH_TX_SRC>, + <&cru SCLK_I2S1_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + rockchip,io-multiplex; + status = "disabled"; + }; + + i2s_8ch_2: i2s@ff320000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff320000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>, + <&cru SCLK_I2S2_8CH_TX_SRC>, + <&cru SCLK_I2S2_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 4>, <&dmac1 5>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + status = "disabled"; + }; + + i2s_8ch_3: i2s@ff330000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff330000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>, + <&cru SCLK_I2S3_8CH_TX_SRC>, + <&cru SCLK_I2S3_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 7>; + dma-names = "rx"; + resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + status = "disabled"; + }; + i2s_2ch_0: i2s@ff350000 { compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff350000 0x0 0x1000>; -- 2.25.1