From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Paolo Date: Thu, 23 Jun 2022 08:30:54 +0200 Subject: [ARCHEOLOGY] rockchip64: add rk3318-box tvbox board patch and configurations (#3921) > X-Git-Archeology: > recovered message: > * rockchip64: add rk3318-box tvbox board patch and configurations > X-Git-Archeology: > recovered message: > * rockchip64: add missing bcm43342 patch for edge kernel > X-Git-Archeology: - Revision 2ca6a9381db4b875533926e0eae9d3d17f68ad06: https://github.com/armbian/build/commit/2ca6a9381db4b875533926e0eae9d3d17f68ad06 > X-Git-Archeology: Date: Thu, 23 Jun 2022 08:30:54 +0200 > X-Git-Archeology: From: Paolo > X-Git-Archeology: Subject: rockchip64: add rk3318-box tvbox board patch and configurations (#3921) > X-Git-Archeology: > X-Git-Archeology: - Revision 0310f955051adafee3a9701e7e54f01d6a496ff5: https://github.com/armbian/build/commit/0310f955051adafee3a9701e7e54f01d6a496ff5 > X-Git-Archeology: Date: Sat, 09 Jul 2022 16:30:16 +0200 > X-Git-Archeology: From: Paolo > X-Git-Archeology: Subject: rockchip64: fix rk3318-box cpu voltages (#3976) > X-Git-Archeology: > X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 > X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 > X-Git-Archeology: From: Jianfeng Liu > X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) > X-Git-Archeology: > X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 > X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 > X-Git-Archeology: From: Igor Pecovnik > X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) > X-Git-Archeology: > X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 > X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 > X-Git-Archeology: From: Igor Pecovnik > X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) > X-Git-Archeology: > X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 > X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 > X-Git-Archeology: From: amazingfate > X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 > X-Git-Archeology: --- arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi | 311 ++++++++++ 1 file changed, 311 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi new file mode 100644 index 000000000000..31a28d82952f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr3_odt_dis_freq = <100>; + phy_ddr3_odt_dis_freq = <100>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <666>; + phy_lpddr3_odt_dis_freq = <666>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <2>; + ddr3a0_ddr4a10_de-skew = <3>; + ddr3a3_ddr4a6_de-skew = <3>; + ddr3a2_ddr4a4_de-skew = <2>; + ddr3a5_ddr4a8_de-skew = <3>; + ddr3a4_ddr4a5_de-skew = <2>; + ddr3a7_ddr4a11_de-skew = <3>; + ddr3a6_ddr4a7_de-skew = <2>; + ddr3a9_ddr4a0_de-skew = <2>; + ddr3a8_ddr4a13_de-skew = <1>; + ddr3a11_ddr4a3_de-skew = <2>; + ddr3a10_ddr4cs0_de-skew = <2>; + ddr3a13_ddr4a2_de-skew = <1>; + ddr3a12_ddr4ba1_de-skew = <2>; + ddr3a15_ddr4odt0_de-skew = <3>; + ddr3a14_ddr4a1_de-skew = <2>; + ddr3ba1_ddr4a15_de-skew = <2>; + ddr3ba0_ddr4bg0_de-skew = <4>; + ddr3ras_ddr4cke_de-skew = <4>; + ddr3ba2_ddr4ba0_de-skew = <3>; + ddr3we_ddr4bg1_de-skew = <2>; + ddr3cas_ddr4a12_de-skew = <2>; + ddr3ckn_ddr4ckn_de-skew = <11>; + ddr3ckp_ddr4ckp_de-skew = <11>; + ddr3cke_ddr4a16_de-skew = <2>; + ddr3odt0_ddr4a14_de-skew = <4>; + ddr3cs0_ddr4act_de-skew = <4>; + ddr3reset_ddr4reset_de-skew = <7>; + ddr3cs1_ddr4cs1_de-skew = <7>; + ddr3odt1_ddr4odt1_de-skew = <7>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <12>; + cs0_dm0_tx_de-skew = <10>; + cs0_dq0_rx_de-skew = <12>; + cs0_dq0_tx_de-skew = <10>; + cs0_dq1_rx_de-skew = <12>; + cs0_dq1_tx_de-skew = <10>; + cs0_dq2_rx_de-skew = <12>; + cs0_dq2_tx_de-skew = <10>; + cs0_dq3_rx_de-skew = <12>; + cs0_dq3_tx_de-skew = <10>; + cs0_dq4_rx_de-skew = <12>; + cs0_dq4_tx_de-skew = <10>; + cs0_dq5_rx_de-skew = <12>; + cs0_dq5_tx_de-skew = <10>; + cs0_dq6_rx_de-skew = <12>; + cs0_dq6_tx_de-skew = <10>; + cs0_dq7_rx_de-skew = <12>; + cs0_dq7_tx_de-skew = <10>; + cs0_dqs0_rx_de-skew = <10>; + cs0_dqs0p_tx_de-skew = <12>; + cs0_dqs0n_tx_de-skew = <12>; + + cs0_dm1_rx_de-skew = <10>; + cs0_dm1_tx_de-skew = <8>; + cs0_dq8_rx_de-skew = <10>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <10>; + cs0_dq9_tx_de-skew = <8>; + cs0_dq10_rx_de-skew = <10>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <10>; + cs0_dq11_tx_de-skew = <8>; + cs0_dq12_rx_de-skew = <10>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <10>; + cs0_dq13_tx_de-skew = <8>; + cs0_dq14_rx_de-skew = <10>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <10>; + cs0_dq15_tx_de-skew = <8>; + cs0_dqs1_rx_de-skew = <9>; + cs0_dqs1p_tx_de-skew = <10>; + cs0_dqs1n_tx_de-skew = <10>; + + cs0_dm2_rx_de-skew = <10>; + cs0_dm2_tx_de-skew = <9>; + cs0_dq16_rx_de-skew = <10>; + cs0_dq16_tx_de-skew = <9>; + cs0_dq17_rx_de-skew = <10>; + cs0_dq17_tx_de-skew = <9>; + cs0_dq18_rx_de-skew = <10>; + cs0_dq18_tx_de-skew = <9>; + cs0_dq19_rx_de-skew = <10>; + cs0_dq19_tx_de-skew = <9>; + cs0_dq20_rx_de-skew = <10>; + cs0_dq20_tx_de-skew = <9>; + cs0_dq21_rx_de-skew = <10>; + cs0_dq21_tx_de-skew = <9>; + cs0_dq22_rx_de-skew = <10>; + cs0_dq22_tx_de-skew = <9>; + cs0_dq23_rx_de-skew = <10>; + cs0_dq23_tx_de-skew = <9>; + cs0_dqs2_rx_de-skew = <9>; + cs0_dqs2p_tx_de-skew = <11>; + cs0_dqs2n_tx_de-skew = <11>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <7>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <10>; + cs0_dqs3n_tx_de-skew = <10>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <8>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <8>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <8>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + }; +}; -- Armbian