From bdbf0a1cb3c23e69ddff2a2c1c3202455b248afc Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 16 Aug 2017 12:37:30 +0800 Subject: [PATCH 1/3] ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI controllers. Add the device nodes for the controllers. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7b2d684aeb97..3e7e99745b73 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -297,6 +297,25 @@ usbphy: phy@1c19400 { #phy-cells = <1>; }; + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; -- 2.28.0 From 7c23b1d9d8140c97ffcfe5714467a6dc23462b32 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 16 Aug 2017 12:38:25 +0800 Subject: [PATCH 2/3] ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero As the USB port on Lichee Pi Zero works in the OTG mode, enable the EHCI/OHCI controllers for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts index 2e4587d26ce5..0cd969194acb 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts @@ -77,6 +77,10 @@ red_led { }; }; +&ehci0 { + status = "okay"; +}; + &mmc0 { broken-cd; bus-width = <4>; @@ -84,6 +88,10 @@ &mmc0 { status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &uart0 { pinctrl-0 = <&uart0_pb_pins>; pinctrl-names = "default"; -- 2.28.0 From 845ece80db17cca5e205a14bb07bc428f0035c14 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 22 Nov 2020 08:25:35 +0800 Subject: [PATCH 3/3] ARM: dts: sun8i: s3: switch PineCube to use OHCI/EHCI only The PineCube board features a USB Type-A connector connected to the SoC's USB pins. As this is not designed for being used as a USB device, disable OTG controller and route USB to OHCI/EHCI fixedly. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts index 4aa0ee897a0a..c4177c54ef29 100644 --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts @@ -78,6 +78,12 @@ csi1_ep: endpoint { }; }; +&ehci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + &emac { phy-handle = <&int_mii_phy>; phy-mode = "mii"; @@ -158,6 +164,12 @@ &mmc1 { status = "okay"; }; +&ohci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + &pio { vcc-pd-supply = <®_dcdc3>; vcc-pe-supply = <®_ldo3>; @@ -224,11 +236,6 @@ &uart2 { status = "okay"; }; -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - &usbphy { usb0_vbus-supply = <®_vcc5v0>; status = "okay"; -- 2.28.0