From edb97bfb16d446719388a0fddd08d046cad9723c Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 3 Jun 2020 11:06:05 +0200 Subject: [PATCH 228/351] drm debugging code --- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 14 ++++++++++++++ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index e58482f6d7ba..5ef1f75130b8 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -101,6 +101,11 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } + + unsigned tmp; + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp); } static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -218,11 +223,20 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, return -EINVAL; } + unsigned tmp; + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp); + val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-format %08x\n", tmp); + return 0; } diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 0c2ccc33d456..c393c388e6be 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -95,6 +95,11 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, DRM_DEBUG_DRIVER(" enable pipe %d <- ch %d\n", zpos, channel); } + + unsigned tmp; + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-en-dis %08x\n", tmp); } static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -275,11 +280,20 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, return ret; } + unsigned tmp; + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" pre-format %08x\n", tmp); + val = hw_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" mid1-format %08x\n", tmp); + csc_mode = sun8i_vi_layer_get_csc_mode(fmt); if (csc_mode != SUN8I_CSC_MODE_OFF) { sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode, @@ -290,6 +304,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, sun8i_csc_enable_ccsc(mixer, channel, false); } + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" mid2-format %08x\n", tmp); + if (!fmt->is_yuv) val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE; else @@ -307,6 +325,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK, SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(0xff)); + regmap_read(mixer->engine.regs, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), &tmp); + DRM_DEBUG_DRIVER(" post-format %08x\n", tmp); + return 0; } -- 2.34.0