From d271d5f20015452fbe7fc8f983dde014b6904741 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 25 Dec 2017 12:08:01 +0800 Subject: [PATCH 097/101] Doc:dt-bindings:usb: add binding for DWC3 controller on Allwinner SoC The Allwinner H6 SoC uses DWC3 controller for USB3. Add its device tree binding document. Signed-off-by: Icenowy Zheng --- .../bindings/usb/allwinner,dwc3.txt | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt new file mode 100644 index 000000000..3f7714636 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt @@ -0,0 +1,39 @@ +Allwinner SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: should contain "allwinner,sun50i-h6-dwc3" for H6 SoC +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "bus" The bus clock of the DWC3 part +- resets: A list of phandle + reset-specifier pairs for the + resets listed in reset-names +- reset-names: Should contain the following: + "bus" The bus reset of the DWC3 part + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Phy documentation is provided in the following places: +Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt + +Example device nodes: + usb3: usb@5200000 { + compatible = "allwinner,sun50i-h6-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&ccu CLK_BUS_XHCI>; + clock-names = "bus"; + resets = <&ccu RST_BUS_XHCI>; + reset-names = "bus"; + + dwc3: dwc3 { + compatible = "snps,dwc3"; + reg = <0x5200000 0x10000>; + interrupts = ; + phys = <&usb3phy>; + phy-names = "usb3-phy"; + }; + }; -- 2.31.1