From 7f8a0e72011bfac4601e445fe3a75171b22ffdd9 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 10 Mar 2020 06:04:32 +0100 Subject: [PATCH 115/478] clk: sunxi-ng: Don't use CPU PLL gating and CPUX reparenting to HOSC It's not necessary when not using dividers on CPU PLL, and it's causing cntvct jump backs on H3. Signed-off-by: Ondrej Jirman --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index ec4c92bca173..9d461deb13f8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -1129,20 +1129,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = { .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets), }; -static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = { - .common = &pll_cpux_clk.common, - /* copy from pll_cpux_clk */ - .enable = BIT(31), - .lock = BIT(28), -}; - -static struct ccu_mux_nb sun8i_h3_cpu_nb = { - .common = &cpux_clk.common, - .cm = &cpux_clk.mux, - .delay_us = 1, /* > 8 clock cycles at 24 MHz */ - .bypass_index = 1, /* index of 24 MHz oscillator */ -}; - static void __init sunxi_h3_h5_ccu_init(struct device_node *node, const struct sunxi_ccu_desc *desc) { @@ -1161,13 +1147,6 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node, writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); of_sunxi_ccu_probe(node, reg, desc); - - /* Gate then ungate PLL CPU after any rate changes */ - ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb); - - /* Reparent CPU during PLL CPU rate changes */ - ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, - &sun8i_h3_cpu_nb); } static void __init sun8i_h3_ccu_setup(struct device_node *node) -- 2.35.3