From 5e8ddad49123e2ef40705993bfb487cf5a77715b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Mon, 23 May 2022 18:54:32 +0200
Subject: [PATCH 350/389] media: i2c: imx258: Simplify register settings

Split into common and per-mode settings. Use understandable macros,
instead of raw values.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 drivers/media/i2c/imx258.c | 859 ++++++++++++++++++++-----------------
 1 file changed, 477 insertions(+), 382 deletions(-)

diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index 4f47253e182d..db9abd9c41c6 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -79,9 +79,60 @@
 #define REG_CONFIG_FLIP_TEST_PATTERN	0x02
 
 /* Input clock frequency in Hz */
-#define IMX258_INPUT_CLOCK_FREQ_MIN	19000000
-#define IMX258_INPUT_CLOCK_FREQ		19200000
-#define IMX258_INPUT_CLOCK_FREQ_MAX	19400000
+#define IMX258_INPUT_CLOCK_FREQ_MIN	24000000
+#define IMX258_INPUT_CLOCK_FREQ		24000000
+#define IMX258_INPUT_CLOCK_FREQ_MAX	24000000
+
+/* regs */
+#define PLL_MULT_DRIV                  0x0310
+#define IVTPXCK_DIV                    0x0301
+#define IVTSYCK_DIV                    0x0303
+#define PREPLLCK_VT_DIV                0x0305
+#define IOPPXCK_DIV                    0x0309
+#define IOPSYCK_DIV                    0x030b
+#define PREPLLCK_OP_DIV                0x030d
+#define PHASE_PIX_OUTEN                0x3030
+#define PDPIX_DATA_RATE                0x3032
+#define SCALE_MODE                     0x0401
+#define SCALE_MODE_EXT                 0x3038
+#define AF_WINDOW_MODE                 0x7bcd
+#define FRM_LENGTH_CTL                 0x0350
+#define CSI_LANE_MODE                  0x0114
+#define X_EVN_INC                      0x0381
+#define X_ODD_INC                      0x0383
+#define Y_EVN_INC                      0x0385
+#define Y_ODD_INC                      0x0387
+#define BINNING_MODE                   0x0900
+#define BINNING_TYPE_V                 0x0901
+#define FORCE_FD_SUM                   0x300d
+#define HDR_MODE                       0x0220
+#define MODE_SEL                       0x0100
+#define DIG_CROP_X_OFFSET              0x0408
+#define DIG_CROP_Y_OFFSET              0x040a
+#define DIG_CROP_IMAGE_WIDTH           0x040c
+#define DIG_CROP_IMAGE_HEIGHT          0x040e
+#define SCALE_M                        0x0404
+#define X_OUT_SIZE                     0x034c
+#define Y_OUT_SIZE                     0x034e
+#define X_ADD_STA                      0x0344
+#define Y_ADD_STA                      0x0346
+#define X_ADD_END                      0x0348
+#define Y_ADD_END                      0x034a
+#define EXCK_FREQ                      0x0136
+#define CSI_DT_FMT                     0x0112
+#define LINE_LENGTH_PCK                0x0342
+#define FRM_LENGTH_LINES               0x0340
+#define SCALE_M_EXT                    0x303a
+#define COARSE_INTEG_TIME              0x0202
+#define FINE_INTEG_TIME                0x0200
+#define ANA_GAIN_GLOBAL                0x0204
+#define PLL_IVT_MPY                    0x0306
+#define PLL_IOP_MPY                    0x030e
+#define REQ_LINK_BIT_RATE_MBPS_H       0x0820
+#define REQ_LINK_BIT_RATE_MBPS_L       0x0822
+
+#define REG8(a, v) { a, v }
+#define REG16(a, v) { a, ((v) >> 8) & 0xff }, { (a) + 1, (v) & 0xff }
 
 struct imx258_reg {
 	u16 address;
@@ -118,398 +169,424 @@ struct imx258_mode {
 	struct imx258_reg_list reg_list;
 };
 
-/* 4208x3118 needs 1267Mbps/lane, 4 lanes */
+/* 4032*3024 needs 1267Mbps/lane, 4 lanes */
 static const struct imx258_reg mipi_data_rate_1267mbps[] = {
-	{ 0x0301, 0x05 },
-	{ 0x0303, 0x02 },
-	{ 0x0305, 0x03 },
-	{ 0x0306, 0x00 },
-	{ 0x0307, 0xC6 },
-	{ 0x0309, 0x0A },
-	{ 0x030B, 0x01 },
-	{ 0x030D, 0x02 },
-	{ 0x030E, 0x00 },
-	{ 0x030F, 0xD8 },
-	{ 0x0310, 0x00 },
-	{ 0x0820, 0x13 },
-	{ 0x0821, 0x4C },
-	{ 0x0822, 0xCC },
-	{ 0x0823, 0xCC },
+	REG8(IVTPXCK_DIV, 5),
+	REG8(IVTSYCK_DIV, 2),
+	REG8(PREPLLCK_VT_DIV, 4),
+	REG16(PLL_IVT_MPY, 208), // 1296 MHz
+	REG8(IOPPXCK_DIV, 10), // or 8
+	REG8(IOPSYCK_DIV, 1),
+	REG8(PREPLLCK_OP_DIV, 2),
+	REG16(PLL_IOP_MPY, 216),
+	REG8(PLL_MULT_DRIV, 0),
+	REG16(REQ_LINK_BIT_RATE_MBPS_H, 4992),
+	REG16(REQ_LINK_BIT_RATE_MBPS_L, 0),
 };
 
 static const struct imx258_reg mipi_data_rate_640mbps[] = {
-	{ 0x0301, 0x05 },
-	{ 0x0303, 0x02 },
-	{ 0x0305, 0x03 },
-	{ 0x0306, 0x00 },
-	{ 0x0307, 0x64 },
-	{ 0x0309, 0x0A },
-	{ 0x030B, 0x01 },
-	{ 0x030D, 0x02 },
-	{ 0x030E, 0x00 },
-	{ 0x030F, 0xD8 },
-	{ 0x0310, 0x00 },
-	{ 0x0820, 0x0A },
-	{ 0x0821, 0x00 },
-	{ 0x0822, 0x00 },
-	{ 0x0823, 0x00 },
+	REG8(IVTPXCK_DIV, 0x05),
+	REG8(IVTSYCK_DIV, 0x02),
+	REG8(PREPLLCK_VT_DIV, 0x03),
+	REG16(PLL_IVT_MPY, 0x0064), // 100
+	REG8(IOPPXCK_DIV, 0x0a),
+	REG8(IOPSYCK_DIV, 0x01),
+	REG8(PREPLLCK_OP_DIV, 0x02),
+	REG16(PLL_IOP_MPY, 0x00d8), // 216
+	REG8(PLL_MULT_DRIV, 0x00),
+	REG16(REQ_LINK_BIT_RATE_MBPS_H, 0x0a00), // 2560
+	REG16(REQ_LINK_BIT_RATE_MBPS_L, 0x0000), // 0
+};
+
+static const struct imx258_reg common_regs[] = {
+	REG8(EXCK_FREQ, 24),
+	REG8(EXCK_FREQ+1, 0),
+
+	REG8(0x3051, 0x00),
+
+	REG8(0x3052, 0x00), // extra in mainline
+	REG8(0x4e21, 0x14), // extra in mainline
+
+	REG8(0x6b11, 0xcf),
+	REG8(0x7ff0, 0x08),
+	REG8(0x7ff1, 0x0f),
+	REG8(0x7ff2, 0x08),
+	REG8(0x7ff3, 0x1b),
+	REG8(0x7ff4, 0x23),
+	REG8(0x7ff5, 0x60),
+	REG8(0x7ff6, 0x00),
+	REG8(0x7ff7, 0x01),
+	REG8(0x7ff8, 0x00),
+	REG8(0x7ff9, 0x78),
+	REG8(0x7ffa, 0x01), // 1 in rk, 0 in mainline
+	REG8(0x7ffb, 0x00),
+	REG8(0x7ffc, 0x00),
+	REG8(0x7ffd, 0x00),
+	REG8(0x7ffe, 0x00),
+	REG8(0x7fff, 0x03),
+	REG8(0x7f76, 0x03),
+	REG8(0x7f77, 0xfe),
+	REG8(0x7fa8, 0x03),
+	REG8(0x7fa9, 0xfe),
+	REG8(0x7b24, 0x81),
+	REG8(0x7b25, 0x01), // 1 in rk, 0 in mainline
+	REG8(0x6564, 0x07),
+	REG8(0x6b0d, 0x41),
+	REG8(0x653d, 0x04),
+	REG8(0x6b05, 0x8c),
+	REG8(0x6b06, 0xf9),
+	REG8(0x6b08, 0x65),
+	REG8(0x6b09, 0xfc),
+	REG8(0x6b0a, 0xcf),
+	REG8(0x6b0b, 0xd2),
+	REG8(0x6700, 0x0e),
+	REG8(0x6707, 0x0e), // extra in mainline
+	REG8(0x9104, 0x00), // extra in mainline
+	REG8(0x4648, 0x7f), // extra in mainline
+	REG8(0x7420, 0x00), // extra in mainline
+	REG8(0x7421, 0x1c), // extra in mainline
+	REG8(0x7422, 0x00), // extra in mainline
+	REG8(0x7423, 0xd7), // extra in mainline
+	REG8(0x5f04, 0x00),
+	REG8(0x5f05, 0xed),
+
+	// extra in rk bsp driver (pixel defect correction)
+	{0x94c7, 0xff},
+	{0x94c8, 0xff},
+	{0x94c9, 0xff},
+	{0x95c7, 0xff},
+	{0x95c8, 0xff},
+	{0x95c9, 0xff},
+	{0x94c4, 0x3f},
+	{0x94c5, 0x3f},
+	{0x94c6, 0x3f},
+	{0x95c4, 0x3f},
+	{0x95c5, 0x3f},
+	{0x95c6, 0x3f},
+	{0x94c1, 0x02},
+	{0x94c2, 0x02},
+	{0x94c3, 0x02},
+	{0x95c1, 0x02},
+	{0x95c2, 0x02},
+	{0x95c3, 0x02},
+	{0x94be, 0x0c},
+	{0x94bf, 0x0c},
+	{0x94c0, 0x0c},
+	{0x95be, 0x0c},
+	{0x95bf, 0x0c},
+	{0x95c0, 0x0c},
+	{0x94d0, 0x74},
+	{0x94d1, 0x74},
+	{0x94d2, 0x74},
+	{0x95d0, 0x74},
+	{0x95d1, 0x74},
+	{0x95d2, 0x74},
+	{0x94cd, 0x2e},
+	{0x94ce, 0x2e},
+	{0x94cf, 0x2e},
+	{0x95cd, 0x2e},
+	{0x95ce, 0x2e},
+	{0x95cf, 0x2e},
+	{0x94ca, 0x4c},
+	{0x94cb, 0x4c},
+	{0x94cc, 0x4c},
+	{0x95ca, 0x4c},
+	{0x95cb, 0x4c},
+	{0x95cc, 0x4c},
+	{0x900e, 0x32},
+	{0x94e2, 0xff},
+	{0x94e3, 0xff},
+	{0x94e4, 0xff},
+	{0x95e2, 0xff},
+	{0x95e3, 0xff},
+	{0x95e4, 0xff},
+	{0x94df, 0x6e},
+	{0x94e0, 0x6e},
+	{0x94e1, 0x6e},
+	{0x95df, 0x6e},
+	{0x95e0, 0x6e},
+	{0x95e1, 0x6e},
+	{0x7fcc, 0x01},
+	{0x7b78, 0x00},
+	{0x9401, 0x35},
+	{0x9403, 0x23},
+	{0x9405, 0x23},
+	{0x9406, 0x00},
+	{0x9407, 0x31},
+	{0x9408, 0x00},
+	{0x9409, 0x1b},
+	{0x940a, 0x00},
+	{0x940b, 0x15},
+	{0x940d, 0x3f},
+	{0x940f, 0x3f},
+	{0x9411, 0x3f},
+	{0x9413, 0x64},
+	{0x9415, 0x64},
+	{0x9417, 0x64},
+	{0x941d, 0x34},
+	{0x941f, 0x01},
+	{0x9421, 0x01},
+	{0x9423, 0x01},
+	{0x9425, 0x23},
+	{0x9427, 0x23},
+	{0x9429, 0x23},
+	{0x942b, 0x2f},
+	{0x942d, 0x1a},
+	{0x942f, 0x14},
+	{0x9431, 0x3f},
+	{0x9433, 0x3f},
+	{0x9435, 0x3f},
+	{0x9437, 0x6b},
+	{0x9439, 0x7c},
+	{0x943b, 0x81},
+	{0x9443, 0x0f},
+	{0x9445, 0x0f},
+	{0x9447, 0x0f},
+	{0x9449, 0x0f},
+	{0x944b, 0x0f},
+	{0x944d, 0x0f},
+	{0x944f, 0x1e},
+	{0x9451, 0x0f},
+	{0x9453, 0x0b},
+	{0x9455, 0x28},
+	{0x9457, 0x13},
+	{0x9459, 0x0c},
+	{0x945d, 0x00},
+	{0x945e, 0x00},
+	{0x945f, 0x00},
+	{0x946d, 0x00},
+	{0x946f, 0x10},
+	{0x9471, 0x10},
+	{0x9473, 0x40},
+	{0x9475, 0x2e},
+	{0x9477, 0x10},
+	{0x9478, 0x0a},
+	{0x947b, 0xe0},
+	{0x947c, 0xe0},
+	{0x947d, 0xe0},
+	{0x947e, 0xe0},
+	{0x947f, 0xe0},
+	{0x9480, 0xe0},
+	{0x9483, 0x14},
+	{0x9485, 0x14},
+	{0x9487, 0x14},
+	{0x9501, 0x35},
+	{0x9503, 0x14},
+	{0x9505, 0x14},
+	{0x9507, 0x31},
+	{0x9509, 0x1b},
+	{0x950b, 0x15},
+	{0x950d, 0x1e},
+	{0x950f, 0x1e},
+	{0x9511, 0x1e},
+	{0x9513, 0x64},
+	{0x9515, 0x64},
+	{0x9517, 0x64},
+	{0x951d, 0x34},
+	{0x951f, 0x01},
+	{0x9521, 0x01},
+	{0x9523, 0x01},
+	{0x9525, 0x14},
+	{0x9527, 0x14},
+	{0x9529, 0x14},
+	{0x952b, 0x2f},
+	{0x952d, 0x1a},
+	{0x952f, 0x14},
+	{0x9531, 0x1e},
+	{0x9533, 0x1e},
+	{0x9535, 0x1e},
+	{0x9537, 0x6b},
+	{0x9539, 0x7c},
+	{0x953b, 0x81},
+	{0x9543, 0x0f},
+	{0x9545, 0x0f},
+	{0x9547, 0x0f},
+	{0x9549, 0x0f},
+	{0x954b, 0x0f},
+	{0x954d, 0x0f},
+	{0x954f, 0x15},
+	{0x9551, 0x0b},
+	{0x9553, 0x08},
+	{0x9555, 0x1c},
+	{0x9557, 0x0d},
+	{0x9559, 0x08},
+	{0x955d, 0x00},
+	{0x955e, 0x00},
+	{0x955f, 0x00},
+	{0x956d, 0x00},
+	{0x956f, 0x10},
+	{0x9571, 0x10},
+	{0x9573, 0x40},
+	{0x9575, 0x2e},
+	{0x9577, 0x10},
+	{0x9578, 0x0a},
+	{0x957b, 0xe0},
+	{0x957c, 0xe0},
+	{0x957d, 0xe0},
+	{0x957e, 0xe0},
+	{0x957f, 0xe0},
+	{0x9580, 0xe0},
+	{0x9583, 0x14},
+	{0x9585, 0x14},
+	{0x9587, 0x14},
+	{0x7f78, 0x00},
+	{0x7f89, 0x00},
+	{0x7f93, 0x00},
+	{0x924b, 0x1b},
+	{0x924c, 0x0a},
+	{0x9304, 0x04},
+	{0x9315, 0x04},
+	{0x9250, 0x50},
+	{0x9251, 0x3c},
+	{0x9252, 0x14},
+
+	REG8(0x94dc, 0x20),
+	REG8(0x94dd, 0x20),
+	REG8(0x94de, 0x20),
+	REG8(0x95dc, 0x20),
+	REG8(0x95dd, 0x20),
+	REG8(0x95de, 0x20),
+	REG8(0x7fb0, 0x00),
+	REG8(0x9010, 0x3e),
+	REG8(0x9419, 0x50),
+	REG8(0x941b, 0x50),
+	REG8(0x9519, 0x50),
+	REG8(0x951b, 0x50),
+
+	// common per-mode settings
+	REG16(ANA_GAIN_GLOBAL, 0),
+	REG8(0x20e, 0x01),
+	REG8(0x20f, 0x00),
+	REG8(0x210, 0x01),
+	REG8(0x211, 0x00),
+	REG8(0x212, 0x01),
+	REG8(0x213, 0x00),
+	REG8(0x214, 0x01),
+	REG8(0x215, 0x00),
+	REG8(AF_WINDOW_MODE, 0),
+	REG8(PHASE_PIX_OUTEN, 0x00),
+	REG8(PDPIX_DATA_RATE, 0x00),
+	REG8(HDR_MODE, 0x00),
 };
 
 static const struct imx258_reg mode_4208x3118_regs[] = {
-	{ 0x0136, 0x13 },
-	{ 0x0137, 0x33 },
-	{ 0x3051, 0x00 },
-	{ 0x3052, 0x00 },
-	{ 0x4E21, 0x14 },
-	{ 0x6B11, 0xCF },
-	{ 0x7FF0, 0x08 },
-	{ 0x7FF1, 0x0F },
-	{ 0x7FF2, 0x08 },
-	{ 0x7FF3, 0x1B },
-	{ 0x7FF4, 0x23 },
-	{ 0x7FF5, 0x60 },
-	{ 0x7FF6, 0x00 },
-	{ 0x7FF7, 0x01 },
-	{ 0x7FF8, 0x00 },
-	{ 0x7FF9, 0x78 },
-	{ 0x7FFA, 0x00 },
-	{ 0x7FFB, 0x00 },
-	{ 0x7FFC, 0x00 },
-	{ 0x7FFD, 0x00 },
-	{ 0x7FFE, 0x00 },
-	{ 0x7FFF, 0x03 },
-	{ 0x7F76, 0x03 },
-	{ 0x7F77, 0xFE },
-	{ 0x7FA8, 0x03 },
-	{ 0x7FA9, 0xFE },
-	{ 0x7B24, 0x81 },
-	{ 0x7B25, 0x00 },
-	{ 0x6564, 0x07 },
-	{ 0x6B0D, 0x41 },
-	{ 0x653D, 0x04 },
-	{ 0x6B05, 0x8C },
-	{ 0x6B06, 0xF9 },
-	{ 0x6B08, 0x65 },
-	{ 0x6B09, 0xFC },
-	{ 0x6B0A, 0xCF },
-	{ 0x6B0B, 0xD2 },
-	{ 0x6700, 0x0E },
-	{ 0x6707, 0x0E },
-	{ 0x9104, 0x00 },
-	{ 0x4648, 0x7F },
-	{ 0x7420, 0x00 },
-	{ 0x7421, 0x1C },
-	{ 0x7422, 0x00 },
-	{ 0x7423, 0xD7 },
-	{ 0x5F04, 0x00 },
-	{ 0x5F05, 0xED },
-	{ 0x0112, 0x0A },
-	{ 0x0113, 0x0A },
-	{ 0x0114, 0x03 },
-	{ 0x0342, 0x14 },
-	{ 0x0343, 0xE8 },
-	{ 0x0340, 0x0C },
-	{ 0x0341, 0x50 },
-	{ 0x0344, 0x00 },
-	{ 0x0345, 0x00 },
-	{ 0x0346, 0x00 },
-	{ 0x0347, 0x00 },
-	{ 0x0348, 0x10 },
-	{ 0x0349, 0x6F },
-	{ 0x034A, 0x0C },
-	{ 0x034B, 0x2E },
-	{ 0x0381, 0x01 },
-	{ 0x0383, 0x01 },
-	{ 0x0385, 0x01 },
-	{ 0x0387, 0x01 },
-	{ 0x0900, 0x00 },
-	{ 0x0901, 0x11 },
-	{ 0x0401, 0x00 },
-	{ 0x0404, 0x00 },
-	{ 0x0405, 0x10 },
-	{ 0x0408, 0x00 },
-	{ 0x0409, 0x00 },
-	{ 0x040A, 0x00 },
-	{ 0x040B, 0x00 },
-	{ 0x040C, 0x10 },
-	{ 0x040D, 0x70 },
-	{ 0x040E, 0x0C },
-	{ 0x040F, 0x30 },
-	{ 0x3038, 0x00 },
-	{ 0x303A, 0x00 },
-	{ 0x303B, 0x10 },
-	{ 0x300D, 0x00 },
-	{ 0x034C, 0x10 },
-	{ 0x034D, 0x70 },
-	{ 0x034E, 0x0C },
-	{ 0x034F, 0x30 },
-	{ 0x0350, 0x01 },
-	{ 0x0202, 0x0C },
-	{ 0x0203, 0x46 },
-	{ 0x0204, 0x00 },
-	{ 0x0205, 0x00 },
-	{ 0x020E, 0x01 },
-	{ 0x020F, 0x00 },
-	{ 0x0210, 0x01 },
-	{ 0x0211, 0x00 },
-	{ 0x0212, 0x01 },
-	{ 0x0213, 0x00 },
-	{ 0x0214, 0x01 },
-	{ 0x0215, 0x00 },
-	{ 0x7BCD, 0x00 },
-	{ 0x94DC, 0x20 },
-	{ 0x94DD, 0x20 },
-	{ 0x94DE, 0x20 },
-	{ 0x95DC, 0x20 },
-	{ 0x95DD, 0x20 },
-	{ 0x95DE, 0x20 },
-	{ 0x7FB0, 0x00 },
-	{ 0x9010, 0x3E },
-	{ 0x9419, 0x50 },
-	{ 0x941B, 0x50 },
-	{ 0x9519, 0x50 },
-	{ 0x951B, 0x50 },
-	{ 0x3030, 0x00 },
-	{ 0x3032, 0x00 },
-	{ 0x0220, 0x00 },
+	REG16(CSI_DT_FMT, 0x0a0a), // 2570
+	REG8(CSI_LANE_MODE, 0x03),
+	REG16(LINE_LENGTH_PCK, 0x14e8), // 5352
+	REG16(FRM_LENGTH_LINES, 0x0c50), // 3152
+	REG16(X_ADD_STA, 0),
+	REG16(Y_ADD_STA, 0),
+	REG16(X_ADD_END, 4207),
+	REG16(Y_ADD_END, 3119),
+	REG8(X_EVN_INC, 0x01),
+	REG8(X_ODD_INC, 0x01),
+	REG8(Y_EVN_INC, 0x01),
+	REG8(Y_ODD_INC, 0x01),
+	REG8(BINNING_MODE, 0x00),
+	REG8(BINNING_TYPE_V, 0x11),
+	REG8(SCALE_MODE, 0x00),
+	REG16(SCALE_M, 0x0010), // 16
+	REG16(DIG_CROP_X_OFFSET, 0),
+	REG16(DIG_CROP_Y_OFFSET, 0),
+	REG16(DIG_CROP_IMAGE_WIDTH, 4208),
+	REG16(DIG_CROP_IMAGE_HEIGHT, 3120),
+	REG8(SCALE_MODE_EXT, 0x00),
+	REG16(SCALE_M_EXT, 0x0010), // 16
+	REG8(FORCE_FD_SUM, 0x00),
+	REG16(X_OUT_SIZE, 4208),
+	REG16(Y_OUT_SIZE, 3120),
+	REG8(FRM_LENGTH_CTL, 0x01),
+	REG16(COARSE_INTEG_TIME, 3142),
+};
+
+static const struct imx258_reg mode_4032x3024_regs[] = {
+	REG16(CSI_DT_FMT, 0x0a0a), // 2570
+	REG8(CSI_LANE_MODE, 0x03),
+	REG16(LINE_LENGTH_PCK, 5352),
+	REG16(FRM_LENGTH_LINES, 3224),
+	REG16(X_ADD_STA, 0),
+	REG16(Y_ADD_STA, 0),
+	REG16(X_ADD_END, 4207),
+	REG16(Y_ADD_END, 3119),
+	REG8(X_EVN_INC, 1),
+	REG8(X_ODD_INC, 1),
+	REG8(Y_EVN_INC, 1),
+	REG8(Y_ODD_INC, 1),
+	REG8(BINNING_MODE, 0x00),
+	REG8(BINNING_TYPE_V, 0x11),
+	REG8(SCALE_MODE, 0x00),
+	REG16(SCALE_M, 16),
+	REG16(DIG_CROP_X_OFFSET, 0), //(4208-4032)/2),
+	REG16(DIG_CROP_Y_OFFSET, 0), //(3120-3024)/2),
+	REG16(DIG_CROP_IMAGE_WIDTH, 4032),
+	REG16(DIG_CROP_IMAGE_HEIGHT, 3024),
+	REG8(SCALE_MODE_EXT, 0),
+	REG16(SCALE_M_EXT, 16),
+	REG8(FORCE_FD_SUM, 0x00),
+	REG16(X_OUT_SIZE, 4032),
+	REG16(Y_OUT_SIZE, 3024),
+	REG8(FRM_LENGTH_CTL, 0x01),
+	REG16(COARSE_INTEG_TIME, 3184),
 };
 
 static const struct imx258_reg mode_2104_1560_regs[] = {
-	{ 0x0136, 0x13 },
-	{ 0x0137, 0x33 },
-	{ 0x3051, 0x00 },
-	{ 0x3052, 0x00 },
-	{ 0x4E21, 0x14 },
-	{ 0x6B11, 0xCF },
-	{ 0x7FF0, 0x08 },
-	{ 0x7FF1, 0x0F },
-	{ 0x7FF2, 0x08 },
-	{ 0x7FF3, 0x1B },
-	{ 0x7FF4, 0x23 },
-	{ 0x7FF5, 0x60 },
-	{ 0x7FF6, 0x00 },
-	{ 0x7FF7, 0x01 },
-	{ 0x7FF8, 0x00 },
-	{ 0x7FF9, 0x78 },
-	{ 0x7FFA, 0x00 },
-	{ 0x7FFB, 0x00 },
-	{ 0x7FFC, 0x00 },
-	{ 0x7FFD, 0x00 },
-	{ 0x7FFE, 0x00 },
-	{ 0x7FFF, 0x03 },
-	{ 0x7F76, 0x03 },
-	{ 0x7F77, 0xFE },
-	{ 0x7FA8, 0x03 },
-	{ 0x7FA9, 0xFE },
-	{ 0x7B24, 0x81 },
-	{ 0x7B25, 0x00 },
-	{ 0x6564, 0x07 },
-	{ 0x6B0D, 0x41 },
-	{ 0x653D, 0x04 },
-	{ 0x6B05, 0x8C },
-	{ 0x6B06, 0xF9 },
-	{ 0x6B08, 0x65 },
-	{ 0x6B09, 0xFC },
-	{ 0x6B0A, 0xCF },
-	{ 0x6B0B, 0xD2 },
-	{ 0x6700, 0x0E },
-	{ 0x6707, 0x0E },
-	{ 0x9104, 0x00 },
-	{ 0x4648, 0x7F },
-	{ 0x7420, 0x00 },
-	{ 0x7421, 0x1C },
-	{ 0x7422, 0x00 },
-	{ 0x7423, 0xD7 },
-	{ 0x5F04, 0x00 },
-	{ 0x5F05, 0xED },
-	{ 0x0112, 0x0A },
-	{ 0x0113, 0x0A },
-	{ 0x0114, 0x03 },
-	{ 0x0342, 0x14 },
-	{ 0x0343, 0xE8 },
-	{ 0x0340, 0x06 },
-	{ 0x0341, 0x38 },
-	{ 0x0344, 0x00 },
-	{ 0x0345, 0x00 },
-	{ 0x0346, 0x00 },
-	{ 0x0347, 0x00 },
-	{ 0x0348, 0x10 },
-	{ 0x0349, 0x6F },
-	{ 0x034A, 0x0C },
-	{ 0x034B, 0x2E },
-	{ 0x0381, 0x01 },
-	{ 0x0383, 0x01 },
-	{ 0x0385, 0x01 },
-	{ 0x0387, 0x01 },
-	{ 0x0900, 0x01 },
-	{ 0x0901, 0x12 },
-	{ 0x0401, 0x01 },
-	{ 0x0404, 0x00 },
-	{ 0x0405, 0x20 },
-	{ 0x0408, 0x00 },
-	{ 0x0409, 0x02 },
-	{ 0x040A, 0x00 },
-	{ 0x040B, 0x00 },
-	{ 0x040C, 0x10 },
-	{ 0x040D, 0x6A },
-	{ 0x040E, 0x06 },
-	{ 0x040F, 0x18 },
-	{ 0x3038, 0x00 },
-	{ 0x303A, 0x00 },
-	{ 0x303B, 0x10 },
-	{ 0x300D, 0x00 },
-	{ 0x034C, 0x08 },
-	{ 0x034D, 0x38 },
-	{ 0x034E, 0x06 },
-	{ 0x034F, 0x18 },
-	{ 0x0350, 0x01 },
-	{ 0x0202, 0x06 },
-	{ 0x0203, 0x2E },
-	{ 0x0204, 0x00 },
-	{ 0x0205, 0x00 },
-	{ 0x020E, 0x01 },
-	{ 0x020F, 0x00 },
-	{ 0x0210, 0x01 },
-	{ 0x0211, 0x00 },
-	{ 0x0212, 0x01 },
-	{ 0x0213, 0x00 },
-	{ 0x0214, 0x01 },
-	{ 0x0215, 0x00 },
-	{ 0x7BCD, 0x01 },
-	{ 0x94DC, 0x20 },
-	{ 0x94DD, 0x20 },
-	{ 0x94DE, 0x20 },
-	{ 0x95DC, 0x20 },
-	{ 0x95DD, 0x20 },
-	{ 0x95DE, 0x20 },
-	{ 0x7FB0, 0x00 },
-	{ 0x9010, 0x3E },
-	{ 0x9419, 0x50 },
-	{ 0x941B, 0x50 },
-	{ 0x9519, 0x50 },
-	{ 0x951B, 0x50 },
-	{ 0x3030, 0x00 },
-	{ 0x3032, 0x00 },
-	{ 0x0220, 0x00 },
+	REG16(CSI_DT_FMT, 0x0a0a), // 2570
+	REG8(CSI_LANE_MODE, 0x03),
+	REG16(LINE_LENGTH_PCK, 0x14e8), // 5352
+	REG16(FRM_LENGTH_LINES, 0x0638), // 1592
+	REG16(X_ADD_STA, 0),
+	REG16(Y_ADD_STA, 0),
+	REG16(X_ADD_END, 4207),
+	REG16(Y_ADD_END, 3119),
+	REG8(X_EVN_INC, 0x01),
+	REG8(X_ODD_INC, 0x01),
+	REG8(Y_EVN_INC, 0x01),
+	REG8(Y_ODD_INC, 0x01),
+	REG8(BINNING_MODE, 0x01),
+	REG8(BINNING_TYPE_V, 0x12),
+	REG8(SCALE_MODE, 0x01),
+	REG16(SCALE_M, 0x0020), // 32
+	REG16(DIG_CROP_X_OFFSET, 2),
+	REG16(DIG_CROP_Y_OFFSET, 0),
+	REG16(DIG_CROP_IMAGE_WIDTH, 4208),
+	REG16(DIG_CROP_IMAGE_HEIGHT, 1560),
+	REG8(SCALE_MODE_EXT, 0x00),
+	REG16(SCALE_M_EXT, 0x0010), // 16
+	REG8(FORCE_FD_SUM, 0x00),
+	REG16(X_OUT_SIZE, 2104),
+	REG16(Y_OUT_SIZE, 1560),
+	REG8(FRM_LENGTH_CTL, 0x01),
+	REG16(COARSE_INTEG_TIME, 1582),
 };
 
 static const struct imx258_reg mode_1048_780_regs[] = {
-	{ 0x0136, 0x13 },
-	{ 0x0137, 0x33 },
-	{ 0x3051, 0x00 },
-	{ 0x3052, 0x00 },
-	{ 0x4E21, 0x14 },
-	{ 0x6B11, 0xCF },
-	{ 0x7FF0, 0x08 },
-	{ 0x7FF1, 0x0F },
-	{ 0x7FF2, 0x08 },
-	{ 0x7FF3, 0x1B },
-	{ 0x7FF4, 0x23 },
-	{ 0x7FF5, 0x60 },
-	{ 0x7FF6, 0x00 },
-	{ 0x7FF7, 0x01 },
-	{ 0x7FF8, 0x00 },
-	{ 0x7FF9, 0x78 },
-	{ 0x7FFA, 0x00 },
-	{ 0x7FFB, 0x00 },
-	{ 0x7FFC, 0x00 },
-	{ 0x7FFD, 0x00 },
-	{ 0x7FFE, 0x00 },
-	{ 0x7FFF, 0x03 },
-	{ 0x7F76, 0x03 },
-	{ 0x7F77, 0xFE },
-	{ 0x7FA8, 0x03 },
-	{ 0x7FA9, 0xFE },
-	{ 0x7B24, 0x81 },
-	{ 0x7B25, 0x00 },
-	{ 0x6564, 0x07 },
-	{ 0x6B0D, 0x41 },
-	{ 0x653D, 0x04 },
-	{ 0x6B05, 0x8C },
-	{ 0x6B06, 0xF9 },
-	{ 0x6B08, 0x65 },
-	{ 0x6B09, 0xFC },
-	{ 0x6B0A, 0xCF },
-	{ 0x6B0B, 0xD2 },
-	{ 0x6700, 0x0E },
-	{ 0x6707, 0x0E },
-	{ 0x9104, 0x00 },
-	{ 0x4648, 0x7F },
-	{ 0x7420, 0x00 },
-	{ 0x7421, 0x1C },
-	{ 0x7422, 0x00 },
-	{ 0x7423, 0xD7 },
-	{ 0x5F04, 0x00 },
-	{ 0x5F05, 0xED },
-	{ 0x0112, 0x0A },
-	{ 0x0113, 0x0A },
-	{ 0x0114, 0x03 },
-	{ 0x0342, 0x14 },
-	{ 0x0343, 0xE8 },
-	{ 0x0340, 0x03 },
-	{ 0x0341, 0x4C },
-	{ 0x0344, 0x00 },
-	{ 0x0345, 0x00 },
-	{ 0x0346, 0x00 },
-	{ 0x0347, 0x00 },
-	{ 0x0348, 0x10 },
-	{ 0x0349, 0x6F },
-	{ 0x034A, 0x0C },
-	{ 0x034B, 0x2E },
-	{ 0x0381, 0x01 },
-	{ 0x0383, 0x01 },
-	{ 0x0385, 0x01 },
-	{ 0x0387, 0x01 },
-	{ 0x0900, 0x01 },
-	{ 0x0901, 0x14 },
-	{ 0x0401, 0x01 },
-	{ 0x0404, 0x00 },
-	{ 0x0405, 0x40 },
-	{ 0x0408, 0x00 },
-	{ 0x0409, 0x06 },
-	{ 0x040A, 0x00 },
-	{ 0x040B, 0x00 },
-	{ 0x040C, 0x10 },
-	{ 0x040D, 0x64 },
-	{ 0x040E, 0x03 },
-	{ 0x040F, 0x0C },
-	{ 0x3038, 0x00 },
-	{ 0x303A, 0x00 },
-	{ 0x303B, 0x10 },
-	{ 0x300D, 0x00 },
-	{ 0x034C, 0x04 },
-	{ 0x034D, 0x18 },
-	{ 0x034E, 0x03 },
-	{ 0x034F, 0x0C },
-	{ 0x0350, 0x01 },
-	{ 0x0202, 0x03 },
-	{ 0x0203, 0x42 },
-	{ 0x0204, 0x00 },
-	{ 0x0205, 0x00 },
-	{ 0x020E, 0x01 },
-	{ 0x020F, 0x00 },
-	{ 0x0210, 0x01 },
-	{ 0x0211, 0x00 },
-	{ 0x0212, 0x01 },
-	{ 0x0213, 0x00 },
-	{ 0x0214, 0x01 },
-	{ 0x0215, 0x00 },
-	{ 0x7BCD, 0x00 },
-	{ 0x94DC, 0x20 },
-	{ 0x94DD, 0x20 },
-	{ 0x94DE, 0x20 },
-	{ 0x95DC, 0x20 },
-	{ 0x95DD, 0x20 },
-	{ 0x95DE, 0x20 },
-	{ 0x7FB0, 0x00 },
-	{ 0x9010, 0x3E },
-	{ 0x9419, 0x50 },
-	{ 0x941B, 0x50 },
-	{ 0x9519, 0x50 },
-	{ 0x951B, 0x50 },
-	{ 0x3030, 0x00 },
-	{ 0x3032, 0x00 },
-	{ 0x0220, 0x00 },
+	REG16(CSI_DT_FMT, 0x0a0a), // 2570
+	REG8(CSI_LANE_MODE, 0x03),
+	REG16(LINE_LENGTH_PCK, 0x14e8), // 5352
+	REG16(FRM_LENGTH_LINES, 0x034c), // 844
+	REG16(X_ADD_STA, 0x0000), // 0
+	REG16(Y_ADD_STA, 0x0000), // 0
+	REG16(X_ADD_END, 4191),
+	REG16(Y_ADD_END, 3119),
+	REG8(X_EVN_INC, 0x01),
+	REG8(X_ODD_INC, 0x01),
+	REG8(Y_EVN_INC, 0x01),
+	REG8(Y_ODD_INC, 0x01),
+	REG8(BINNING_MODE, 0x01),
+	REG8(BINNING_TYPE_V, 0x14),
+	REG8(SCALE_MODE, 0x01),
+	REG16(SCALE_M, 0x0040), // 64
+	REG16(DIG_CROP_X_OFFSET, 0x0006), // 6
+	REG16(DIG_CROP_Y_OFFSET, 0x0000), // 0
+	REG16(DIG_CROP_IMAGE_WIDTH, 4192),
+	REG16(DIG_CROP_IMAGE_HEIGHT, 780), // 780
+	REG8(SCALE_MODE_EXT, 0x00),
+	REG16(SCALE_M_EXT, 0x0010), // 16
+	REG8(FORCE_FD_SUM, 0x00),
+	REG16(X_OUT_SIZE, 1048), // 1048
+	REG16(Y_OUT_SIZE, 780), // 780
+	REG8(FRM_LENGTH_CTL, 0x01),
+	REG16(COARSE_INTEG_TIME, 0x0342), // 834
 };
 
 static const char * const imx258_test_pattern_menu[] = {
@@ -578,6 +655,17 @@ static const struct imx258_mode supported_modes[] = {
 		},
 		.link_freq_index = IMX258_LINK_FREQ_1267MBPS,
 	},
+	{
+		.width = 4032,
+		.height = 3024,
+		.vts_def = IMX258_VTS_30FPS,
+		.vts_min = IMX258_VTS_30FPS,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(mode_4032x3024_regs),
+			.regs = mode_4032x3024_regs,
+		},
+		.link_freq_index = IMX258_LINK_FREQ_1267MBPS,
+	},
 	{
 		.width = 2104,
 		.height = 1560,
@@ -964,6 +1052,13 @@ static int imx258_start_streaming(struct imx258 *imx258)
 	const struct imx258_reg_list *reg_list;
 	int ret, link_freq_index;
 
+	/* Common registers */
+	ret = imx258_write_regs(imx258, common_regs, ARRAY_SIZE(common_regs));
+	if (ret) {
+		dev_err(&client->dev, "%s failed to set common registers\n", __func__);
+		return ret;
+	}
+
 	/* Setup PLL */
 	link_freq_index = imx258->cur_mode->link_freq_index;
 	reg_list = &link_freq_configs[link_freq_index].reg_list;
-- 
2.35.3