From 83245baf899e580c000483afe5d61840e78e3b03 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 25 Apr 2023 18:17:19 +0200 Subject: [PATCH 462/469] arm64: dts: rockchip: rk3588s: Add USB3 controllers Add all USB3 controllers. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 29 ++++++++++- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 60 ++++++++++++++++++++++- 2 files changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 07119c308e48..a0ab543c4c54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,34 @@ #include "rk3588-pinctrl.dtsi" / { + usbdrd3_1: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref", "suspend", "bus"; + ranges; + resets = <&cru SRST_A_USB3OTG1>; + reset-names = "usb3-otg"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + }; + }; + pipe_phy1_grf: syscon@fd5c0000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5c0000 0x0 0x100>; @@ -34,7 +62,6 @@ u2phy1: usb2-phy@4000 { clock-names = "phyclk"; clock-output-names = "usb480m_phy1"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled"; u2phy1_otg: otg-port { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index e08e9221aea9..2a0037d203fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -832,6 +832,36 @@ scmi_shmem: sram@0 { }; }; + usbdrd3_0: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref", "suspend", "bus"; + ranges; + resets = <&cru SRST_A_USB3OTG0>; + reset-names = "usb3-otg"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -876,6 +906,35 @@ usb_host1_ohci: usb@fc8c0000 { status = "disabled"; }; + usbhost3_0: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3-host", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; + ranges; + resets = <&cru SRST_A_USB3OTG2>; + reset-names = "usb3-host"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usbhost_dwc3_0: usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = ; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + }; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -898,7 +957,6 @@ u2phy0: usb2-phy@0 { clock-names = "phyclk"; clock-output-names = "usb480m_phy0"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled"; u2phy0_otg: otg-port { -- 2.34.1