diff --git a/drivers/net/wireless/ssv6x5x/Kconfig b/drivers/net/wireless/ssv6x5x/Kconfig
new file mode 100755
index 000000000..ebfe6153f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Kconfig
@@ -0,0 +1,8 @@
+#menu "iComm-semi 6X5X WLAN support"
+config SSV6X5X
+ tristate "SSV6X5X Wireless driver"
+ depends on MAC80211 && MMC
+ ---help---
+ Enable iComm-semi SSV6X5X WLAN kernel driver.
+
+#endmenu
diff --git a/drivers/net/wireless/ssv6x5x/Makefile b/drivers/net/wireless/ssv6x5x/Makefile
new file mode 100755
index 000000000..d3821b37f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile
@@ -0,0 +1,142 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate include/ssv_conf_parser.h
+# GEN_CONF_PARSER := $(shell cd $(KBUILD_TOP); env ccflags="$(ccflags-y)" ./parser-conf.sh include/ssv_conf_parser.h)
+# Generate $(KMODULE_NAME)-wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+MODDESTDIR = /lib/modules/$(shell uname -r)/kernel/drivers/net/wireless
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+KERN_SRCS += $(KMODULE_NAME)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+#export CONFIG_SSV6X5X=m
+
+.PHONY: all ver modules clean
+
+all: modules
+
+modules:
+ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+install:
+ install -p -m 644 $(KMODULE_NAME).ko $(MODDESTDIR)
+ /sbin/depmod -a ${KVER}
+
+uninstall:
+ rm -f $(MODDESTDIR)/$(KMODULE_NAME).ko
+ /sbin/depmod -a ${KVER}
+
+clean:
+ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+ rm -fr .tmp_versions
+ rm -fr Module.symvers
+ rm -fr Module.markers
+ rm -fr modules.order
+ rm -fr image/$(KMODULE_NAME)-wifi.cfg
+ cd ssvdevice/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hci/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd smac/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/sdio/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd crypto/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.android b/drivers/net/wireless/ssv6x5x/Makefile.android
new file mode 100755
index 000000000..77988a340
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.android
@@ -0,0 +1,142 @@
+PLATFORMS =
+
+KBUILD_TOP := $(PWD)
+include $(KBUILD_TOP)/platforms/$(PLATFORMS).cfg
+include $(KBUILD_TOP)/platforms/platform-config.mak
+
+PWD := $(shell pwd)
+
+ifeq ($(KERNELRELEASE),)
+# current directory is driver
+CFGDIR = $(PWD)/../../../../config
+
+-include $(CFGDIR)/build_config.cfg
+-include $(CFGDIR)/rules.make
+
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KMODULE_NAME=ssv6xxx
+else
+KMODULE_NAME=ssv6051
+endif
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+#KERNEL_MODULES += crypto
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+
+KERN_SRCS += platforms/$(PLATFORMS)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+all:module strip
+
+module:
+ make -C $(SSV_KERNEL_PATH) ARCH=$(SSV_ARCH) CROSS_COMPILE=$(SSV_CROSS) \
+ EXTRA_CFLAGS="$(EXTRA_CFLAGS)" M=$(PWD) modules
+
+install:
+ install -p -m 644 $(KMODULE_NAME).ko $(KMODDESTDIR)
+
+uninstall:
+ rm -f $(KMODDESTDIR)/$(KMODULE_NAME).ko
+
+strip:
+ #cp eagle.ko $(KO_NAME).ko
+ #cp $(KO_NAME).ko $(DEFAULT_MODULES_DIR)
+ #cp ssv6200.ko $(DEFAULT_MODULES_DIR)
+ cp platforms/$(PLATFORMS)-wifi.cfg image/$(KMODULE_NAME)-wifi.cfg
+ cp $(KMODULE_NAME).ko image/$(KMODULE_NAME).ko
+ cp platforms/cli image
+ifneq ($(SSV_STRIP),)
+ cp $(KMODULE_NAME).ko image/$(KMODULE_NAME)_ori.ko
+ $(SSV_STRIP) --strip-unneeded image/$(KMODULE_NAME).ko
+ #$(SSV_STRIP) --strip-debug image/$(KMODULE_NAME).ko
+endif
+
+clean:
+ make -C $(SSV_KERNEL_PATH) ARCH=$(SSV_ARCH) CROSS_COMPILE=$(SSV_CROSS) \
+ M=$(PWD) clean
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.cross_linux b/drivers/net/wireless/ssv6x5x/Makefile.cross_linux
new file mode 100755
index 000000000..16148bf63
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.cross_linux
@@ -0,0 +1,140 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate include/ssv_conf_parser.h
+# GEN_CONF_PARSER := $(shell cd $(KBUILD_TOP); env ccflags="$(ccflags-y)" ./parser-conf.sh include/ssv_conf_parser.h)
+# Generate $(KMODULE_NAME)-wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+KERN_SRCS += $(KMODULE_NAME)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+#export CONFIG_SSV6X5X=m
+
+.PHONY: all ver modules clean
+
+all: modules
+
+modules:
+ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+#install:
+# install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
+# /sbin/depmod -a ${KVER}
+#
+#uninstall:
+# rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
+# /sbin/depmod -a ${KVER}
+
+clean:
+ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+ rm -fr .tmp_versions
+ rm -fr Module.symvers
+ rm -fr Module.markers
+ rm -fr modules.order
+ rm -fr image/$(KMODULE_NAME)-wifi.cfg
+ cd ssvdevice/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hci/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd smac/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/sdio/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd crypto/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux b/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux
new file mode 100755
index 000000000..e35ffa532
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux
@@ -0,0 +1,57 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate -wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell touch $(DEF_PARSER_H))
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+obj-$(CONFIG_SSV6XXX) := $(KMODULE_NAME).o
+$(KMODULE_NAME)-objs := $(KMODULE_NAME)-generic-wlan.o lib.a
+
+.PHONY: all modules clean
+
+all: modules
+
+modules:
+ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+#install:
+# install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
+# /sbin/depmod -a ${KVER}
+#
+#uninstall:
+# rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
+# /sbin/depmod -a ${KVER}
+
+clean:
+ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+ rm -fr .tmp_versions
+ rm -fr Module.symvers
+ rm -fr Module.markers
+ rm -fr modules.order
+ rm -fr image/$(KMODULE_NAME)-wifi.cfg
+ cd ssvdevice/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hci/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd smac/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd hwif/sdio/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd crypto/; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ rm -fr lib.a
+ rm $(DEF_PARSER_H)
diff --git a/drivers/net/wireless/ssv6x5x/README.md b/drivers/net/wireless/ssv6x5x/README.md
new file mode 100644
index 000000000..992cf0101
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/README.md
@@ -0,0 +1,10 @@
+ssv6x5x driver adapter to compile and work in rockchip linux 4.4 kernel, mainly for rk322x SoCs
+
+To compile on the board:
+
+source ./vars
+make -j4
+make install
+
+Otherwise put this in kernel tree in /driver/net/wireless/ssv6x5x, adapt the Kconfig and Makefile
+and then compile the kernel as usual
diff --git a/drivers/net/wireless/ssv6x5x/android-build.sh b/drivers/net/wireless/ssv6x5x/android-build.sh
new file mode 100755
index 000000000..4a8bed51a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/android-build.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+ "h8" \
+ "h3" \
+ "rk3036" \
+ "rk3126" \
+ "rk3128" \
+ "rk322x" \
+ "atm7039-action" \
+ "aml-s905" \
+ "aml-s805" \
+ "x1000" \
+ "t10" \
+ "xml-hi3518")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do
+ case "$REPLY" in
+
+ 1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 5 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 6 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 7 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 8 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 9 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 10 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 11 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 12 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 13 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+ $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+ *) echo "Invalid option. Try another one.";continue;;
+ esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+ echo "Please check SVN first !!"
+else
+mv Makefile Makefile.org
+cp Makefile.android Makefile
+sed -i 's,PLATFORMS =,PLATFORMS = '"$PLATFORM"',g' Makefile
+make clean
+make
+mv -f Makefile.org Makefile
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/ap.cfg b/drivers/net/wireless/ssv6x5x/ap.cfg
new file mode 100755
index 000000000..9901ae0fd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap.cfg
@@ -0,0 +1,52 @@
+ssid=testMssyAP
+channel=40
+
+#5G mode
+hw_mode=a
+ht_capab=[SHORT-GI-20][RX-STBC1][HT40-][SHORT-GI-40]
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+#[40-INTOLERANT]
+
+#DFS
+country_code=US
+ieee80211d=1
+
+#2G mode
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+
+#OPEN
+ieee80211n=1
+
+##WEP
+#wep_default_key=0
+##5 characters
+#wep_key0="aaaaa"
+##13 characters
+##wep_key0="aaaaaaaaaaaaa"
+
+
+##WPA
+#wpa=1
+#wpa_key_mgmt=WPA-PSK
+#rsn_pairwise=TKIP
+#wpa_passphrase=12345678
+
+
+
+##WPA2
+#ieee80211n=1
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+#wpa=2
+#wpa_key_mgmt=WPA-PSK
+#rsn_pairwise=CCMP
+## WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+## secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+## (8..63 characters) that will be converted to PSK. This conversion uses SSID
+## so the PSK changes when ASCII passphrase is used and the SSID is changed.
+## wpa_psk (dot11RSNAConfigPSKValue)
+## wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+##wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+#wpa_passphrase=12345678
+
+
+
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/ap_check.sh b/drivers/net/wireless/ssv6x5x/ap_check.sh
new file mode 100755
index 000000000..a5de18076
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_check.sh
@@ -0,0 +1,97 @@
+#! /bin/bash
+
+
+
+HOSTPAD_DIR=../hostapd/hostapd/
+BLUE='\e[1;34m'
+GREEN='\e[1;32m'
+CYAN='\e[1;36m'
+RED='\e[1;31m'
+PURPLE='\e[1;35m'
+YELLOW='\e[1;33m'
+# No Color
+NC='\e[0m'
+
+
+check_package(){
+ for i in {1..5}
+ do
+ echo -en "${GREEN}Check package - $1...${NC}"
+ status=$(dpkg -s $1 | grep "Status: install ok installed")
+ if [ "$status" == "" ]; then
+ echo -e "${PURPLE}Try to intall package $1...${NC}"
+ apt-get install -y $1
+ retval=2
+ else
+ echo -e "${GREEN}OK${NC}"
+ retval=1
+ break;
+ fi
+ done
+ return "$retval"
+}
+
+check_dhcp_server_config(){
+
+ dhcp_config_file="/etc/dhcp/dhcpd.conf"
+ echo -en "${YELLOW}Check DHCPD config...${NC}"
+ dhcp_config=$(grep "subnet 192.168.0.0 netmask 255.255.255.0" $dhcp_config_file)
+
+ if [ "$dhcp_config" == "" ]; then
+ echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+ echo "subnet 192.168.0.0 netmask 255.255.255.0" >> $dhcp_config_file
+ echo "{" >> $dhcp_config_file
+ echo " range 192.168.0.2 192.168.0.10;" >> $dhcp_config_file
+ echo " option routers 192.168.0.1;" >> $dhcp_config_file
+ echo " option domain-name-servers 168.95.1.1;" >> $dhcp_config_file
+ echo "}" >> $dhcp_config_file
+
+ echo -e "${YELLOW}OK${NC}"
+ else
+ echo -e "${YELLOW}OK${NC}"
+ fi
+}
+
+
+
+
+check()
+{
+ check_package $1
+ ret=$?
+ if test $ret -eq 2
+ then
+ echo -e "${RED}#############FAIL to CHECK PACKAGE for AP MODE#############${NC}"
+ exit 0;
+ fi
+}
+
+#############################################==MAIN==#############################################
+#
+if [ ! -d "$HOSTPAD_DIR" ]; then
+ echo -e "${RED}#############HOSTPAD needs to be put at the same level of the wireless driver#############${NC}"
+ exit 0;
+fi
+
+
+#
+echo -e "${YELLOW}Check internet access...${NC}"
+wget --spider http://www.google.com
+
+if [ "$?" != 0 ]; then
+ echo -e "${RED}Please connect to internet firstly......${NC}"
+ exit 0;
+fi
+
+#
+echo -e "${YELLOW}Check necessary packages to run AP mode${NC}"
+check libnl1
+check libnl-dev
+check libssl-dev
+check isc-dhcp-server
+check_dhcp_server_config
+
+#
+cd $HOSTPAD_DIR
+make
+
diff --git a/drivers/net/wireless/ssv6x5x/ap_launch.sh b/drivers/net/wireless/ssv6x5x/ap_launch.sh
new file mode 100755
index 000000000..a34897c90
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_launch.sh
@@ -0,0 +1,124 @@
+#! /bin/bash
+
+BLUE='\e[1;34m'
+GREEN='\e[1;32m'
+CYAN='\e[1;36m'
+RED='\e[1;31m'
+PURPLE='\e[1;35m'
+YELLOW='\e[1;33m'
+# No Color
+NC='\e[0m'
+
+
+HOSTPAD_DIR=../hostapd/hostapd
+
+./ap_shutdown.sh
+
+dir=$(pwd)
+chmod 777 -R $HOSTPAD_DIR
+cd $HOSTPAD_DIR
+
+PID=$!
+wait $PID
+sleep 2
+
+
+cd $dir
+echo -e "${YELLOW}Load wireless driver...${NC}"
+./load.sh
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Detect wireless device...${NC}"
+sleep 2
+#get driver mac address
+macAddr=$(cat sta.cfg| grep "hw_mac"|sed 1q |tr -d ' '|tail -c 18)
+echo "device macaddr=[$macAddr]"
+
+#get driver name(wlan??)
+#devName=$(ifconfig | grep $macAddr)
+devName=$(ifconfig -a | grep -i $macAddr)
+devName=`echo $devName| cut -d ' ' -f 1`
+
+ifconfig $devName > /dev/null
+
+if [ $? -ne 0 ]; then
+ echo -e "${RED}Device $devName does not exist.${NC}"
+ exit 1;
+else
+ echo -e "${YELLOW}Device is $devName.${NC}"
+fi
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+#rm -rf load_dhcp.sh
+#rm -rf hostapd.conf
+#relpace wlan@@ to real device name
+cp script/template/load_dhcp.sh load_dhcp.sh
+#cp script/template/hostapd.conf hostapd.conf
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$devName/" load_dhcp.sh
+sed -i "s/wlan@@/$devName/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+#move to right position
+#mv load_dhcp.sh $HOSTPAD_DIR
+#mv hostapd.conf $HOSTPAD_DIR/hostapd/
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$devName" $dhcp_config_file)
+if [ "$dhcp_config" != "$devName" ]; then
+ echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+
+ rm -rf tmp
+ sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+ echo "INTERFACES=\"$devName\"" >>tmp
+ rm -rf $dhcp_config_file
+ mv tmp /etc/default/isc-dhcp-server
+
+ echo -e "${YELLOW}OK${NC}"
+fi
+
+
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+# popd
+ if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi on
+ else
+ nmcli nm wifi on
+ fi
+
+ echo -e "${YELLOW}Shutting down AP.${NC}"
+ ./ap_shutdown.sh
+}
+
+if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi off
+else
+ nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+#pushd $HOSTPAD_DIR
+#. ./load_ap.sh
+#$HOSTPAD_DIR/load_dhcp.sh &
+./load_dhcp.sh &
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd -t hostapd.conf
+#hostapd -t hostapd.conf
diff --git a/drivers/net/wireless/ssv6x5x/ap_shutdown.sh b/drivers/net/wireless/ssv6x5x/ap_shutdown.sh
new file mode 100755
index 000000000..376f45f91
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_shutdown.sh
@@ -0,0 +1,17 @@
+#! /bin/bash
+
+echo "@@Unload hostapd..."
+dir=$(pwd)
+
+HOSTPAD_DIR=../hostapd
+
+$HOSTPAD_DIR/unload_ap.sh
+
+echo "@@Unload wireless driver..."
+sleep 1
+
+./unload.sh
+
+
+
+
diff --git a/drivers/net/wireless/ssv6x5x/bridge/Kconfig b/drivers/net/wireless/ssv6x5x/bridge/Kconfig
new file mode 100755
index 000000000..f685f75e9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/Kconfig
@@ -0,0 +1,17 @@
+config SSV_SDIO_BRIDGE_HW
+ tristate
+ default m
+ depends on MMC
+ ---help---
+ This option enables the SDIO bus support in ssvcabrio.
+
+ Say Y, if you have a ssv SDIO device.
+
+config SSV_SDIO_BRIDGE_DEBUGFS
+ bool "SSV ssvsdiobridge debugging"
+ depends on DEBUG_FS
+ ---help---
+ Say Y, if you need access to ssvsdiobridge's statistics.
+
+ Also required for changing debug message flags at run time.
+
diff --git a/drivers/net/wireless/ssv6x5x/bridge/Makefile b/drivers/net/wireless/ssv6x5x/bridge/Makefile
new file mode 100755
index 000000000..e6d3026aa
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/Makefile
@@ -0,0 +1,22 @@
+ifeq ($(KBUILD_TOP),)
+ ifneq ($(KBUILD_EXTMOD),)
+ KBUILD_DIR := $(KBUILD_EXTMOD)
+ else
+ KBUILD_DIR := $(PWD)
+ endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+#Define CONFIG_CABRIO_DEBUG to show debug messages
+ccflags-y += -DCONFIG_CABRIO_DEBUG
+
+KMODULE_NAME=ssv6200_sdiobridge
+KERN_SRCS := sdiobridge.c
+KERN_SRCS += debug.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/bridge/aaa.mk b/drivers/net/wireless/ssv6x5x/bridge/aaa.mk
new file mode 100755
index 000000000..0284a5148
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/aaa.mk
@@ -0,0 +1,27 @@
+#aaa.mk - what is this used for?
+
+obj-m += ssvsdiobridge.o
+
+ssvsdiobridge-y += sdiobridge.o
+ssvsdiobridge-y += debug.o
+
+
+
+#Define CONFIG_CABRIO_DEBUG to show debug messages
+ccflags-y += -DCONFIG_CABRIO_DEBUG
+
+ifndef ($(KBUILD_EXTMOD),)
+KDIR=/lib/modules/`uname -r`/build
+
+_all:
+ $(MAKE) -C $(KDIR) M=$(PWD) KBUILD_EXTRA_SYMBOLS=$(PWD)/../ssvdevice/Module.symvers modules 2>&1 | tee make.log
+clean:
+ $(MAKE) -C $(KDIR) M=$(PWD) clean
+ rm -f make.log
+
+install:
+ @-rmmod ssvsdiobridge
+ $(MAKE) INSTALL_MOD_DIR=kernel/drivers/net/wireless/ssv6200 -C $(KDIR) M=$(PWD) modules_install
+ modprobe ssvsdiobridge
+
+endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/debug.c b/drivers/net/wireless/ssv6x5x/bridge/debug.c
new file mode 100644
index 000000000..3f3b95507
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/debug.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include "debug.h"
+int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue)
+{
+ glue->debugfs = debugfs_create_dir("tu_ssv",
+ NULL);
+ if (!glue->debugfs)
+ return -ENOMEM;
+ glue->dump_entry = debugfs_create_bool("sdiobridge_dump", S_IRUSR, glue->debugfs, &glue->dump);
+ return 0;
+}
+void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue)
+{
+ if (!glue->dump_entry)
+ debugfs_remove(glue->dump_entry);
+}
diff --git a/drivers/net/wireless/ssv6x5x/bridge/debug.h b/drivers/net/wireless/ssv6x5x/bridge/debug.h
new file mode 100644
index 000000000..9c1b2badd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/debug.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef DEBUG_H
+#define DEBUG_H
+#include "sdiobridge.h"
+#include
+int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue);
+void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/make.log b/drivers/net/wireless/ssv6x5x/bridge/make.log
new file mode 100755
index 000000000..acdaa681e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/make.log
@@ -0,0 +1,7 @@
+make[1]: Entering directory `/usr/src/linux-headers-3.2.0-48-generic'
+ CC [M] /root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.o
+/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.c:44:33: fatal error: ../include/sdio_def.h: No such file or directory
+compilation terminated.
+make[2]: *** [/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.o] Error 1
+make[1]: *** [_module_/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge] Error 2
+make[1]: Leaving directory `/usr/src/linux-headers-3.2.0-48-generic'
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c
new file mode 100644
index 000000000..937699541
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c
@@ -0,0 +1,982 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdiobridge.h"
+#include "debug.h"
+#define BLOCKSIZE 0x40
+#define RXBUFLENGTH 1024*3
+#define RXBUFSIZE 512
+enum ssvcabrio_int {
+ SSVCABRIO_INT_RX = 0x00000001,
+ SSVCABRIO_INT_TX = 0x00000002,
+ SSVCABRIO_INT_GPIO = 0x00000004,
+ SSVCABRIO_INT_SYS = 0x00000008,
+};
+#define CHECK_RET(_fun) \
+ do { \
+ if (0 != _fun) \
+ printk("File = %s\nLine = %d\nFunc=%s\nDate=%s\nTime=%s\n", __FILE__, __LINE__, __FUNCTION__, __DATE__, __TIME__); \
+ } while (0)
+static unsigned int ssv_sdiobridge_ioctl_major = 0;
+static unsigned int num_of_dev = 1;
+static struct cdev ssv_sdiobridge_ioctl_cdev;
+static struct class *fc;
+static struct ssv_sdiobridge_glue *glue;
+struct ssv_rxbuf {
+ struct list_head list;
+ u32 rxsize;
+ u8 rxdata[RXBUFLENGTH];
+};
+static const struct sdio_device_id ssv_sdiobridge_devices[] = {
+ {SDIO_DEVICE(MANUFACTURER_SSV_CODE, (MANUFACTURER_ID_CABRIO_BASE | 0x0))},
+ {}
+};
+MODULE_DEVICE_TABLE(sdio, ssv_sdiobridge_devices);
+static long ssv_sdiobridge_ioctl_getFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->out_data_len < 1) {
+ retval = -1;
+ } else {
+ u8 out_data = glue->funcFocus;
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data, &out_data, sizeof(out_data)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_setFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ int retval =0;
+ if ( pcmd_data->out_data_len < 0) {
+ retval = -EFAULT;
+ dev_err(glue->dev, "%s : input length must < 0",__FUNCTION__);
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&glue->funcFocus,(int __user *)compat_ptr((unsigned long)pcmd_data->in_data),sizeof(glue->funcFocus)));
+ } else {
+ CHECK_RET(copy_from_user(&glue->funcFocus,(int __user *)pcmd_data->in_data,sizeof(glue->funcFocus)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_getBusWidth(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->out_data_len < 1) {
+ retval = -1;
+ } else {
+ u8 out_data = 1;
+ if ( func->card->host->ios.bus_width != MMC_BUS_WIDTH_1 ) {
+ out_data = 4;
+ }
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data)));
+ }
+ }
+ return retval;
+}
+#if 0
+static long ssv_sdiobridge_ioctl_setBusWidth(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ int retval =0;
+ struct ssv_sdiobridge_cmd *pData;
+ u8 inData[1];
+ copy_from_user(pData,(int __user *)arg,sizeof(*pData));
+ if ( isCompat ) {
+ copy_from_user(&cmd_data,(int __user *)compat_ptr((unsigned long)pucmd_data),sizeof(*pucmd_data));
+ } else {
+ copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data));
+ }
+ if ( pData->in_data_len < 0) {
+ retval = -EFAULT;
+ dev_err(glue->dev, "%s : input length must > 1",__FUNCTION__);
+ } else {
+ if ( pData->in_data == 1 ) {
+ if ( (func->card->host->caps & MMC_CAP_4_BIT_DATA) && !(func->card->cccr.low_speed && !func->card->cccr.wide_bus) ) {
+ u8 ctrl = sdio_f0_readb(func,SDIO_CCCR_IF,&retval);
+ if (retval)
+ return retval;
+ if (!(ctrl & SDIO_BUS_WIDTH_4BIT))
+ return 0;
+ ctrl &= ~SDIO_BUS_WIDTH_4BIT;
+ ctrl |= SDIO_BUS_ASYNC_INT;
+ sdio_f0_writeb(func,ctrl,SDIO_CCCR_IF,&retval);
+ if (retval)
+ return retval;
+ mmc_set_bus_width(func->card->host, MMC_BUS_WIDTH_1);
+ }
+ } else {
+ if ( func->card->host->ios.bus_width != MMC_BUS_WIDTH_4 ) {
+ }
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_getBlockMode(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->out_data_len < 1) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data));
+ } else {
+ copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_setBlockMode(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->in_data_len < 1) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ copy_from_user(&glue->blockMode,(int __user *)pucmd_data->in_data,sizeof(glue->blockMode));
+ }
+ }
+ return retval;
+}
+#endif
+static long ssv_sdiobridge_ioctl_getBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->out_data_len < 2) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->blockSize,sizeof(glue->blockSize)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->blockSize,sizeof(glue->blockSize)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_setBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->in_data_len < 2) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&glue->blockSize,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->blockSize)));
+ } else {
+ CHECK_RET(copy_from_user(&glue->blockSize,(int __user *)pucmd_data->in_data,sizeof(glue->blockSize)));
+ }
+ dev_err(glue->dev,"%s: blockSize [%d]\n",__FUNCTION__,glue->blockSize);
+ sdio_claim_host(func);
+ sdio_set_block_size(func,glue->blockSize);
+ sdio_release_host(func);
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_readByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->out_data_len < 4) {
+ retval = -1;
+ } else {
+ u32 address;
+ u8 out_data;
+ int ret = 0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&address,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(address)));
+ } else {
+ CHECK_RET(copy_from_user(&address,(int __user *)pucmd_data->in_data,sizeof(address)));
+ }
+ sdio_claim_host(func);
+ if ( glue->funcFocus == 0 ) {
+ out_data = sdio_f0_readb(func, address, &ret);
+ } else {
+ out_data = sdio_readb(func, address, &ret);
+ }
+ sdio_release_host(func);
+ dev_err(glue->dev,"%s: [%X] [%02X] ret:[%d]\n",__FUNCTION__,address,out_data,ret);
+ if ( !ret ) {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((void *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data)));
+ }
+ } else {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_writeByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->in_data_len < 5) {
+ retval = -1;
+ } else {
+ u8 tmp[5];
+ u32 address;
+ u8 data;
+ int ret = 0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(tmp,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmp)));
+ } else {
+ CHECK_RET(copy_from_user(tmp,(int __user *)pucmd_data->in_data,sizeof(tmp)));
+ }
+ address = *((u32 *)tmp);
+ data = tmp[4];
+ sdio_claim_host(func);
+ if ( glue->funcFocus == 0 ) {
+ sdio_f0_writeb(func,data, address, &ret);
+ } else {
+ sdio_writeb(func,data, address, &ret);
+ }
+ sdio_release_host(func);
+ if ( ret ) {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_getMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->out_data_len < 4) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->dataIOPort,sizeof(glue->dataIOPort)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->dataIOPort,sizeof(glue->dataIOPort)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_setMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->in_data_len < 4) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&glue->dataIOPort,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->dataIOPort)));
+ } else {
+ CHECK_RET(copy_from_user(&glue->dataIOPort,(int __user *)pucmd_data->in_data,sizeof(glue->dataIOPort)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_readMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ u8 *tmpdata;
+ int ret;
+ int readsize;
+ tmpdata = kzalloc(pcmd_data->out_data_len, GFP_KERNEL);
+ if ( tmpdata == NULL ) {
+ dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,pcmd_data->out_data_len);
+ return -1;
+ }
+ readsize = sdio_align_size(func,pcmd_data->out_data_len);
+ sdio_claim_host(func);
+ ret = sdio_memcpy_fromio(func, tmpdata,glue->dataIOPort, readsize );
+ sdio_release_host(func);
+ if (unlikely(glue->dump)) {
+ printk(KERN_DEBUG "%s: READ data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)pcmd_data->out_data_len,readsize);
+ print_hex_dump(KERN_DEBUG, "ssv_sdio: READ ",
+ DUMP_PREFIX_OFFSET, 16, 1,
+ tmpdata, pcmd_data->out_data_len, false);
+ }
+ if ( !ret ) {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),tmpdata,pcmd_data->out_data_len));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,tmpdata,pcmd_data->out_data_len));
+ }
+ } else {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ kfree(tmpdata);
+ dev_err(glue->dev,"%s(): %d\n", __FUNCTION__, ret);
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_writeMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ u8 *tmpdata;
+ int ret;
+ int readsize ;
+ tmpdata = kzalloc(pcmd_data->in_data_len, GFP_KERNEL);
+ if ( tmpdata == NULL ) {
+ dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,pcmd_data->out_data_len);
+ return -1;
+ }
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),pcmd_data->in_data_len));
+ } else {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,pcmd_data->in_data_len));
+ }
+ readsize = sdio_align_size(func,pcmd_data->in_data_len);
+ if (unlikely(glue->dump)) {
+ printk(KERN_DEBUG "%s: READ data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)pcmd_data->in_data_len,readsize);
+ print_hex_dump(KERN_DEBUG, "ssv_sdio: WRITE ",
+ DUMP_PREFIX_OFFSET, 16, 1,
+ tmpdata, pcmd_data->in_data_len, false);
+ }
+ sdio_claim_host(func);
+ ret = sdio_memcpy_toio(func, glue->dataIOPort,tmpdata, readsize);
+ sdio_release_host(func);
+ if ( ret ) {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ kfree(tmpdata);
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_getMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->out_data_len < 4) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->regIOPort,sizeof(glue->regIOPort)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->regIOPort,sizeof(glue->regIOPort)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_setMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->in_data_len < 4) {
+ retval = -1;
+ } else {
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&glue->regIOPort,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->regIOPort)));
+ } else {
+ CHECK_RET(copy_from_user(&glue->regIOPort,(int __user *)pucmd_data->in_data,sizeof(glue->regIOPort)));
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_readReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->in_data_len < 4 || pcmd_data->out_data_len < 4) {
+ retval = -1;
+ } else {
+ u8 tmpdata[4];
+ int ret = 0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+ } else {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+ }
+ sdio_claim_host(func);
+ dev_err(glue->dev,"%s: read reg 1 [%02X][%02X][%02X][%02X]\n",__FUNCTION__,tmpdata[0],tmpdata[1],tmpdata[2],tmpdata[3]);
+ ret = sdio_memcpy_toio(func, glue->regIOPort, tmpdata, 4);
+ ret = sdio_memcpy_fromio(func, tmpdata, glue->regIOPort, 4);
+ sdio_release_host(func);
+ dev_err(glue->dev,"%s: read reg 2 [%02X][%02X][%02X][%02X] ret:%d\n",__FUNCTION__,tmpdata[0],tmpdata[1],tmpdata[2],tmpdata[3],ret);
+ if ( !ret ) {
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),tmpdata,sizeof(tmpdata)));
+ } else {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,tmpdata,sizeof(tmpdata)));
+ }
+ } else {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static long ssv_sdiobridge_ioctl_writeReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ long retval =0;
+ if ( pcmd_data->in_data_len < 8) {
+ retval = -1;
+ } else {
+ u8 tmpdata[8];
+ int ret = 0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+ } else {
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+ }
+ dev_err(glue->dev,"%s: write reg ADR[%02X%02X%02X%02X] [%02X][%02X][%02X][%02X]\n",__FUNCTION__,tmpdata[3],tmpdata[2],tmpdata[1],tmpdata[0],
+ tmpdata[7], tmpdata[6], tmpdata[5], tmpdata[4]);
+ sdio_claim_host(func);
+ ret = sdio_memcpy_toio(func, glue->regIOPort, tmpdata, 8);
+ sdio_release_host(func);
+ if ( ret ) {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static int ssv_sdiobridge_device_open(struct inode *inode, struct file *filp)
+{
+ dev_err(glue->dev,"%s():\n", __FUNCTION__);
+ filp->private_data = glue;
+ return 0;
+}
+static int ssv_sdiobridge_device_close(struct inode *inode, struct file *filp)
+{
+ dev_err(glue->dev,"%s():\n", __FUNCTION__);
+ return 0;
+}
+static long ssv_sdiobridge_device_ioctl_process(struct ssv_sdiobridge_glue *glue, unsigned int cmd, struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+ struct ssv_sdiobridge_cmd cmd_data;
+ long retval=0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+ } else {
+ CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+ }
+#if 0
+#ifdef __x86_64
+ dev_err(glue->dev,"%s: isCompat[%d] [%lX] [%lX] [%X] \n",__FUNCTION__,isCompat,IOCTL_SSVSDIO_GET_FUNCTION_FOCUS,IOCTL_SSVSDIO_READ_DATA,cmd);
+#else
+ dev_err(glue->dev,"%s: isCompat[%d] [%X] [%X] [%X] \n",__FUNCTION__,isCompat,IOCTL_SSVSDIO_GET_FUNCTION_FOCUS,IOCTL_SSVSDIO_READ_DATA,cmd);
+#endif
+#endif
+ switch (cmd) {
+ case IOCTL_SSVSDIO_GET_FUNCTION_FOCUS:
+ retval = ssv_sdiobridge_ioctl_getFuncfocus(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_SET_FUNCTION_FOCUS:
+ retval = ssv_sdiobridge_ioctl_setFuncfocus(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_GET_BUS_WIDTH:
+ retval = ssv_sdiobridge_ioctl_getBusWidth(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+#if 0
+ case IOCTL_SSVSDIO_SET_BUS_WIDTH:
+ retval = ssv_sdiobridge_ioctl_setBusWidth(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_GET_BUS_CLOCK:
+ break;
+ case IOCTL_SSVSDIO_SET_BUS_CLOCK:
+ break;
+ case IOCTL_SSVSDIO_GET_BLOCK_MODE:
+ retval = ssv_sdiobridge_ioctl_getBlockMode(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_SET_BLOCK_MODE:
+ retval = ssv_sdiobridge_ioctl_setBlockMode(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+#endif
+ case IOCTL_SSVSDIO_GET_BLOCKLEN:
+ retval = ssv_sdiobridge_ioctl_getBlockSize(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_SET_BLOCKLEN:
+ retval = ssv_sdiobridge_ioctl_setBlockSize(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_READ_BYTE:
+ retval = ssv_sdiobridge_ioctl_readByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_WRITE_BYTE:
+ retval = ssv_sdiobridge_ioctl_writeByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT:
+ retval = ssv_sdiobridge_ioctl_getMultiByteIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT:
+ retval = ssv_sdiobridge_ioctl_setMultiByteIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_READ_MULTI_BYTE:
+ retval = ssv_sdiobridge_ioctl_readMultiByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_WRITE_MULTI_BYTE:
+ retval = ssv_sdiobridge_ioctl_writeMultiByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT:
+ retval = ssv_sdiobridge_ioctl_getMultiByteRegIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT:
+ retval = ssv_sdiobridge_ioctl_setMultiByteRegIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_READ_REG:
+ retval = ssv_sdiobridge_ioctl_readReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_WRITE_REG:
+ retval = ssv_sdiobridge_ioctl_writeReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ }
+ return retval;
+}
+static long ssv_sdiobridge_device_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct ssv_sdiobridge_glue *glue =filp->private_data;
+ long retval=0;
+ struct ssv_sdiobridge_cmd *pucmd_data;
+ pucmd_data = (struct ssv_sdiobridge_cmd *)arg;
+ retval = ssv_sdiobridge_device_ioctl_process( glue,cmd,pucmd_data,true);
+ return retval;
+}
+static long ssv_sdiobridge_device_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct ssv_sdiobridge_glue *glue =filp->private_data;
+ long retval=0;
+ struct ssv_sdiobridge_cmd *pucmd_data;
+ pucmd_data = (struct ssv_sdiobridge_cmd *)arg;
+ retval = ssv_sdiobridge_device_ioctl_process( glue,cmd,pucmd_data,false);
+ return retval;
+}
+static bool ssv_sdiobridge_have_data(struct ssv_sdiobridge_glue *glue)
+{
+ dev_err(glue->dev,"%s(): !list_empty(&glue->rxreadybuf)[%d]\n", __FUNCTION__,!list_empty(&glue->rxreadybuf));
+ return !list_empty(&glue->rxreadybuf);
+}
+static ssize_t ssv_sdiobridge_device_read(struct file *filp,
+ char *buffer,
+ size_t length,
+ loff_t *offset)
+{
+ struct ssv_sdiobridge_glue *glue =filp->private_data;
+ struct ssv_rxbuf *bf;
+ int copylength;
+ dev_err(glue->dev,"%s():\n", __FUNCTION__);
+ spin_lock_bh(&glue->rxbuflock);
+ if (list_empty(&glue->rxreadybuf)) {
+ spin_unlock_bh(&glue->rxbuflock);
+ dev_err(glue->dev,"%s():no data for read \n", __FUNCTION__);
+#if 1
+ if ( wait_event_interruptible(glue->read_wq, ssv_sdiobridge_have_data(glue))!=0) {
+ dev_err(glue->dev,"%s():not get data ?? \n", __FUNCTION__);
+ return -1;
+ }
+#else
+ wait_event(glue->read_wq,ssv_sdiobridge_have_data(glue));
+#endif
+ spin_lock_bh(&glue->rxbuflock);
+ if (list_empty(&glue->rxreadybuf)) {
+ spin_unlock_bh(&glue->rxbuflock);
+ dev_err(glue->dev,"%s():stop ?? \n", __FUNCTION__);
+ return -1;
+ }
+ }
+ bf = list_first_entry(&glue->rxreadybuf, struct ssv_rxbuf, list);
+ list_del(&bf->list);
+ spin_unlock_bh(&glue->rxbuflock);
+ copylength = min(bf->rxsize,(u32)length);
+ CHECK_RET(copy_to_user((int __user *)buffer,bf->rxdata,copylength));
+ dev_err(glue->dev,"%s():get rx data : data len:[%d], user read len:[%d],real read len:[%d] \n", __FUNCTION__,bf->rxsize,(u32)length,copylength);
+ spin_lock_bh(&glue->rxbuflock);
+ list_add_tail(&bf->list, &glue->rxbuf);
+ spin_unlock_bh(&glue->rxbuflock);
+ return copylength;
+}
+static ssize_t ssv_sdiobridge_device_write(struct file *filp,
+ const char *buff,
+ size_t len,
+ loff_t *off)
+{
+ struct ssv_sdiobridge_glue *glue =filp->private_data;
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ u8 *tmpdata;
+ int ret;
+ dev_err(glue->dev,"%s():\n", __FUNCTION__);
+ tmpdata = kzalloc(len, GFP_KERNEL);
+ if ( tmpdata == NULL ) {
+ dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,(u32)len);
+ return -1;
+ }
+ CHECK_RET(copy_from_user(tmpdata,(int __user *)buff,len));
+ if (unlikely(glue->dump)) {
+ printk(KERN_DEBUG "%s: WRITE data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)len,sdio_align_size(func,len));
+ print_hex_dump(KERN_DEBUG, "ssv_sdio: WRITE ",
+ DUMP_PREFIX_OFFSET, 16, 1,
+ tmpdata, len, false);
+ }
+ sdio_claim_host(func);
+ ret = sdio_memcpy_toio(func, glue->dataIOPort,tmpdata, sdio_align_size(func,len));
+ sdio_release_host(func);
+ kfree(tmpdata);
+ if ( ret ) {
+ dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+ return -1;
+ }
+ return len;
+}
+struct file_operations fops = {
+ .owner = THIS_MODULE,
+ .read = ssv_sdiobridge_device_read,
+ .write = ssv_sdiobridge_device_write,
+ .open = ssv_sdiobridge_device_open,
+ .release = ssv_sdiobridge_device_close,
+ .compat_ioctl = ssv_sdiobridge_device_compat_ioctl,
+ .unlocked_ioctl = ssv_sdiobridge_device_ioctl
+};
+static void ssv_sdiobridge_irq_process(struct sdio_func *func,
+ struct ssv_sdiobridge_glue *glue)
+{
+ int err_ret;
+ u8 status;
+ sdio_claim_host(func);
+ status = sdio_readb(func, REG_INT_STATUS, &err_ret);
+ if ( status & SSVCABRIO_INT_RX ) {
+ struct ssv_rxbuf *bf;
+ int readsize;
+ spin_lock_bh(&glue->rxbuflock);
+ if (list_empty(&glue->rxbuf)) {
+ spin_unlock_bh(&glue->rxbuflock);
+ sdio_release_host(func);
+ dev_err(glue->dev, "ssv_sdiobridge_irq_process no avaible rx buf list??\n");
+ return;
+ } else {
+ bf = list_first_entry(&glue->rxbuf, struct ssv_rxbuf, list);
+ list_del(&bf->list);
+ }
+ spin_unlock_bh(&glue->rxbuflock);
+ bf->rxsize = (int)(sdio_readb(func, REG_CARD_PKT_LEN_0, &err_ret)&0xff);
+ dev_err(glue->dev, "sdio read rx size[%08x] 0x10[%02x]\n",bf->rxsize, sdio_readb(func, REG_CARD_PKT_LEN_0, &err_ret)&0xff);
+ bf->rxsize = bf->rxsize | ((sdio_readb(func, REG_CARD_PKT_LEN_1, &err_ret)&0xff)<<0x8);
+ readsize = sdio_align_size(func,bf->rxsize);
+ dev_err(glue->dev, "sdio read rx size[%08x] 0x11[%02x] readsize[%d]\n",bf->rxsize, sdio_readb(func, REG_CARD_PKT_LEN_1, &err_ret)&0xff,readsize);
+ err_ret = sdio_memcpy_fromio(func, bf->rxdata, glue->dataIOPort, readsize);
+ sdio_release_host(func);
+ dev_err(glue->dev, "ssv_sdiobridge_irq_process read 53, %d bytes ret:[%d]\n", readsize,err_ret );
+ if (unlikely(glue->dump)) {
+ printk(KERN_DEBUG "ssv_sdiobridge_irq_process: READ data address[%08x] len[%d] readsize[%d]\n",glue->dataIOPort,(int)bf->rxsize,readsize);
+ print_hex_dump(KERN_DEBUG, "ssv_sdio: READ ",
+ DUMP_PREFIX_OFFSET, 16, 1,
+ bf->rxdata, bf->rxsize, false);
+ }
+ if (WARN_ON(err_ret)) {
+ dev_err(glue->dev, "ssv_sdiobridge_irq_process read failed (%d)\n", err_ret);
+ spin_lock_bh(&glue->rxbuflock);
+ list_add_tail(&bf->list, &glue->rxbuf);
+ spin_unlock_bh(&glue->rxbuflock);
+ } else {
+ spin_lock_bh(&glue->rxbuflock);
+ list_add_tail(&bf->list, &glue->rxreadybuf);
+ wake_up(&glue->read_wq);
+ spin_unlock_bh(&glue->rxbuflock);
+ }
+ } else {
+ sdio_release_host(func);
+ }
+}
+static void ssv_sdiobridge_irq_handler(struct sdio_func *func)
+{
+ struct ssv_sdiobridge_glue *glue = sdio_get_drvdata(func);
+ dev_err(&func->dev, "ssv_sdiobridge_irq_handler\n");
+ WARN_ON(glue == NULL);
+ if ( glue != NULL ) {
+ atomic_set(&glue->irq_handling, 1);
+ ssv_sdiobridge_irq_process(func,glue);
+ atomic_set(&glue->irq_handling, 0);
+ wake_up(&glue->irq_wq);
+ }
+}
+static void ssv_sdiobridge_irq_enable(struct sdio_func *func,
+ struct ssv_sdiobridge_glue *glue)
+{
+ int ret;
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ dev_err(glue->dev, "ssv_sdiobridge_irq_enable\n");
+ ret = sdio_claim_irq(func, ssv_sdiobridge_irq_handler);
+ if (ret)
+ dev_err(glue->dev, "Failed to claim sdio irq: %d\n", ret);
+ sdio_release_host(func);
+}
+static bool ssv_sdiobridge_is_on_irq(struct ssv_sdiobridge_glue *glue)
+{
+ return !atomic_read(&glue->irq_handling);
+}
+static void ssv_sdiobridge_irq_disable(struct ssv_sdiobridge_glue *glue,bool iswaitirq)
+{
+ struct sdio_func *func;
+ int ret;
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable1\n");
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable2 [%d]\n",atomic_read(&glue->irq_handling));
+ if (atomic_read(&glue->irq_handling)&&iswaitirq) {
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable3\n");
+ sdio_release_host(func);
+ ret = wait_event_interruptible(glue->irq_wq,
+ ssv_sdiobridge_is_on_irq(glue));
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable4 ret[%d]\n",ret);
+ if (ret)
+ return;
+ sdio_claim_host(func);
+ }
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable5\n");
+ ret = sdio_release_irq(func);
+ if (ret)
+ dev_err(glue->dev, "Failed to release sdio irq: %d\n", ret);
+ dev_err(glue->dev, "ssv_sdiobridge_irq_disable6\n");
+ sdio_release_host(func);
+ }
+}
+#if 0
+static void ssv_sdiobridge_irq_sync(struct device *child)
+{
+ struct ssv_sdiobridge_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ int ret;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ if (atomic_read(&glue->irq_handling)) {
+ sdio_release_host(func);
+ ret = wait_event_interruptible(glue->irq_wq,
+ ssv_sdiobridge_is_on_irq(glue));
+ if (ret)
+ return;
+ sdio_claim_host(func);
+ }
+ sdio_release_host(func);
+ }
+}
+#endif
+static void ssv_sdiobridge_read_parameter(struct sdio_func *func,
+ struct ssv_sdiobridge_glue *glue)
+{
+ int err_ret;
+ sdio_claim_host(func);
+ glue->dataIOPort = 0;
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret) << ( 8*0 ));
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret) << ( 8*1 ));
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret) << ( 8*2 ));
+ glue->regIOPort = 0;
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) << ( 8*0 ));
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) << ( 8*1 ));
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) << ( 8*2 ));
+ dev_err(&func->dev, "dataIOPort 0x%x regIOPort 0x%x [%lx]\n",
+ glue->dataIOPort,glue->regIOPort,(long unsigned int)IOCTL_SSVSDIO_GET_BLOCKLEN);
+ sdio_set_block_size(func,glue->blockSize);
+ sdio_release_host(func);
+}
+static int ssv_sdiobridge_init_buf(struct ssv_sdiobridge_glue *glue)
+{
+ u32 bsize,i,error;
+ struct ssv_rxbuf *bf;
+ init_waitqueue_head(&glue->read_wq);
+ spin_lock_init(&glue->rxbuflock);
+ INIT_LIST_HEAD(&glue->rxbuf);
+ INIT_LIST_HEAD(&glue->rxreadybuf);
+ bsize = sizeof(struct ssv_rxbuf) * RXBUFSIZE;
+ glue->bufaddr = kzalloc(bsize, GFP_KERNEL);
+ if (glue->bufaddr == NULL) {
+ error = -ENOMEM;
+ goto fail;
+ }
+ bf = glue->bufaddr;
+ for (i = 0; i < RXBUFSIZE; i++, bf++) {
+ list_add_tail(&bf->list, &glue->rxbuf);
+ }
+ return 0;
+fail:
+ return error;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+static char *ssv_sdiobridge_devnode(struct device *dev, umode_t *mode)
+#else
+static char *ssv_sdiobridge_devnode(struct device *dev, mode_t *mode)
+#endif
+{
+ if (!mode)
+ return NULL;
+ *mode = 0644;
+ return NULL;
+}
+extern int ssv_devicetype;
+static int __devinit ssv_sdiobridge_probe(struct sdio_func *func,
+ const struct sdio_device_id *id)
+{
+ mmc_pm_flag_t mmcflags;
+ int ret = -ENOMEM;
+ dev_t dev;
+ int alloc_ret = 0;
+ int cdev_ret = 0;
+ int err_ret;
+ if (ssv_devicetype != 1) {
+ printk(KERN_INFO "Not using SSV6200 bridge SDIO driver.\n");
+ return -ENODEV;
+ }
+ printk(KERN_INFO "=======================================\n");
+ printk(KERN_INFO "== RUN SDIO BRIDGE ==\n");
+ printk(KERN_INFO "=======================================\n");
+ printk(KERN_INFO "ssv_sdiobridge_probe func->num:%d",func->num);
+ if (func->num != 0x01)
+ return -ENODEV;
+ glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+ if (!glue) {
+ dev_err(&func->dev, "can't allocate glue\n");
+ goto out;
+ }
+ glue->blockMode = false;
+ glue->blockSize = BLOCKSIZE;
+ glue->autoAckInt = true;
+ glue->dump = false;
+ glue->funcFocus = 1;
+ ssv_sdiobridge_init_buf(glue);
+ glue->dev = &func->dev;
+ func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+ mmcflags = sdio_get_host_pm_caps(func);
+ dev_err(glue->dev, "sdio PM caps = 0x%x\n", mmcflags);
+ sdio_set_drvdata(func, glue);
+ pm_runtime_put_noidle(&func->dev);
+ ssv_sdiobridge_read_parameter(func,glue);
+ dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+ alloc_ret = alloc_chrdev_region(&dev, 0, num_of_dev, FILE_DEVICE_SSVSDIO_NAME);
+ if (alloc_ret)
+ goto error;
+ ssv_sdiobridge_ioctl_major = MAJOR(dev);
+ cdev_init(&ssv_sdiobridge_ioctl_cdev, &fops);
+ cdev_ret = cdev_add(&ssv_sdiobridge_ioctl_cdev, dev, num_of_dev);
+ if (cdev_ret)
+ goto error;
+ fc=class_create(THIS_MODULE, FILE_DEVICE_SSVSDIO_NAME);
+ fc->devnode = ssv_sdiobridge_devnode;
+ device_create(fc, NULL, dev, NULL, "%s", FILE_DEVICE_SSVSDIO_NAME);
+ dev_err(glue->dev, "%s driver(major: %d) installed.\n", FILE_DEVICE_SSVSDIO_NAME, ssv_sdiobridge_ioctl_major);
+ init_waitqueue_head(&glue->irq_wq);
+ ssv_sdiobridge_irq_enable(func,glue);
+ sdio_claim_host(func);
+#ifdef CONFIG_SSV_SDIO_EXT_INT
+ sdio_writeb(func,(~(SSVCABRIO_INT_RX)|SSVCABRIO_INT_GPIO)&0x7, 0x04, &err_ret);
+#else
+ sdio_writeb(func,(~(SSVCABRIO_INT_RX|SSVCABRIO_INT_GPIO))&0x7, 0x04, &err_ret);
+#endif
+ sdio_release_host(func);
+ return 0;
+error:
+ if (cdev_ret == 0)
+ cdev_del(&ssv_sdiobridge_ioctl_cdev);
+ if (alloc_ret == 0)
+ unregister_chrdev_region(dev, num_of_dev);
+ kfree(glue);
+out:
+ return ret;
+}
+static void __devexit ssv_sdiobridge_remove(struct sdio_func *func)
+{
+ struct ssv_sdiobridge_glue *glue = sdio_get_drvdata(func);
+ dev_t dev;
+ int err_ret;
+ sdio_claim_host(func);
+#ifdef CONFIG_SSV_SDIO_EXT_INT
+ sdio_writeb(func,0, 0x04, &err_ret);
+#else
+ sdio_writeb(func,SSVCABRIO_INT_GPIO, 0x04, &err_ret);
+#endif
+ sdio_release_host(func);
+ ssv_sdiobridge_irq_disable(glue,false);
+ dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+ device_destroy(fc,dev);
+ class_destroy(fc);
+ cdev_del(&ssv_sdiobridge_ioctl_cdev);
+ unregister_chrdev_region(dev, num_of_dev);
+ pm_runtime_get_noresume(&func->dev);
+ if ( glue ) {
+ dev_err(glue->dev, "ssv_sdiobridge_remove");
+ if (glue->bufaddr) {
+ kfree(glue->bufaddr);
+ }
+ kfree(glue);
+ glue = NULL;
+ }
+ sdio_set_drvdata(func, NULL);
+}
+#ifdef CONFIG_PM
+static int ssv_sdiobridge_suspend(struct device *dev)
+{
+ int ret = 0;
+ return ret;
+}
+static int ssv_sdiobridge_resume(struct device *dev)
+{
+ dev_dbg(dev, "ssvcabrio resume\n");
+ return 0;
+}
+static const struct dev_pm_ops ssv_sdiobridge_pm_ops = {
+ .suspend = ssv_sdiobridge_suspend,
+ .resume = ssv_sdiobridge_resume,
+};
+#endif
+static struct sdio_driver ssv_sdio_bridge_driver = {
+ .name = "ssv_sdio_bridge",
+ .id_table = ssv_sdiobridge_devices,
+ .probe = ssv_sdiobridge_probe,
+ .remove = __devexit_p(ssv_sdiobridge_remove),
+#ifdef CONFIG_PM
+ .drv = {
+ .pm = &ssv_sdiobridge_pm_ops,
+ },
+#endif
+};
+EXPORT_SYMBOL(ssv_sdio_bridge_driver);
+#if 1
+static int __init ssv_sdiobridge_init(void)
+{
+ printk(KERN_INFO "ssv_sdiobridge_init\n");
+ return sdio_register_driver(&ssv_sdio_bridge_driver);
+}
+static void __exit ssv_sdiobridge_exit(void)
+{
+ printk(KERN_INFO "ssv_sdiobridge_exit\n");
+ sdio_unregister_driver(&ssv_sdio_bridge_driver);
+}
+module_init(ssv_sdiobridge_init);
+module_exit(ssv_sdiobridge_exit);
+#endif
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("iComm-semi, Ltd");
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h
new file mode 100644
index 000000000..2a80c923f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef SSVSDIOBRIDGE_H
+#define SSVSDIOBRIDGE_H
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdiobridge_pub.h"
+struct ssv_sdiobridge_glue {
+ struct device *dev;
+ u8 blockMode;
+ u16 blockSize;
+ u8 autoAckInt;
+ unsigned int dataIOPort;
+ unsigned int regIOPort;
+ u8 funcFocus;
+ atomic_t irq_handling;
+ wait_queue_head_t irq_wq;
+ wait_queue_head_t read_wq;
+ spinlock_t rxbuflock;
+ void *bufaddr;
+ struct list_head rxbuf;
+ struct list_head rxreadybuf;
+ struct dentry *debugfs;
+ struct dentry *dump_entry;
+ u32 dump;
+};
+#define MANUFACTURER_SSV_CODE 0x3030
+#define MANUFACTURER_ID_CABRIO_BASE 0x3030
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h
new file mode 100644
index 000000000..a644f277a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef SSVSDIOBRIDGE_PUB_H
+#define SSVSDIOBRIDGE_PUB_H
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+struct ssv_sdiobridge_cmd {
+ __u32 in_data_len;
+ u8* in_data;
+#ifndef __x86_64
+ __u32 padding1;
+#endif
+ __u32 out_data_len;
+ u8* out_data;
+#ifndef __x86_64
+ __u32 padding2;
+#endif
+ __u32 response;
+} __attribute__((packed));
+#define FILE_DEVICE_SSVSDIO MMC_BLOCK_MAJOR
+#define FILE_DEVICE_SSVSDIO_SEQ 0x50
+#define FILE_DEVICE_SSVSDIO_NAME "ssvsdiobridge"
+#if 0
+#define IOCTL_SSVSDIO_GET_DRIVER_VERSION \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x01, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_NUMBER \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x02, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_GET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x03, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x04, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x05, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x06, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x07, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x08, struct ssv_sdiobridge_cmd)
+#if 0
+#define IOCTL_SSVSDIO_GET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x09, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0a, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_GET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0b, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0c, struct ssv_sdiobridge_cmd)
+#if 0
+#define IOCTL_SSVSDIO_GET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0d, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0e, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0f, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x10, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x11, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x12, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x13, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x14, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x15, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_READ_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x16, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x17, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x18, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x19, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1a, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1b, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1c, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1d, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1e, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1f, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_DATA \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x20, struct ssv_sdiobridge_cmd)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/build.sh b/drivers/net/wireless/ssv6x5x/build.sh
new file mode 100755
index 000000000..10fbc693f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/build.sh
@@ -0,0 +1,14 @@
+#/bin/bash
+
+# generate version information header
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+ echo "Please check SVN first !!"
+else
+if hash colormake 2>/dev/null; then
+ colormake;colormake install
+else
+ make;make install
+fi
+fi
diff --git a/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh b/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh
new file mode 100755
index 000000000..5d510da58
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh
@@ -0,0 +1,61 @@
+#!/bin/sh
+
+syms="\
+ssv_initmac \
+ssv6xxx_sdio_driver \
+stacfgpath \
+cfgfirmwarepath \
+ssv_cfg \
+ssv6xxx_exit \
+ssv6xxx_init \
+ssv6xxx_hci_deregister \
+ssv6xxx_dev_remove \
+ssv6xxx_sdio_exit \
+ssv6xxx_sdio_init \
+ssvdevice_init \
+ssvdevice_exit \
+ssv6xxx_hci_exit \
+ssv6xxx_hci_init \
+cfg_cmds \
+ssv6xxx_dev_probe \
+ssv6xxx_hci_register \
+generic_wifi_exit_module \
+generic_wifi_init_module \
+ssv\" \
+"
+syms2="\
+ssv6xxx_sdio_probe \
+ssv6xxx_sdio_remove \
+ssv6xxx_sdio_suspend \
+ssv6xxx_sdio_resume \
+"
+
+syms3="\
+SSV6XXX_SDIO \
+"
+
+for i in $syms;
+do
+echo "Replacing $i to tu_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/tu_$i/g"
+done
+
+echo "Restoring tu_ssv_cfg.h to ssv_cfg.h\n"
+find . -name "*.[ch]"| xargs sed -i "s/\"tu_ssv_cfg\.h\"/\"ssv_cfg\.h\"/g"
+find . -name "*.[ch]"| xargs sed -i "s//\"ssv_cfg\.h\"/g"
+
+for i in $syms2;
+do
+echo "Replacing $i to tu_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/tu_$i/g"
+done
+
+echo "Replacing SSV WLAN driver to TU SSV WLAN driver\n"
+find . -name "*.[ch]"| xargs sed -i "s/SSV WLAN driver/TU SSV WLAN driver/g"
+
+for i in $syms3;
+do
+echo "Replacing $i to TU_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/TU_$i/g"
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/clean_log.sh b/drivers/net/wireless/ssv6x5x/clean_log.sh
new file mode 100755
index 000000000..a9eeac927
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/clean_log.sh
@@ -0,0 +1,4 @@
+#/bin/bash
+dmesg -C
+rm -fr /var/log
+service rsyslog restart
diff --git a/drivers/net/wireless/ssv6x5x/cli b/drivers/net/wireless/ssv6x5x/cli
new file mode 100755
index 000000000..8d8579aca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cli
@@ -0,0 +1,40 @@
+#!/bin/bash
+
+ssv_phy=""
+if [[ ${1} =~ "wlan" ]]; then
+ wlan_dirs=/sys/class/net/${1}/device/ieee80211/
+ if [ ! -e ${wlan_dirs} ]; then
+ echo "Could not find the ${1}."
+ exit 1;
+ fi
+ # shift wlanX
+ shift 1
+ ssv_phy=`ls ${wlan_dirs}`
+else
+ phy_dirs="/sys/class/ieee80211/*"
+
+ for phy_dir in $phy_dirs; do
+ if [ ! -d ${phy_dir}/device/driver ]; then
+ exit 1;
+ fi
+ drv_name=`ls ${phy_dir}/device/driver | grep SV6`
+
+ if [ ${drv_name} ]; then
+ ssv_phy=`basename $phy_dir`;
+ break;
+ fi
+ done
+fi
+
+
+# excute CLI
+if [ ${ssv_phy} ]; then
+ SSV_CMD_FILE=/proc/ssv/${ssv_phy}/ssv_cmd
+ if [ -f $SSV_CMD_FILE ]; then
+ echo "$*" > $SSV_CMD_FILE
+ cat $SSV_CMD_FILE
+ fi
+else
+ echo "./cli [wlanX] [CMD]"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/config.mak b/drivers/net/wireless/ssv6x5x/config.mak
new file mode 100755
index 000000000..af7c90918
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/config.mak
@@ -0,0 +1,64 @@
+
+KVERSION="`uname -r`"
+#DRVPATH=/lib/modules/$(KVERSION)/kernel/drivers/net/wireless/ssv6200
+DRVPATH=kernel/drivers/net/wireless/ssv6200
+KCFLAG += -Werror
+#EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+EXTRA_CFLAGS := -I$(KBUILD_TOP)
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/include
+
+
+include $(KBUILD_TOP)/config_common.mak
+
+
+ccflags-y += -DREPORT_TX_STATUS_DIRECTLY
+
+########################################################
+## The following definition move from common mak
+
+# use for debug
+ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+#### end of move from common mak
+
+
+## Use crypto in SSV driver for ssv6051
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DUSE_LOCAL_CRYPTO
+#ccflags-y += -DUSE_LOCAL_WEP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_TKIP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_CCMP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_SMS4_CRYPTO
+#ccflags-y += -DCONFIG_SSV_WAPI
+#ccflags-y += -DHAS_CRYPTO_LOCK
+#ccflags-y += -DFW_WSID_WATCH_LIST
+#endif
+
+
+###########################################################
+# option to :qswitch driver between relay device and sw mac device
+# Enable ->Relay device (CHAR)
+# Disable->SW MAC device(NET)
+
+#DRV_OPT = HUW_DRV
+#For HUW to define some resources
+ifeq ($(DRV_OPT), HUW_DRV)
+ccflags-y += -DHUW_DRV
+endif
+#
+
+####################################################################
+# mac80211 option for use local ssv_mac80211 or kernel mac80211
+# if set SSV means our smac driver use local ssv_mac80211.ko
+# otherwise use kernel mac80211 build-in sub-sys
+####################################################################
+#MAC80211_OPT = SSV
+#For HUW to define some resources
+ifeq ($(MAC80211_OPT), SSV)
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/mac80211
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/mac80211/include
+
+ccflags-y += -DSSV_MAC80211
+endif
+#
diff --git a/drivers/net/wireless/ssv6x5x/config_common.mak b/drivers/net/wireless/ssv6x5x/config_common.mak
new file mode 100755
index 000000000..b29847713
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/config_common.mak
@@ -0,0 +1,142 @@
+
+CONFIG_SSV6X5X=m
+#ccflags-y += -DCONFIG_SSV6200_CORE
+#CONFIG_MAC80211_LEDS=y
+#CONFIG_MAC80211_DEBUGFS=y
+#CONFIG_MAC80211_MESH=y
+#CONFIG_PM=y
+#CONFIG_MAC80211_RC_MINSTREL=y
+#CONFIG_MAC80211_RC_MINSTREL_HT=y
+
+#ccflags-y += -D_ICOMM_MAC80211_
+
+ccflags-y += -D__CHECK_ENDIAN__
+###########################################################################
+# Compiler options #
+###########################################################################
+ccflags-y += -Werror
+
+# Enable -g to help debug. Deassembly from .o to .S would help to track to
+# the problomatic line from call stack dump.
+#ccflags-y += -DDEBUG -g
+ccflags-y += -Os
+
+#########################################################
+# option enable shal
+# if it is enable
+# DCONFIG_SSV_CABRIO_A/DCONFIG_SSV_CABRIO_A is not valid in driver.
+ccflags-y += -DSSV_SUPPORT_HAL
+ccflags-y += -DSSV_SUPPORT_SSV6006
+
+############################################################
+# If you change the settings, please change the file synchronization
+# smac\firmware\include\config.h & compiler firmware
+############################################################
+#ccflags-y += -DCONFIG_SSV_CABRIO_A
+#ccflags-y += -DSDIO_USE_SLOW_CLOCK
+ccflags-y += -DCONFIG_SSV_CABRIO_E
+
+#CONFIG_SSV_SUPPORT_BTCX=y
+
+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
+
+#ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+
+
+############################################################
+# Options should be able to set as parameters. #
+############################################################
+
+#PADPD
+#ccflags-y += -DCONFIG_SSV_DPD
+
+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
+
+#ccflags-y += -DCONFIG_SSV6XXX_HW_DEBUG
+
+#SDIO
+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
+
+#HCI AGGREGATION
+#ccflags-y += -DCONFIG_SSV_HCI_RX_AGGREGATION
+
+############################################################
+# Rate control update for MPDU.
+############################################################
+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATE
+
+#workaround
+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
+
+############################################################
+# NOTE:
+# Only one of the following flags could be turned on.
+# It also turned off the following flags. In this case,
+# pure software security or pure hardware security is used.
+#
+############################################################
+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+
+# FOR WFA
+#ccflags-y += -DWIFI_CERTIFIED
+
+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
+
+#######################################################
+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
+ccflags-y += -DUSE_THREAD_RX
+ccflags-y += -DUSE_THREAD_TX
+ccflags-y += -DENABLE_AGGREGATE_IN_TIME
+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
+
+# Generic decision table applicable to both AP and STA modes.
+ccflags-y += -DUSE_GENERIC_DECI_TBL
+
+########################################################
+## The following definition move to indivdual platform
+## should not enable again here.
+
+# Use crypto in SSV driver.
+ccflags-y += -DUSE_LOCAL_CRYPTO
+ccflags-y += -DUSE_LOCAL_WEP_CRYPTO
+ccflags-y += -DUSE_LOCAL_TKIP_CRYPTO
+ccflags-y += -DUSE_LOCAL_CCMP_CRYPTO
+ccflags-y += -DUSE_LOCAL_SMS4_CRYPTO
+ccflags-y += -DCONFIG_SSV_WAPI
+ccflags-y += -DHAS_CRYPTO_LOCK
+
+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+#### end of move to individual platform
+
+
+
+#ccflags-y += -DFW_WSID_WATCH_LIST
+#ccflags-y += -DUSE_BATCH_RX
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+
+
+ccflags-y += -DSSV6200_ECO
+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+#ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
+
+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
+
+
+#enable p2p client to parse GO broadcast noa
+#ccflags-y += -DCONFIG_P2P_NOA
+
+#enable rx management frame check
+#ccflags-y += -DCONFIG_RX_MGMT_CHECK
+
+#enable smart icomm
+
+#ccflags-y += -DCONFIG_SMARTLINK
+#ccflags-y += -DCONFIG_SSV_SMARTLINK
+
+ccflags-y += -DCONFIG_SSV_CCI_IMPROVEMENT
+
+#enable USB LPM function
+#ccflags-y += -DSSV_SUPPORT_USB_LPM
+
diff --git a/drivers/net/wireless/ssv6x5x/cross-android-release.sh b/drivers/net/wireless/ssv6x5x/cross-android-release.sh
new file mode 100755
index 000000000..8cf12a3ff
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cross-android-release.sh
@@ -0,0 +1,83 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+ "h8" \
+ "h3" \
+ "rk3036" \
+ "rk3126" \
+ "rk3128" \
+ "rk322x" \
+ "atm7039-action" \
+ "aml-s805" \
+ "aml-s905" \
+ "aml-t950" \
+ "xm-hi3518" \
+ "v66")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do
+ case "$REPLY" in
+
+ 1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 5 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 6 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 7 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 8 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 9 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 10 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 11 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 12 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 13 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+ $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+ *) echo "Invalid option. Try another one.";continue;;
+ esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+ echo "Please check SVN first !!"
+else
+cp platforms/platform-config.mak .
+cp platforms/$PLATFORM.cfg ssv6x5x.cfg
+cp platforms/$PLATFORM-generic-wlan.c ssv6x5x-generic-wlan.c
+cp platforms/$PLATFORM-wifi.cfg image/ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-wifi.cfg ssv6x5x-wifi.cfg
+cp Makefile.android Makefile
+
+# Remove garbage
+svn rm wpa_supplicant.conf
+svn rm unload.sh
+svn rm sta.cfg
+svn rm ssvcfg.sh
+svn rm rules.mak
+svn rm remove_old_driver.sh
+svn rm load.sh
+svn rm launch_sta_ap.sh
+svn rm launch_ap_sta.sh
+svn rm config.mak
+svn rm cli
+svn rm clean_log.sh
+svn rm ap_shutdown.sh
+svn rm ap_launch.sh
+svn rm ap_check.sh
+svn rm ap.cfg
+svn rm build.sh
+svn rm linux-build.sh
+svn rm android-build.sh
+svn rm cross-linux-release.sh
+svn rm Makefile.*
+svn rm platforms/* --force
+svn rm platforms --force
+
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/cross-linux-release.sh b/drivers/net/wireless/ssv6x5x/cross-linux-release.sh
new file mode 100755
index 000000000..f73df0927
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cross-linux-release.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("ak3916" \
+ "x1000" \
+ "t10" \
+ "t20" \
+ "sc6138")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do
+ case "$REPLY" in
+
+ 1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+ $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+ *) echo "Invalid option. Try another one.";continue;;
+ esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+ echo "Please check SVN first !!"
+else
+cp platforms/platform-config.mak .
+cp platforms/$PLATFORM.cfg ssv6x5x.cfg
+cp platforms/$PLATFORM-wifi.cfg ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-wifi.cfg image/ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-generic-wlan.c ssv6x5x-generic-wlan.c
+cp Makefile.cross_linux Makefile
+#sed -i 's,PLATFORMS =,PLATFORMS = '"$PLATFORM"',g' Makefile
+make clean
+
+# Remove garbage
+svn rm wpa_supplicant.conf
+svn rm unload.sh
+svn rm sta.cfg
+svn rm ssvcfg.sh
+svn rm rules.mak
+svn rm remove_old_driver.sh
+svn rm load.sh
+svn rm launch_sta_ap.sh
+svn rm launch_ap_sta.sh
+svn rm config.mak
+svn rm cli
+svn rm clean_log.sh
+svn rm ap_shutdown.sh
+svn rm ap_launch.sh
+svn rm ap_check.sh
+svn rm ap.cfg
+svn rm build.sh
+svn rm linux-build.sh
+svn rm android-build.sh
+svn rm cross-android-release.sh
+svn rm Makefile.* --force
+svn rm platforms/* --force
+svn rm platforms --force
+
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S b/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S
new file mode 100755
index 000000000..e59b1d505
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S
@@ -0,0 +1,1112 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ AES for ARMv4
+
+@ January 2007.
+@
+@ Code uses single 1K S-box and is >2 times faster than code generated
+@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
+@ allows to merge logical or arithmetic operation with shift or rotate
+@ in one instruction and emit combined result every cycle. The module
+@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
+@ key [on single-issue Xscale PXA250 core].
+
+@ May 2007.
+@
+@ AES_set_[en|de]crypt_key is added.
+
+@ July 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
+@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 16%
+@ improvement on Cortex A8 core and ~21.5 cycles per byte.
+
+@ A little glue here to select the correct code below for the ARM CPU
+@ that is being targetted.
+
+.text
+.code 32
+
+.type AES_Te,%object
+.align 5
+AES_Te:
+.word 0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
+.word 0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
+.word 0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
+.word 0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
+.word 0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
+.word 0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
+.word 0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
+.word 0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
+.word 0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
+.word 0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
+.word 0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
+.word 0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
+.word 0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
+.word 0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
+.word 0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
+.word 0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
+.word 0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
+.word 0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
+.word 0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
+.word 0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
+.word 0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
+.word 0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
+.word 0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
+.word 0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
+.word 0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
+.word 0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
+.word 0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
+.word 0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
+.word 0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
+.word 0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
+.word 0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
+.word 0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
+.word 0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
+.word 0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
+.word 0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
+.word 0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
+.word 0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
+.word 0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
+.word 0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
+.word 0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
+.word 0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
+.word 0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
+.word 0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
+.word 0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
+.word 0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
+.word 0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
+.word 0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
+.word 0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
+.word 0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
+.word 0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
+.word 0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
+.word 0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
+.word 0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
+.word 0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
+.word 0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
+.word 0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
+.word 0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
+.word 0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
+.word 0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
+.word 0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
+.word 0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
+.word 0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
+.word 0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
+.word 0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
+@ Te4[256]
+.byte 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
+.byte 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
+.byte 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
+.byte 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
+.byte 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
+.byte 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
+.byte 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
+.byte 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
+.byte 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
+.byte 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
+.byte 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
+.byte 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
+.byte 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
+.byte 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
+.byte 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
+.byte 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
+.byte 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
+.byte 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
+.byte 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
+.byte 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
+.byte 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
+.byte 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
+.byte 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
+.byte 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
+.byte 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
+.byte 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
+.byte 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
+.byte 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
+.byte 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
+.byte 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
+.byte 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
+.byte 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+@ rcon[]
+.word 0x01000000, 0x02000000, 0x04000000, 0x08000000
+.word 0x10000000, 0x20000000, 0x40000000, 0x80000000
+.word 0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
+.size AES_Te,.-AES_Te
+
+@ void AES_encrypt(const unsigned char *in, unsigned char *out,
+@ const AES_KEY *key) {
+.global AES_encrypt
+.type AES_encrypt,%function
+.align 5
+AES_encrypt:
+ sub r3,pc,#8 @ AES_encrypt
+ stmdb sp!,{r1,r4-r12,lr}
+ mov r12,r0 @ inp
+ mov r11,r2
+ sub r10,r3,#AES_encrypt-AES_Te @ Te
+#if __ARM_ARCH__<7
+ ldrb r0,[r12,#3] @ load input data in endian-neutral
+ ldrb r4,[r12,#2] @ manner...
+ ldrb r5,[r12,#1]
+ ldrb r6,[r12,#0]
+ orr r0,r0,r4,lsl#8
+ ldrb r1,[r12,#7]
+ orr r0,r0,r5,lsl#16
+ ldrb r4,[r12,#6]
+ orr r0,r0,r6,lsl#24
+ ldrb r5,[r12,#5]
+ ldrb r6,[r12,#4]
+ orr r1,r1,r4,lsl#8
+ ldrb r2,[r12,#11]
+ orr r1,r1,r5,lsl#16
+ ldrb r4,[r12,#10]
+ orr r1,r1,r6,lsl#24
+ ldrb r5,[r12,#9]
+ ldrb r6,[r12,#8]
+ orr r2,r2,r4,lsl#8
+ ldrb r3,[r12,#15]
+ orr r2,r2,r5,lsl#16
+ ldrb r4,[r12,#14]
+ orr r2,r2,r6,lsl#24
+ ldrb r5,[r12,#13]
+ ldrb r6,[r12,#12]
+ orr r3,r3,r4,lsl#8
+ orr r3,r3,r5,lsl#16
+ orr r3,r3,r6,lsl#24
+#else
+ ldr r0,[r12,#0]
+ ldr r1,[r12,#4]
+ ldr r2,[r12,#8]
+ ldr r3,[r12,#12]
+#ifdef __ARMEL__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+#endif
+#endif
+ bl _armv4_AES_encrypt
+
+ ldr r12,[sp],#4 @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+#endif
+ str r0,[r12,#0]
+ str r1,[r12,#4]
+ str r2,[r12,#8]
+ str r3,[r12,#12]
+#else
+ mov r4,r0,lsr#24 @ write output in endian-neutral
+ mov r5,r0,lsr#16 @ manner...
+ mov r6,r0,lsr#8
+ strb r4,[r12,#0]
+ strb r5,[r12,#1]
+ mov r4,r1,lsr#24
+ strb r6,[r12,#2]
+ mov r5,r1,lsr#16
+ strb r0,[r12,#3]
+ mov r6,r1,lsr#8
+ strb r4,[r12,#4]
+ strb r5,[r12,#5]
+ mov r4,r2,lsr#24
+ strb r6,[r12,#6]
+ mov r5,r2,lsr#16
+ strb r1,[r12,#7]
+ mov r6,r2,lsr#8
+ strb r4,[r12,#8]
+ strb r5,[r12,#9]
+ mov r4,r3,lsr#24
+ strb r6,[r12,#10]
+ mov r5,r3,lsr#16
+ strb r2,[r12,#11]
+ mov r6,r3,lsr#8
+ strb r4,[r12,#12]
+ strb r5,[r12,#13]
+ strb r6,[r12,#14]
+ strb r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r4-r12,pc}
+#else
+ ldmia sp!,{r4-r12,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size AES_encrypt,.-AES_encrypt
+
+.type _armv4_AES_encrypt,%function
+.align 2
+_armv4_AES_encrypt:
+ str lr,[sp,#-4]! @ push lr
+ ldmia r11!,{r4-r7}
+ eor r0,r0,r4
+ ldr r12,[r11,#240-16]
+ eor r1,r1,r5
+ eor r2,r2,r6
+ eor r3,r3,r7
+ sub r12,r12,#1
+ mov lr,#255
+
+ and r7,lr,r0
+ and r8,lr,r0,lsr#8
+ and r9,lr,r0,lsr#16
+ mov r0,r0,lsr#24
+.Lenc_loop:
+ ldr r4,[r10,r7,lsl#2] @ Te3[s0>>0]
+ and r7,lr,r1,lsr#16 @ i0
+ ldr r5,[r10,r8,lsl#2] @ Te2[s0>>8]
+ and r8,lr,r1
+ ldr r6,[r10,r9,lsl#2] @ Te1[s0>>16]
+ and r9,lr,r1,lsr#8
+ ldr r0,[r10,r0,lsl#2] @ Te0[s0>>24]
+ mov r1,r1,lsr#24
+
+ ldr r7,[r10,r7,lsl#2] @ Te1[s1>>16]
+ ldr r8,[r10,r8,lsl#2] @ Te3[s1>>0]
+ ldr r9,[r10,r9,lsl#2] @ Te2[s1>>8]
+ eor r0,r0,r7,ror#8
+ ldr r1,[r10,r1,lsl#2] @ Te0[s1>>24]
+ and r7,lr,r2,lsr#8 @ i0
+ eor r5,r5,r8,ror#8
+ and r8,lr,r2,lsr#16 @ i1
+ eor r6,r6,r9,ror#8
+ and r9,lr,r2
+ ldr r7,[r10,r7,lsl#2] @ Te2[s2>>8]
+ eor r1,r1,r4,ror#24
+ ldr r8,[r10,r8,lsl#2] @ Te1[s2>>16]
+ mov r2,r2,lsr#24
+
+ ldr r9,[r10,r9,lsl#2] @ Te3[s2>>0]
+ eor r0,r0,r7,ror#16
+ ldr r2,[r10,r2,lsl#2] @ Te0[s2>>24]
+ and r7,lr,r3 @ i0
+ eor r1,r1,r8,ror#8
+ and r8,lr,r3,lsr#8 @ i1
+ eor r6,r6,r9,ror#16
+ and r9,lr,r3,lsr#16 @ i2
+ ldr r7,[r10,r7,lsl#2] @ Te3[s3>>0]
+ eor r2,r2,r5,ror#16
+ ldr r8,[r10,r8,lsl#2] @ Te2[s3>>8]
+ mov r3,r3,lsr#24
+
+ ldr r9,[r10,r9,lsl#2] @ Te1[s3>>16]
+ eor r0,r0,r7,ror#24
+ ldr r7,[r11],#16
+ eor r1,r1,r8,ror#16
+ ldr r3,[r10,r3,lsl#2] @ Te0[s3>>24]
+ eor r2,r2,r9,ror#8
+ ldr r4,[r11,#-12]
+ eor r3,r3,r6,ror#8
+
+ ldr r5,[r11,#-8]
+ eor r0,r0,r7
+ ldr r6,[r11,#-4]
+ and r7,lr,r0
+ eor r1,r1,r4
+ and r8,lr,r0,lsr#8
+ eor r2,r2,r5
+ and r9,lr,r0,lsr#16
+ eor r3,r3,r6
+ mov r0,r0,lsr#24
+
+ subs r12,r12,#1
+ bne .Lenc_loop
+
+ add r10,r10,#2
+
+ ldrb r4,[r10,r7,lsl#2] @ Te4[s0>>0]
+ and r7,lr,r1,lsr#16 @ i0
+ ldrb r5,[r10,r8,lsl#2] @ Te4[s0>>8]
+ and r8,lr,r1
+ ldrb r6,[r10,r9,lsl#2] @ Te4[s0>>16]
+ and r9,lr,r1,lsr#8
+ ldrb r0,[r10,r0,lsl#2] @ Te4[s0>>24]
+ mov r1,r1,lsr#24
+
+ ldrb r7,[r10,r7,lsl#2] @ Te4[s1>>16]
+ ldrb r8,[r10,r8,lsl#2] @ Te4[s1>>0]
+ ldrb r9,[r10,r9,lsl#2] @ Te4[s1>>8]
+ eor r0,r7,r0,lsl#8
+ ldrb r1,[r10,r1,lsl#2] @ Te4[s1>>24]
+ and r7,lr,r2,lsr#8 @ i0
+ eor r5,r8,r5,lsl#8
+ and r8,lr,r2,lsr#16 @ i1
+ eor r6,r9,r6,lsl#8
+ and r9,lr,r2
+ ldrb r7,[r10,r7,lsl#2] @ Te4[s2>>8]
+ eor r1,r4,r1,lsl#24
+ ldrb r8,[r10,r8,lsl#2] @ Te4[s2>>16]
+ mov r2,r2,lsr#24
+
+ ldrb r9,[r10,r9,lsl#2] @ Te4[s2>>0]
+ eor r0,r7,r0,lsl#8
+ ldrb r2,[r10,r2,lsl#2] @ Te4[s2>>24]
+ and r7,lr,r3 @ i0
+ eor r1,r1,r8,lsl#16
+ and r8,lr,r3,lsr#8 @ i1
+ eor r6,r9,r6,lsl#8
+ and r9,lr,r3,lsr#16 @ i2
+ ldrb r7,[r10,r7,lsl#2] @ Te4[s3>>0]
+ eor r2,r5,r2,lsl#24
+ ldrb r8,[r10,r8,lsl#2] @ Te4[s3>>8]
+ mov r3,r3,lsr#24
+
+ ldrb r9,[r10,r9,lsl#2] @ Te4[s3>>16]
+ eor r0,r7,r0,lsl#8
+ ldr r7,[r11,#0]
+ ldrb r3,[r10,r3,lsl#2] @ Te4[s3>>24]
+ eor r1,r1,r8,lsl#8
+ ldr r4,[r11,#4]
+ eor r2,r2,r9,lsl#16
+ ldr r5,[r11,#8]
+ eor r3,r6,r3,lsl#24
+ ldr r6,[r11,#12]
+
+ eor r0,r0,r7
+ eor r1,r1,r4
+ eor r2,r2,r5
+ eor r3,r3,r6
+
+ sub r10,r10,#2
+ ldr pc,[sp],#4 @ pop and return
+.size _armv4_AES_encrypt,.-_armv4_AES_encrypt
+
+.global private_AES_set_encrypt_key
+.type private_AES_set_encrypt_key,%function
+.align 5
+private_AES_set_encrypt_key:
+_armv4_AES_set_encrypt_key:
+ sub r3,pc,#8 @ AES_set_encrypt_key
+ teq r0,#0
+ moveq r0,#-1
+ beq .Labrt
+ teq r2,#0
+ moveq r0,#-1
+ beq .Labrt
+
+ teq r1,#128
+ beq .Lok
+ teq r1,#192
+ beq .Lok
+ teq r1,#256
+ movne r0,#-1
+ bne .Labrt
+
+.Lok: stmdb sp!,{r4-r12,lr}
+ sub r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024 @ Te4
+
+ mov r12,r0 @ inp
+ mov lr,r1 @ bits
+ mov r11,r2 @ key
+
+#if __ARM_ARCH__<7
+ ldrb r0,[r12,#3] @ load input data in endian-neutral
+ ldrb r4,[r12,#2] @ manner...
+ ldrb r5,[r12,#1]
+ ldrb r6,[r12,#0]
+ orr r0,r0,r4,lsl#8
+ ldrb r1,[r12,#7]
+ orr r0,r0,r5,lsl#16
+ ldrb r4,[r12,#6]
+ orr r0,r0,r6,lsl#24
+ ldrb r5,[r12,#5]
+ ldrb r6,[r12,#4]
+ orr r1,r1,r4,lsl#8
+ ldrb r2,[r12,#11]
+ orr r1,r1,r5,lsl#16
+ ldrb r4,[r12,#10]
+ orr r1,r1,r6,lsl#24
+ ldrb r5,[r12,#9]
+ ldrb r6,[r12,#8]
+ orr r2,r2,r4,lsl#8
+ ldrb r3,[r12,#15]
+ orr r2,r2,r5,lsl#16
+ ldrb r4,[r12,#14]
+ orr r2,r2,r6,lsl#24
+ ldrb r5,[r12,#13]
+ ldrb r6,[r12,#12]
+ orr r3,r3,r4,lsl#8
+ str r0,[r11],#16
+ orr r3,r3,r5,lsl#16
+ str r1,[r11,#-12]
+ orr r3,r3,r6,lsl#24
+ str r2,[r11,#-8]
+ str r3,[r11,#-4]
+#else
+ ldr r0,[r12,#0]
+ ldr r1,[r12,#4]
+ ldr r2,[r12,#8]
+ ldr r3,[r12,#12]
+#ifdef __ARMEL__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+#endif
+ str r0,[r11],#16
+ str r1,[r11,#-12]
+ str r2,[r11,#-8]
+ str r3,[r11,#-4]
+#endif
+
+ teq lr,#128
+ bne .Lnot128
+ mov r12,#10
+ str r12,[r11,#240-16]
+ add r6,r10,#256 @ rcon
+ mov lr,#255
+
+.L128_loop:
+ and r5,lr,r3,lsr#24
+ and r7,lr,r3,lsr#16
+ ldrb r5,[r10,r5]
+ and r8,lr,r3,lsr#8
+ ldrb r7,[r10,r7]
+ and r9,lr,r3
+ ldrb r8,[r10,r8]
+ orr r5,r5,r7,lsl#24
+ ldrb r9,[r10,r9]
+ orr r5,r5,r8,lsl#16
+ ldr r4,[r6],#4 @ rcon[i++]
+ orr r5,r5,r9,lsl#8
+ eor r5,r5,r4
+ eor r0,r0,r5 @ rk[4]=rk[0]^...
+ eor r1,r1,r0 @ rk[5]=rk[1]^rk[4]
+ str r0,[r11],#16
+ eor r2,r2,r1 @ rk[6]=rk[2]^rk[5]
+ str r1,[r11,#-12]
+ eor r3,r3,r2 @ rk[7]=rk[3]^rk[6]
+ str r2,[r11,#-8]
+ subs r12,r12,#1
+ str r3,[r11,#-4]
+ bne .L128_loop
+ sub r2,r11,#176
+ b .Ldone
+
+.Lnot128:
+#if __ARM_ARCH__<7
+ ldrb r8,[r12,#19]
+ ldrb r4,[r12,#18]
+ ldrb r5,[r12,#17]
+ ldrb r6,[r12,#16]
+ orr r8,r8,r4,lsl#8
+ ldrb r9,[r12,#23]
+ orr r8,r8,r5,lsl#16
+ ldrb r4,[r12,#22]
+ orr r8,r8,r6,lsl#24
+ ldrb r5,[r12,#21]
+ ldrb r6,[r12,#20]
+ orr r9,r9,r4,lsl#8
+ orr r9,r9,r5,lsl#16
+ str r8,[r11],#8
+ orr r9,r9,r6,lsl#24
+ str r9,[r11,#-4]
+#else
+ ldr r8,[r12,#16]
+ ldr r9,[r12,#20]
+#ifdef __ARMEL__
+ rev r8,r8
+ rev r9,r9
+#endif
+ str r8,[r11],#8
+ str r9,[r11,#-4]
+#endif
+
+ teq lr,#192
+ bne .Lnot192
+ mov r12,#12
+ str r12,[r11,#240-24]
+ add r6,r10,#256 @ rcon
+ mov lr,#255
+ mov r12,#8
+
+.L192_loop:
+ and r5,lr,r9,lsr#24
+ and r7,lr,r9,lsr#16
+ ldrb r5,[r10,r5]
+ and r8,lr,r9,lsr#8
+ ldrb r7,[r10,r7]
+ and r9,lr,r9
+ ldrb r8,[r10,r8]
+ orr r5,r5,r7,lsl#24
+ ldrb r9,[r10,r9]
+ orr r5,r5,r8,lsl#16
+ ldr r4,[r6],#4 @ rcon[i++]
+ orr r5,r5,r9,lsl#8
+ eor r9,r5,r4
+ eor r0,r0,r9 @ rk[6]=rk[0]^...
+ eor r1,r1,r0 @ rk[7]=rk[1]^rk[6]
+ str r0,[r11],#24
+ eor r2,r2,r1 @ rk[8]=rk[2]^rk[7]
+ str r1,[r11,#-20]
+ eor r3,r3,r2 @ rk[9]=rk[3]^rk[8]
+ str r2,[r11,#-16]
+ subs r12,r12,#1
+ str r3,[r11,#-12]
+ subeq r2,r11,#216
+ beq .Ldone
+
+ ldr r7,[r11,#-32]
+ ldr r8,[r11,#-28]
+ eor r7,r7,r3 @ rk[10]=rk[4]^rk[9]
+ eor r9,r8,r7 @ rk[11]=rk[5]^rk[10]
+ str r7,[r11,#-8]
+ str r9,[r11,#-4]
+ b .L192_loop
+
+.Lnot192:
+#if __ARM_ARCH__<7
+ ldrb r8,[r12,#27]
+ ldrb r4,[r12,#26]
+ ldrb r5,[r12,#25]
+ ldrb r6,[r12,#24]
+ orr r8,r8,r4,lsl#8
+ ldrb r9,[r12,#31]
+ orr r8,r8,r5,lsl#16
+ ldrb r4,[r12,#30]
+ orr r8,r8,r6,lsl#24
+ ldrb r5,[r12,#29]
+ ldrb r6,[r12,#28]
+ orr r9,r9,r4,lsl#8
+ orr r9,r9,r5,lsl#16
+ str r8,[r11],#8
+ orr r9,r9,r6,lsl#24
+ str r9,[r11,#-4]
+#else
+ ldr r8,[r12,#24]
+ ldr r9,[r12,#28]
+#ifdef __ARMEL__
+ rev r8,r8
+ rev r9,r9
+#endif
+ str r8,[r11],#8
+ str r9,[r11,#-4]
+#endif
+
+ mov r12,#14
+ str r12,[r11,#240-32]
+ add r6,r10,#256 @ rcon
+ mov lr,#255
+ mov r12,#7
+
+.L256_loop:
+ and r5,lr,r9,lsr#24
+ and r7,lr,r9,lsr#16
+ ldrb r5,[r10,r5]
+ and r8,lr,r9,lsr#8
+ ldrb r7,[r10,r7]
+ and r9,lr,r9
+ ldrb r8,[r10,r8]
+ orr r5,r5,r7,lsl#24
+ ldrb r9,[r10,r9]
+ orr r5,r5,r8,lsl#16
+ ldr r4,[r6],#4 @ rcon[i++]
+ orr r5,r5,r9,lsl#8
+ eor r9,r5,r4
+ eor r0,r0,r9 @ rk[8]=rk[0]^...
+ eor r1,r1,r0 @ rk[9]=rk[1]^rk[8]
+ str r0,[r11],#32
+ eor r2,r2,r1 @ rk[10]=rk[2]^rk[9]
+ str r1,[r11,#-28]
+ eor r3,r3,r2 @ rk[11]=rk[3]^rk[10]
+ str r2,[r11,#-24]
+ subs r12,r12,#1
+ str r3,[r11,#-20]
+ subeq r2,r11,#256
+ beq .Ldone
+
+ and r5,lr,r3
+ and r7,lr,r3,lsr#8
+ ldrb r5,[r10,r5]
+ and r8,lr,r3,lsr#16
+ ldrb r7,[r10,r7]
+ and r9,lr,r3,lsr#24
+ ldrb r8,[r10,r8]
+ orr r5,r5,r7,lsl#8
+ ldrb r9,[r10,r9]
+ orr r5,r5,r8,lsl#16
+ ldr r4,[r11,#-48]
+ orr r5,r5,r9,lsl#24
+
+ ldr r7,[r11,#-44]
+ ldr r8,[r11,#-40]
+ eor r4,r4,r5 @ rk[12]=rk[4]^...
+ ldr r9,[r11,#-36]
+ eor r7,r7,r4 @ rk[13]=rk[5]^rk[12]
+ str r4,[r11,#-16]
+ eor r8,r8,r7 @ rk[14]=rk[6]^rk[13]
+ str r7,[r11,#-12]
+ eor r9,r9,r8 @ rk[15]=rk[7]^rk[14]
+ str r8,[r11,#-8]
+ str r9,[r11,#-4]
+ b .L256_loop
+
+.Ldone: mov r0,#0
+ ldmia sp!,{r4-r12,lr}
+.Labrt: tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+.size private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
+
+.global private_AES_set_decrypt_key
+.type private_AES_set_decrypt_key,%function
+.align 5
+private_AES_set_decrypt_key:
+ str lr,[sp,#-4]! @ push lr
+#if 0
+ @ kernel does both of these in setkey so optimise this bit out by
+ @ expecting the key to already have the enc_key work done (see aes_glue.c)
+ bl _armv4_AES_set_encrypt_key
+#else
+ mov r0,#0
+#endif
+ teq r0,#0
+ ldrne lr,[sp],#4 @ pop lr
+ bne .Labrt
+
+ stmdb sp!,{r4-r12}
+
+ ldr r12,[r2,#240] @ AES_set_encrypt_key preserves r2,
+ mov r11,r2 @ which is AES_KEY *key
+ mov r7,r2
+ add r8,r2,r12,lsl#4
+
+.Linv: ldr r0,[r7]
+ ldr r1,[r7,#4]
+ ldr r2,[r7,#8]
+ ldr r3,[r7,#12]
+ ldr r4,[r8]
+ ldr r5,[r8,#4]
+ ldr r6,[r8,#8]
+ ldr r9,[r8,#12]
+ str r0,[r8],#-16
+ str r1,[r8,#16+4]
+ str r2,[r8,#16+8]
+ str r3,[r8,#16+12]
+ str r4,[r7],#16
+ str r5,[r7,#-12]
+ str r6,[r7,#-8]
+ str r9,[r7,#-4]
+ teq r7,r8
+ bne .Linv
+ ldr r0,[r11,#16]! @ prefetch tp1
+ mov r7,#0x80
+ mov r8,#0x1b
+ orr r7,r7,#0x8000
+ orr r8,r8,#0x1b00
+ orr r7,r7,r7,lsl#16
+ orr r8,r8,r8,lsl#16
+ sub r12,r12,#1
+ mvn r9,r7
+ mov r12,r12,lsl#2 @ (rounds-1)*4
+
+.Lmix: and r4,r0,r7
+ and r1,r0,r9
+ sub r4,r4,r4,lsr#7
+ and r4,r4,r8
+ eor r1,r4,r1,lsl#1 @ tp2
+
+ and r4,r1,r7
+ and r2,r1,r9
+ sub r4,r4,r4,lsr#7
+ and r4,r4,r8
+ eor r2,r4,r2,lsl#1 @ tp4
+
+ and r4,r2,r7
+ and r3,r2,r9
+ sub r4,r4,r4,lsr#7
+ and r4,r4,r8
+ eor r3,r4,r3,lsl#1 @ tp8
+
+ eor r4,r1,r2
+ eor r5,r0,r3 @ tp9
+ eor r4,r4,r3 @ tpe
+ eor r4,r4,r1,ror#24
+ eor r4,r4,r5,ror#24 @ ^= ROTATE(tpb=tp9^tp2,8)
+ eor r4,r4,r2,ror#16
+ eor r4,r4,r5,ror#16 @ ^= ROTATE(tpd=tp9^tp4,16)
+ eor r4,r4,r5,ror#8 @ ^= ROTATE(tp9,24)
+
+ ldr r0,[r11,#4] @ prefetch tp1
+ str r4,[r11],#4
+ subs r12,r12,#1
+ bne .Lmix
+
+ mov r0,#0
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r4-r12,pc}
+#else
+ ldmia sp!,{r4-r12,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
+
+.type AES_Td,%object
+.align 5
+AES_Td:
+.word 0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
+.word 0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
+.word 0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
+.word 0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
+.word 0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
+.word 0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
+.word 0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
+.word 0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
+.word 0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
+.word 0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
+.word 0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
+.word 0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
+.word 0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
+.word 0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
+.word 0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
+.word 0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
+.word 0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
+.word 0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
+.word 0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
+.word 0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
+.word 0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
+.word 0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
+.word 0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
+.word 0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
+.word 0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
+.word 0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
+.word 0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
+.word 0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
+.word 0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
+.word 0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
+.word 0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
+.word 0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
+.word 0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
+.word 0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
+.word 0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
+.word 0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
+.word 0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
+.word 0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
+.word 0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
+.word 0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
+.word 0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
+.word 0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
+.word 0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
+.word 0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
+.word 0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
+.word 0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
+.word 0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
+.word 0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
+.word 0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
+.word 0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
+.word 0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
+.word 0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
+.word 0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
+.word 0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
+.word 0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
+.word 0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
+.word 0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
+.word 0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
+.word 0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
+.word 0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
+.word 0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
+.word 0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
+.word 0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
+.word 0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
+@ Td4[256]
+.byte 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
+.byte 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
+.byte 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
+.byte 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
+.byte 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
+.byte 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
+.byte 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
+.byte 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
+.byte 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
+.byte 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
+.byte 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
+.byte 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
+.byte 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
+.byte 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
+.byte 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
+.byte 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
+.byte 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
+.byte 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
+.byte 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
+.byte 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
+.byte 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
+.byte 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
+.byte 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
+.byte 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
+.byte 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
+.byte 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
+.byte 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
+.byte 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
+.byte 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
+.byte 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
+.byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
+.byte 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+.size AES_Td,.-AES_Td
+
+@ void AES_decrypt(const unsigned char *in, unsigned char *out,
+@ const AES_KEY *key) {
+.global AES_decrypt
+.type AES_decrypt,%function
+.align 5
+AES_decrypt:
+ sub r3,pc,#8 @ AES_decrypt
+ stmdb sp!,{r1,r4-r12,lr}
+ mov r12,r0 @ inp
+ mov r11,r2
+ sub r10,r3,#AES_decrypt-AES_Td @ Td
+#if __ARM_ARCH__<7
+ ldrb r0,[r12,#3] @ load input data in endian-neutral
+ ldrb r4,[r12,#2] @ manner...
+ ldrb r5,[r12,#1]
+ ldrb r6,[r12,#0]
+ orr r0,r0,r4,lsl#8
+ ldrb r1,[r12,#7]
+ orr r0,r0,r5,lsl#16
+ ldrb r4,[r12,#6]
+ orr r0,r0,r6,lsl#24
+ ldrb r5,[r12,#5]
+ ldrb r6,[r12,#4]
+ orr r1,r1,r4,lsl#8
+ ldrb r2,[r12,#11]
+ orr r1,r1,r5,lsl#16
+ ldrb r4,[r12,#10]
+ orr r1,r1,r6,lsl#24
+ ldrb r5,[r12,#9]
+ ldrb r6,[r12,#8]
+ orr r2,r2,r4,lsl#8
+ ldrb r3,[r12,#15]
+ orr r2,r2,r5,lsl#16
+ ldrb r4,[r12,#14]
+ orr r2,r2,r6,lsl#24
+ ldrb r5,[r12,#13]
+ ldrb r6,[r12,#12]
+ orr r3,r3,r4,lsl#8
+ orr r3,r3,r5,lsl#16
+ orr r3,r3,r6,lsl#24
+#else
+ ldr r0,[r12,#0]
+ ldr r1,[r12,#4]
+ ldr r2,[r12,#8]
+ ldr r3,[r12,#12]
+#ifdef __ARMEL__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+#endif
+#endif
+ bl _armv4_AES_decrypt
+
+ ldr r12,[sp],#4 @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+#endif
+ str r0,[r12,#0]
+ str r1,[r12,#4]
+ str r2,[r12,#8]
+ str r3,[r12,#12]
+#else
+ mov r4,r0,lsr#24 @ write output in endian-neutral
+ mov r5,r0,lsr#16 @ manner...
+ mov r6,r0,lsr#8
+ strb r4,[r12,#0]
+ strb r5,[r12,#1]
+ mov r4,r1,lsr#24
+ strb r6,[r12,#2]
+ mov r5,r1,lsr#16
+ strb r0,[r12,#3]
+ mov r6,r1,lsr#8
+ strb r4,[r12,#4]
+ strb r5,[r12,#5]
+ mov r4,r2,lsr#24
+ strb r6,[r12,#6]
+ mov r5,r2,lsr#16
+ strb r1,[r12,#7]
+ mov r6,r2,lsr#8
+ strb r4,[r12,#8]
+ strb r5,[r12,#9]
+ mov r4,r3,lsr#24
+ strb r6,[r12,#10]
+ mov r5,r3,lsr#16
+ strb r2,[r12,#11]
+ mov r6,r3,lsr#8
+ strb r4,[r12,#12]
+ strb r5,[r12,#13]
+ strb r6,[r12,#14]
+ strb r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r4-r12,pc}
+#else
+ ldmia sp!,{r4-r12,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size AES_decrypt,.-AES_decrypt
+
+.type _armv4_AES_decrypt,%function
+.align 2
+_armv4_AES_decrypt:
+ str lr,[sp,#-4]! @ push lr
+ ldmia r11!,{r4-r7}
+ eor r0,r0,r4
+ ldr r12,[r11,#240-16]
+ eor r1,r1,r5
+ eor r2,r2,r6
+ eor r3,r3,r7
+ sub r12,r12,#1
+ mov lr,#255
+
+ and r7,lr,r0,lsr#16
+ and r8,lr,r0,lsr#8
+ and r9,lr,r0
+ mov r0,r0,lsr#24
+.Ldec_loop:
+ ldr r4,[r10,r7,lsl#2] @ Td1[s0>>16]
+ and r7,lr,r1 @ i0
+ ldr r5,[r10,r8,lsl#2] @ Td2[s0>>8]
+ and r8,lr,r1,lsr#16
+ ldr r6,[r10,r9,lsl#2] @ Td3[s0>>0]
+ and r9,lr,r1,lsr#8
+ ldr r0,[r10,r0,lsl#2] @ Td0[s0>>24]
+ mov r1,r1,lsr#24
+
+ ldr r7,[r10,r7,lsl#2] @ Td3[s1>>0]
+ ldr r8,[r10,r8,lsl#2] @ Td1[s1>>16]
+ ldr r9,[r10,r9,lsl#2] @ Td2[s1>>8]
+ eor r0,r0,r7,ror#24
+ ldr r1,[r10,r1,lsl#2] @ Td0[s1>>24]
+ and r7,lr,r2,lsr#8 @ i0
+ eor r5,r8,r5,ror#8
+ and r8,lr,r2 @ i1
+ eor r6,r9,r6,ror#8
+ and r9,lr,r2,lsr#16
+ ldr r7,[r10,r7,lsl#2] @ Td2[s2>>8]
+ eor r1,r1,r4,ror#8
+ ldr r8,[r10,r8,lsl#2] @ Td3[s2>>0]
+ mov r2,r2,lsr#24
+
+ ldr r9,[r10,r9,lsl#2] @ Td1[s2>>16]
+ eor r0,r0,r7,ror#16
+ ldr r2,[r10,r2,lsl#2] @ Td0[s2>>24]
+ and r7,lr,r3,lsr#16 @ i0
+ eor r1,r1,r8,ror#24
+ and r8,lr,r3,lsr#8 @ i1
+ eor r6,r9,r6,ror#8
+ and r9,lr,r3 @ i2
+ ldr r7,[r10,r7,lsl#2] @ Td1[s3>>16]
+ eor r2,r2,r5,ror#8
+ ldr r8,[r10,r8,lsl#2] @ Td2[s3>>8]
+ mov r3,r3,lsr#24
+
+ ldr r9,[r10,r9,lsl#2] @ Td3[s3>>0]
+ eor r0,r0,r7,ror#8
+ ldr r7,[r11],#16
+ eor r1,r1,r8,ror#16
+ ldr r3,[r10,r3,lsl#2] @ Td0[s3>>24]
+ eor r2,r2,r9,ror#24
+
+ ldr r4,[r11,#-12]
+ eor r0,r0,r7
+ ldr r5,[r11,#-8]
+ eor r3,r3,r6,ror#8
+ ldr r6,[r11,#-4]
+ and r7,lr,r0,lsr#16
+ eor r1,r1,r4
+ and r8,lr,r0,lsr#8
+ eor r2,r2,r5
+ and r9,lr,r0
+ eor r3,r3,r6
+ mov r0,r0,lsr#24
+
+ subs r12,r12,#1
+ bne .Ldec_loop
+
+ add r10,r10,#1024
+
+ ldr r5,[r10,#0] @ prefetch Td4
+ ldr r6,[r10,#32]
+ ldr r4,[r10,#64]
+ ldr r5,[r10,#96]
+ ldr r6,[r10,#128]
+ ldr r4,[r10,#160]
+ ldr r5,[r10,#192]
+ ldr r6,[r10,#224]
+
+ ldrb r0,[r10,r0] @ Td4[s0>>24]
+ ldrb r4,[r10,r7] @ Td4[s0>>16]
+ and r7,lr,r1 @ i0
+ ldrb r5,[r10,r8] @ Td4[s0>>8]
+ and r8,lr,r1,lsr#16
+ ldrb r6,[r10,r9] @ Td4[s0>>0]
+ and r9,lr,r1,lsr#8
+
+ ldrb r7,[r10,r7] @ Td4[s1>>0]
+ ldrb r1,[r10,r1,lsr#24] @ Td4[s1>>24]
+ ldrb r8,[r10,r8] @ Td4[s1>>16]
+ eor r0,r7,r0,lsl#24
+ ldrb r9,[r10,r9] @ Td4[s1>>8]
+ eor r1,r4,r1,lsl#8
+ and r7,lr,r2,lsr#8 @ i0
+ eor r5,r5,r8,lsl#8
+ and r8,lr,r2 @ i1
+ ldrb r7,[r10,r7] @ Td4[s2>>8]
+ eor r6,r6,r9,lsl#8
+ ldrb r8,[r10,r8] @ Td4[s2>>0]
+ and r9,lr,r2,lsr#16
+
+ ldrb r2,[r10,r2,lsr#24] @ Td4[s2>>24]
+ eor r0,r0,r7,lsl#8
+ ldrb r9,[r10,r9] @ Td4[s2>>16]
+ eor r1,r8,r1,lsl#16
+ and r7,lr,r3,lsr#16 @ i0
+ eor r2,r5,r2,lsl#16
+ and r8,lr,r3,lsr#8 @ i1
+ ldrb r7,[r10,r7] @ Td4[s3>>16]
+ eor r6,r6,r9,lsl#16
+ ldrb r8,[r10,r8] @ Td4[s3>>8]
+ and r9,lr,r3 @ i2
+
+ ldrb r9,[r10,r9] @ Td4[s3>>0]
+ ldrb r3,[r10,r3,lsr#24] @ Td4[s3>>24]
+ eor r0,r0,r7,lsl#16
+ ldr r7,[r11,#0]
+ eor r1,r1,r8,lsl#8
+ ldr r4,[r11,#4]
+ eor r2,r9,r2,lsl#8
+ ldr r5,[r11,#8]
+ eor r3,r6,r3,lsl#24
+ ldr r6,[r11,#12]
+
+ eor r0,r0,r7
+ eor r1,r1,r4
+ eor r2,r2,r5
+ eor r3,r3,r6
+
+ sub r10,r10,#1024
+ ldr pc,[sp],#4 @ pop and return
+.size _armv4_AES_decrypt,.-_armv4_AES_decrypt
+.asciz "AES for ARMv4, CRYPTOGAMS by "
+.align 2
diff --git a/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c b/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c
new file mode 100644
index 000000000..3c510e618
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#define AES_MAXNR 14
+typedef struct {
+ unsigned int rd_key[4 *(AES_MAXNR + 1)];
+ int rounds;
+} AES_KEY;
+struct AES_CTX {
+ AES_KEY enc_key;
+ AES_KEY dec_key;
+};
+asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+ struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+ AES_encrypt(src, dst, &ctx->enc_key);
+}
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+ struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+ AES_decrypt(src, dst, &ctx->dec_key);
+}
+static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+ unsigned int key_len)
+{
+ struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+ switch (key_len) {
+ case AES_KEYSIZE_128:
+ key_len = 128;
+ break;
+ case AES_KEYSIZE_192:
+ key_len = 192;
+ break;
+ case AES_KEYSIZE_256:
+ key_len = 256;
+ break;
+ default:
+ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ return -EINVAL;
+ }
+ if (private_AES_set_encrypt_key(in_key, key_len, &ctx->enc_key) == -1) {
+ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ return -EINVAL;
+ }
+ ctx->dec_key = ctx->enc_key;
+ if (private_AES_set_decrypt_key(in_key, key_len, &ctx->dec_key) == -1) {
+ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ return -EINVAL;
+ }
+ return 0;
+}
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-asm",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct AES_CTX),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
+ .cra_u = {
+ .cipher = {
+ .cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cia_setkey = aes_set_key,
+ .cia_encrypt = aes_encrypt,
+ .cia_decrypt = aes_decrypt
+ }
+ }
+};
+int aes_init(void)
+{
+ return crypto_register_alg(&aes_alg);
+}
+void aes_fini(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
diff --git a/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S b/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S
new file mode 100755
index 000000000..7050ab133
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S
@@ -0,0 +1,503 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ sha1_block procedure for ARMv4.
+@
+@ January 2007.
+
+@ Size/performance trade-off
+@ ====================================================================
+@ impl size in bytes comp cycles[*] measured performance
+@ ====================================================================
+@ thumb 304 3212 4420
+@ armv4-small 392/+29% 1958/+64% 2250/+96%
+@ armv4-compact 740/+89% 1552/+26% 1840/+22%
+@ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
+@ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
+@ ====================================================================
+@ thumb = same as 'small' but in Thumb instructions[**] and
+@ with recurring code in two private functions;
+@ small = detached Xload/update, loops are folded;
+@ compact = detached Xload/update, 5x unroll;
+@ large = interleaved Xload/update, 5x unroll;
+@ full unroll = interleaved Xload/update, full unroll, estimated[!];
+@
+@ [*] Manually counted instructions in "grand" loop body. Measured
+@ performance is affected by prologue and epilogue overhead,
+@ i-cache availability, branch penalties, etc.
+@ [**] While each Thumb instruction is twice smaller, they are not as
+@ diverse as ARM ones: e.g., there are only two arithmetic
+@ instructions with 3 arguments, no [fixed] rotate, addressing
+@ modes are limited. As result it takes more instructions to do
+@ the same job in Thumb, therefore the code is never twice as
+@ small and always slower.
+@ [***] which is also ~35% better than compiler generated code. Dual-
+@ issue Cortex A8 core was measured to process input block in
+@ ~990 cycles.
+
+@ August 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
+@ Cortex A8 core and in absolute terms ~870 cycles per input block
+@ [or 13.6 cycles per byte].
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 10%
+@ improvement on Cortex A8 core and 12.2 cycles per byte.
+
+.text
+
+.global sha1_block_data_order
+.type sha1_block_data_order,%function
+
+.align 2
+sha1_block_data_order:
+ stmdb sp!,{r4-r12,lr}
+ add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
+ ldmia r0,{r3,r4,r5,r6,r7}
+.Lloop:
+ ldr r8,.LK_00_19
+ mov r14,sp
+ sub sp,sp,#15*4
+ mov r5,r5,ror#30
+ mov r6,r6,ror#30
+ mov r7,r7,ror#30 @ [6]
+.L_00_15:
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r7,r8,r7,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r5,r6 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r7,r8,r7,ror#2 @ E+=K_00_19
+ eor r10,r5,r6 @ F_xx_xx
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r4,r10,ror#2
+ add r7,r7,r9 @ E+=X[i]
+ eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r7,r7,r10 @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r6,r8,r6,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r4,r5 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r6,r6,r7,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r6,r8,r6,ror#2 @ E+=K_00_19
+ eor r10,r4,r5 @ F_xx_xx
+ add r6,r6,r7,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r3,r10,ror#2
+ add r6,r6,r9 @ E+=X[i]
+ eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r6,r6,r10 @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r5,r8,r5,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r3,r4 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r5,r5,r6,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r5,r8,r5,ror#2 @ E+=K_00_19
+ eor r10,r3,r4 @ F_xx_xx
+ add r5,r5,r6,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r7,r10,ror#2
+ add r5,r5,r9 @ E+=X[i]
+ eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r5,r5,r10 @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r4,r8,r4,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r7,r3 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r4,r4,r5,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r4,r8,r4,ror#2 @ E+=K_00_19
+ eor r10,r7,r3 @ F_xx_xx
+ add r4,r4,r5,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r6,r10,ror#2
+ add r4,r4,r9 @ E+=X[i]
+ eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r4,r4,r10 @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r3,r8,r3,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r6,r7 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r3,r3,r4,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r3,r8,r3,ror#2 @ E+=K_00_19
+ eor r10,r6,r7 @ F_xx_xx
+ add r3,r3,r4,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r5,r10,ror#2
+ add r3,r3,r9 @ E+=X[i]
+ eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r3,r3,r10 @ E+=F_00_19(B,C,D)
+ teq r14,sp
+ bne .L_00_15 @ [((11+4)*5+2)*3]
+#if __ARM_ARCH__<7
+ ldrb r10,[r1,#2]
+ ldrb r9,[r1,#3]
+ ldrb r11,[r1,#1]
+ add r7,r8,r7,ror#2 @ E+=K_00_19
+ ldrb r12,[r1],#4
+ orr r9,r9,r10,lsl#8
+ eor r10,r5,r6 @ F_xx_xx
+ orr r9,r9,r11,lsl#16
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+ orr r9,r9,r12,lsl#24
+#else
+ ldr r9,[r1],#4 @ handles unaligned
+ add r7,r8,r7,ror#2 @ E+=K_00_19
+ eor r10,r5,r6 @ F_xx_xx
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+ rev r9,r9 @ byte swap
+#endif
+#endif
+ and r10,r4,r10,ror#2
+ add r7,r7,r9 @ E+=X[i]
+ eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
+ str r9,[r14,#-4]!
+ add r7,r7,r10 @ E+=F_00_19(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r6,r8,r6,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r4,r5 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r6,r6,r7,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r3,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r6,r6,r9 @ E+=X[i]
+ eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
+ add r6,r6,r10 @ E+=F_00_19(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r5,r8,r5,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r3,r4 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r5,r5,r6,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r7,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r5,r5,r9 @ E+=X[i]
+ eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
+ add r5,r5,r10 @ E+=F_00_19(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r4,r8,r4,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r7,r3 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r4,r4,r5,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r6,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r4,r4,r9 @ E+=X[i]
+ eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
+ add r4,r4,r10 @ E+=F_00_19(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r3,r8,r3,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r6,r7 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r3,r3,r4,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r5,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r3,r3,r9 @ E+=X[i]
+ eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
+ add r3,r3,r10 @ E+=F_00_19(B,C,D)
+
+ ldr r8,.LK_20_39 @ [+15+16*4]
+ sub sp,sp,#25*4
+ cmn sp,#0 @ [+3], clear carry to denote 20_39
+.L_20_39_or_60_79:
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r7,r8,r7,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r5,r6 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ eor r10,r4,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r7,r7,r9 @ E+=X[i]
+ add r7,r7,r10 @ E+=F_20_39(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r6,r8,r6,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r4,r5 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r6,r6,r7,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ eor r10,r3,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r6,r6,r9 @ E+=X[i]
+ add r6,r6,r10 @ E+=F_20_39(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r5,r8,r5,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r3,r4 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r5,r5,r6,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ eor r10,r7,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r5,r5,r9 @ E+=X[i]
+ add r5,r5,r10 @ E+=F_20_39(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r4,r8,r4,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r7,r3 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r4,r4,r5,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ eor r10,r6,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r4,r4,r9 @ E+=X[i]
+ add r4,r4,r10 @ E+=F_20_39(B,C,D)
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r3,r8,r3,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r6,r7 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r3,r3,r4,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ eor r10,r5,r10,ror#2 @ F_xx_xx
+ @ F_xx_xx
+ add r3,r3,r9 @ E+=X[i]
+ add r3,r3,r10 @ E+=F_20_39(B,C,D)
+ teq r14,sp @ preserve carry
+ bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
+ bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
+
+ ldr r8,.LK_40_59
+ sub sp,sp,#20*4 @ [+2]
+.L_40_59:
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r7,r8,r7,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r5,r6 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r7,r7,r3,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r4,r10,ror#2 @ F_xx_xx
+ and r11,r5,r6 @ F_xx_xx
+ add r7,r7,r9 @ E+=X[i]
+ add r7,r7,r10 @ E+=F_40_59(B,C,D)
+ add r7,r7,r11,ror#2
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r6,r8,r6,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r4,r5 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r6,r6,r7,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r3,r10,ror#2 @ F_xx_xx
+ and r11,r4,r5 @ F_xx_xx
+ add r6,r6,r9 @ E+=X[i]
+ add r6,r6,r10 @ E+=F_40_59(B,C,D)
+ add r6,r6,r11,ror#2
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r5,r8,r5,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r3,r4 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r5,r5,r6,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r7,r10,ror#2 @ F_xx_xx
+ and r11,r3,r4 @ F_xx_xx
+ add r5,r5,r9 @ E+=X[i]
+ add r5,r5,r10 @ E+=F_40_59(B,C,D)
+ add r5,r5,r11,ror#2
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r4,r8,r4,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r7,r3 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r4,r4,r5,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r6,r10,ror#2 @ F_xx_xx
+ and r11,r7,r3 @ F_xx_xx
+ add r4,r4,r9 @ E+=X[i]
+ add r4,r4,r10 @ E+=F_40_59(B,C,D)
+ add r4,r4,r11,ror#2
+ ldr r9,[r14,#15*4]
+ ldr r10,[r14,#13*4]
+ ldr r11,[r14,#7*4]
+ add r3,r8,r3,ror#2 @ E+=K_xx_xx
+ ldr r12,[r14,#2*4]
+ eor r9,r9,r10
+ eor r11,r11,r12 @ 1 cycle stall
+ eor r10,r6,r7 @ F_xx_xx
+ mov r9,r9,ror#31
+ add r3,r3,r4,ror#27 @ E+=ROR(A,27)
+ eor r9,r9,r11,ror#31
+ str r9,[r14,#-4]!
+ and r10,r5,r10,ror#2 @ F_xx_xx
+ and r11,r6,r7 @ F_xx_xx
+ add r3,r3,r9 @ E+=X[i]
+ add r3,r3,r10 @ E+=F_40_59(B,C,D)
+ add r3,r3,r11,ror#2
+ teq r14,sp
+ bne .L_40_59 @ [+((12+5)*5+2)*4]
+
+ ldr r8,.LK_60_79
+ sub sp,sp,#20*4
+ cmp sp,#0 @ set carry to denote 60_79
+ b .L_20_39_or_60_79 @ [+4], spare 300 bytes
+.L_done:
+ add sp,sp,#80*4 @ "deallocate" stack frame
+ ldmia r0,{r8,r9,r10,r11,r12}
+ add r3,r8,r3
+ add r4,r9,r4
+ add r5,r10,r5,ror#2
+ add r6,r11,r6,ror#2
+ add r7,r12,r7,ror#2
+ stmia r0,{r3,r4,r5,r6,r7}
+ teq r1,r2
+ bne .Lloop @ [+18], total 1307
+
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r4-r12,pc}
+#else
+ ldmia sp!,{r4-r12,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.align 2
+.LK_00_19: .word 0x5a827999
+.LK_20_39: .word 0x6ed9eba1
+.LK_40_59: .word 0x8f1bbcdc
+.LK_60_79: .word 0xca62c1d6
+.size sha1_block_data_order,.-sha1_block_data_order
+.asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by "
+.align 2
diff --git a/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c b/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c
new file mode 100644
index 000000000..abea12444
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+struct SHA1_CTX {
+ uint32_t h0,h1,h2,h3,h4;
+ u64 count;
+ u8 data[SHA1_BLOCK_SIZE];
+};
+asmlinkage void sha1_block_data_order(struct SHA1_CTX *digest,
+ const unsigned char *data, unsigned int rounds);
+static int sha1_init(struct shash_desc *desc)
+{
+ struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+ memset(sctx, 0, sizeof(*sctx));
+ sctx->h0 = SHA1_H0;
+ sctx->h1 = SHA1_H1;
+ sctx->h2 = SHA1_H2;
+ sctx->h3 = SHA1_H3;
+ sctx->h4 = SHA1_H4;
+ return 0;
+}
+static int __sha1_update(struct SHA1_CTX *sctx, const u8 *data,
+ unsigned int len, unsigned int partial)
+{
+ unsigned int done = 0;
+ sctx->count += len;
+ if (partial) {
+ done = SHA1_BLOCK_SIZE - partial;
+ memcpy(sctx->data + partial, data, done);
+ sha1_block_data_order(sctx, sctx->data, 1);
+ }
+ if (len - done >= SHA1_BLOCK_SIZE) {
+ const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
+ sha1_block_data_order(sctx, data + done, rounds);
+ done += rounds * SHA1_BLOCK_SIZE;
+ }
+ memcpy(sctx->data, data + done, len - done);
+ return 0;
+}
+static int sha1_update(struct shash_desc *desc, const u8 *data,
+ unsigned int len)
+{
+ struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+ unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
+ int res;
+ if (partial + len < SHA1_BLOCK_SIZE) {
+ sctx->count += len;
+ memcpy(sctx->data + partial, data, len);
+ return 0;
+ }
+ res = __sha1_update(sctx, data, len, partial);
+ return res;
+}
+static int sha1_final(struct shash_desc *desc, u8 *out)
+{
+ struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+ unsigned int i, index, padlen;
+ __be32 *dst = (__be32 *)out;
+ __be64 bits;
+ static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
+ bits = cpu_to_be64(sctx->count << 3);
+ index = sctx->count % SHA1_BLOCK_SIZE;
+ padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
+ if (padlen <= 56) {
+ sctx->count += padlen;
+ memcpy(sctx->data + index, padding, padlen);
+ } else {
+ __sha1_update(sctx, padding, padlen, index);
+ }
+ __sha1_update(sctx, (const u8 *)&bits, sizeof(bits), 56);
+ for (i = 0; i < 5; i++)
+ dst[i] = cpu_to_be32(((u32 *)sctx)[i]);
+ memset(sctx, 0, sizeof(*sctx));
+ return 0;
+}
+static int sha1_export(struct shash_desc *desc, void *out)
+{
+ struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+ memcpy(out, sctx, sizeof(*sctx));
+ return 0;
+}
+static int sha1_import(struct shash_desc *desc, const void *in)
+{
+ struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+ memcpy(sctx, in, sizeof(*sctx));
+ return 0;
+}
+static struct shash_alg alg = {
+ .digestsize = SHA1_DIGEST_SIZE,
+ .init = sha1_init,
+ .update = sha1_update,
+ .final = sha1_final,
+ .export = sha1_export,
+ .import = sha1_import,
+ .descsize = sizeof(struct SHA1_CTX),
+ .statesize = sizeof(struct SHA1_CTX),
+ .base = {
+ .cra_name = "sha1",
+ .cra_driver_name= "sha1-asm",
+ .cra_priority = 150,
+ .cra_flags = CRYPTO_ALG_TYPE_SHASH,
+ .cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_module = THIS_MODULE,
+ }
+};
+int sha1_mod_init(void)
+{
+ return crypto_register_shash(&alg);
+}
+void sha1_mod_fini(void)
+{
+ crypto_unregister_shash(&alg);
+}
+#if 0
+module_init(sha1_mod_init);
+module_exit(sha1_mod_fini);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm (ARM)");
+MODULE_ALIAS("sha1");
+MODULE_AUTHOR("David McCullough ");
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/gen-version.sh b/drivers/net/wireless/ssv6x5x/gen-version.sh
new file mode 100755
index 000000000..51fbb6487
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/gen-version.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+
+./ver_info.pl include/ssv_version.h
+
diff --git a/drivers/net/wireless/ssv6x5x/genconf.sh b/drivers/net/wireless/ssv6x5x/genconf.sh
new file mode 100755
index 000000000..e98ee029a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/genconf.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# Script to convert defines in compiler option in to C's defines
+# Should be executed in make file and it take ccflags-y as the
+# compiler options. The content will be redirected to the first arguement.
+
+echo "#ifndef __SSV_MOD_CONF_H__" > $1
+echo "#define __SSV_MOD_CONF_H__" >> $1
+
+for flag in ${ccflags-y}; do
+ if [[ "$flag" =~ ^-D.* ]]; then
+ #def=${flag//-D/}
+ def=${flag:2}
+ echo "#ifndef $def" >> $1
+ echo "#define $def" >> $1
+ echo "#endif" >> $1
+ fi
+done
+
+echo "#define __must_check" >> $1
+echo "#define __devinit" >> $1
+echo "#define __devexit" >> $1
+echo "#define __init" >> $1
+echo "#define __exit" >> $1
+
+echo "#endif // __SSV_MOD_CONF_H__" >> $1
diff --git a/drivers/net/wireless/ssv6x5x/hci/Makefile b/drivers/net/wireless/ssv6x5x/hci/Makefile
new file mode 100755
index 000000000..8b872d665
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/Makefile
@@ -0,0 +1,19 @@
+ifeq ($(KBUILD_TOP),)
+ ifneq ($(KBUILD_EXTMOD),)
+ KBUILD_DIR := $(KBUILD_EXTMOD)
+ else
+ KBUILD_DIR := $(PWD)
+ endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+
+KMODULE_NAME=ssv6200_hci
+KERN_SRCS += ssv_hci.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hci/hctrl.h b/drivers/net/wireless/ssv6x5x/hci/hctrl.h
new file mode 100644
index 000000000..806646a4f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/hctrl.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _HCTRL_H_
+#define _HCTRL_H_
+#define SSV6XXX_HCI_OP_INVALID 0x00000001
+#define SSV6XXX_HCI_OP_IFERR 0x00000002
+#define SSV6XXX_INT_RX 0x00000001
+#define SSV6XXX_INT_TX 0x00000002
+#define SSV6XXX_INT_SOC 0x00000004
+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
+#define IFDEV(_ct) ((_ct)->shi->dev)
+#define IFOPS(_ct) ((_ct)->shi->if_ops)
+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SAFE_READ(_ct,_adr,_val) IFOPS(_ct)->safe_readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SAFE_WRITE(_ct,_adr,_val) IFOPS(_ct)->safe_writereg(IFDEV(_ct), _adr, _val)
+#define HCI_BURST_REG_READ(_ct,_adr,_val,_num) IFOPS(_ct)->burst_readreg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_WRITE(_ct,_adr,_val,_num) IFOPS(_ct)->burst_writereg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_SAFE_READ(_ct,_adr,_val,_num) IFOPS(_ct)->burst_safe_readreg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_SAFE_WRITE(_ct,_adr,_val,_num) IFOPS(_ct)->burst_safe_writereg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
+{ \
+ u32 _regval; \
+ if(HCI_REG_READ(_ct, _reg, &_regval)); \
+ _regval &= ~(_clr); \
+ _regval |= (_set); \
+ if(HCI_REG_WRITE(_ct, _reg, _regval)); \
+}
+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
+#define IF_RECV(_ct,_bf,_len,_mode) IFOPS(_ct)->read(IFDEV(_ct), _bf, _len, _mode)
+#define HCI_LOAD_FW(_ct,_addr,_data,_size) IFOPS(_ct)->load_fw(IFDEV(_ct), _addr, _data, _size)
+struct ssv6xxx_hci_ctrl {
+ struct ssv6xxx_hci_info *shi;
+ u32 hci_flags;
+ int write_hw_config;
+ spinlock_t int_lock;
+ u32 int_status;
+ u32 int_mask;
+ struct mutex txq_mask_lock;
+ u32 txq_mask;
+ struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
+ struct mutex hci_mutex;
+ bool hci_start;
+ bool redownload;
+ struct sk_buff *rx_buf;
+ u32 rx_pkt;
+ struct workqueue_struct *hci_work_queue;
+ struct work_struct hci_rx_work;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ struct work_struct hci_tx_work;
+#else
+ struct work_struct hci_tx_work[SSV_HW_TXQ_NUM];
+#endif
+ wait_queue_head_t tx_wait_q;
+ struct task_struct *hci_tx_task;
+ u32 read_rs0_info_fail;
+ u32 read_rs1_info_fail;
+ u32 rx_work_running;
+ u32 isr_running;
+ u32 xmit_running;
+ u32 isr_disable;
+ u32 isr_summary_eable;
+ u32 isr_routine_time;
+ u32 isr_tx_time;
+ u32 isr_rx_time;
+ u32 isr_idle_time;
+ u32 isr_rx_idle_time;
+ u32 isr_miss_cnt;
+ unsigned long prev_isr_jiffes;
+ unsigned long prev_rx_isr_jiffes;
+ struct work_struct isr_reset_work;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+ u32 isr_mib_enable;
+ u32 isr_mib_reset;
+ long long isr_total_time;
+ long long isr_tx_io_time;
+ long long isr_rx_io_time;
+ u32 isr_rx_io_count;
+ u32 isr_tx_io_count;
+ long long isr_rx_proc_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ bool irq_enable;
+ u32 irq_count;
+ u32 invalid_irq_count;
+ u32 tx_irq_count;
+ u32 real_tx_irq_count;
+ u32 rx_irq_count;
+ u32 irq_rx_pkt_count;
+ u32 irq_tx_pkt_count;
+#endif
+ struct ssv6xxx_tx_hw_info tx_info;
+ struct ssv6xxx_rx_hw_info rx_info;
+};
+struct ssv6xxx_hci_txq_info {
+ u32 tx_use_page:8;
+ u32 tx_use_id:6;
+ u32 txq0_size:4;
+ u32 txq1_size:4;
+ u32 txq2_size:5;
+ u32 txq3_size:5;
+};
+struct ssv6xxx_hci_txq_info2 {
+ u32 tx_use_page:9;
+ u32 tx_use_id:8;
+ u32 txq4_size:4;
+ u32 rsvd:11;
+};
+struct ssv6xxx_hw_resource {
+ int free_tx_page;
+ int free_tx_id;
+ int max_tx_frame[SSV_HW_TXQ_NUM];
+};
+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl, irq_handler_t irq_handler)
+{
+ if(hctrl->shi->if_ops->irq_request)
+ hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler, hctrl);
+}
+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->irq_enable)
+ hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->irq_disable)
+ hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
+}
+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl, int *status)
+{
+ if(hctrl->shi->if_ops->irq_getstatus)
+ return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
+ return 0;
+}
+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl, int mask)
+{
+ if(hctrl->shi->if_ops->irq_setmask)
+ hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
+}
+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->irq_trigger)
+ hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->pmu_wakeup)
+ hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
+}
+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8 *data, u32 size)
+{
+ if(hctrl->shi->if_ops->write_sram)
+ return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data, size);
+ return 0;
+}
+static inline bool ssv6xxx_hwif_ready(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->property)
+ return hctrl->shi->if_ops->is_ready(IFDEV(hctrl));
+ return false;
+}
+static inline int ssv6xxx_hwif_property(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->property)
+ return hctrl->shi->if_ops->property(IFDEV(hctrl));
+ return 0;
+}
+static inline void ssv6xxx_hwif_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->load_fw_pre_config_device)
+ hctrl->shi->if_ops->load_fw_pre_config_device(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->load_fw_post_config_device)
+ hctrl->shi->if_ops->load_fw_post_config_device(IFDEV(hctrl));
+}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+static inline void ssv6xxx_hwif_rx_task(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff_head *rxq, void *args),
+ int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#else
+static inline void ssv6xxx_hwif_rx_task(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff *rx_skb, void *args),
+ int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#endif
+{
+ if(hctrl->shi->if_ops->hwif_rx_task)
+ hctrl->shi->if_ops->hwif_rx_task(IFDEV(hctrl), rx_cb, is_rx_q_full, args, pkt);
+}
+static inline void ssv6xxx_hwif_interface_reset(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->interface_reset)
+ hctrl->shi->if_ops->interface_reset(IFDEV(hctrl));
+}
+static inline int ssv6xxx_hwif_start_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+{
+ if(hctrl->shi->if_ops->start_usb_acc)
+ return hctrl->shi->if_ops->start_usb_acc(IFDEV(hctrl), epnum);
+ return 0;
+}
+static inline int ssv6xxx_hwif_stop_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+{
+ if(hctrl->shi->if_ops->stop_usb_acc)
+ return hctrl->shi->if_ops->stop_usb_acc(IFDEV(hctrl), epnum);
+ return 0;
+}
+static inline int ssv6xxx_hwif_jump_to_rom(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if(hctrl->shi->if_ops->jump_to_rom)
+ return hctrl->shi->if_ops->jump_to_rom(IFDEV(hctrl));
+ return 0;
+}
+static inline void ssv6xxx_hwif_sysplf_reset(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value)
+{
+ if(hctrl->shi->if_ops->sysplf_reset)
+ hctrl->shi->if_ops->sysplf_reset(IFDEV(hctrl), addr, value);
+}
+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
+#define HCI_SRAM_WRITE(ct,adr,dat,size) ssv6xxx_hwif_write_sram(ct, adr, dat, size)
+#define HCI_HWIF_READY(ct) ssv6xxx_hwif_ready(ct)
+#define HCI_HWIF_PROPERTY(ct) ssv6xxx_hwif_property(ct)
+#define HCI_LOAD_FW_PRE_CONFIG_DEVICE(ct) ssv6xxx_hwif_load_fw_pre_config_device(ct)
+#define HCI_LOAD_FW_POST_CONFIG_DEVICE(ct) ssv6xxx_hwif_load_fw_post_config_device(ct)
+#define HCI_RX_TASK(ct,rx_cb,is_rx_q_full,args,pkt) ssv6xxx_hwif_rx_task(ct, rx_cb, is_rx_q_full, args, pkt)
+#define HCI_IFC_RESET(ct) ssv6xxx_hwif_interface_reset(ct)
+#define HCI_START_USB_ACC(ct,epnum) ssv6xxx_hwif_start_usb_acc(ct, epnum)
+#define HCI_STOP_USB_ACC(ct,epnum) ssv6xxx_hwif_stop_usb_acc(ct, epnum)
+#define HCI_JUMP_TO_ROM(ct) ssv6xxx_hwif_jump_to_rom(ct)
+#define HCI_SYSPLF_RESET(ct,addr,value) ssv6xxx_hwif_sysplf_reset(ct, addr, value)
+#define HCI_DEVICE_TYPE(_hci_ctrl) (HCI_HWIF_PROPERTY(_hci_ctrl) & SSV_HWIF_INTERFACE_MASK)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c
new file mode 100644
index 000000000..f4a126ebc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c
@@ -0,0 +1,1924 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "hctrl.h"
+MODULE_AUTHOR("iComm-semi, Ltd");
+MODULE_DESCRIPTION("HCI driver for SSV6xxx 802.11n wireless LAN cards.");
+MODULE_SUPPORTED_DEVICE("SSV6xxx WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
+static void ssv6xxx_hci_trigger_tx(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ unsigned long flags;
+ u32 status;
+ if (ctrl_hci->isr_disable == true) {
+ wake_up_interruptible(&ctrl_hci->tx_wait_q);
+ } else {
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ mutex_lock(&ctrl_hci->hci_mutex);
+#endif
+ spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+ status = ctrl_hci->int_mask ;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
+ if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+ u32 regval;
+ ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
+ regval = ~ctrl_hci->int_mask;
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ HCI_IRQ_SET_MASK(ctrl_hci, regval);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ } else {
+ ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
+ smp_mb();
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->shi->dev);
+ }
+ } else {
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ }
+#else
+ {
+ u32 bitno;
+ bitno = ssv6xxx_hci_get_int_bitno(txqid);
+ if ((ctrl_hci->int_mask & BIT(bitno)) == 0) {
+ if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+ queue_work(ctrl_hci->hci_work_queue,&ctrl_hci->hci_tx_work[txqid]);
+ } else {
+ ctrl_hci->int_status |= BIT(bitno);
+ smp_mb();
+ ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->shi->dev);
+ }
+ }
+ }
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+#endif
+ }
+}
+static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err);
+static int ssv6xxx_hci_irq_enable(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
+ HCI_IRQ_ENABLE(ctrl_hci);
+ return 0;
+}
+static int ssv6xxx_hci_irq_disable(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
+ HCI_IRQ_DISABLE(ctrl_hci);
+ return 0;
+}
+static void ssv6xxx_hci_irq_register(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 irq_mask)
+{
+ unsigned long flags;
+ u32 regval;
+ mutex_lock(&ctrl_hci->hci_mutex);
+ spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+ ctrl_hci->int_mask |= irq_mask;
+ regval = ~ctrl_hci->int_mask;
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ smp_mb();
+ HCI_IRQ_SET_MASK(ctrl_hci, regval);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+}
+static inline u32 ssv6xxx_hci_get_int_bitno(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+{
+ if(txqid == SSV_HW_TXQ_NUM-1)
+ return 1;
+ else
+ return txqid+3;
+}
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id)
+{
+ return;
+}
+void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ if (HCI_REG_WRITE(ctrl_hci, ADR_BRG_SW_RST, 0x1));
+}
+int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ u32 clk_en;
+ if (HCI_REG_WRITE(ctrl_hci, ADR_BRG_SW_RST, 0x0));
+ if (HCI_REG_WRITE(ctrl_hci, ADR_BOOT, 0x0));
+ if (HCI_REG_READ(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, &clk_en));
+ if (HCI_REG_WRITE(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, (clk_en | (1 << 2))));
+ return 0;
+}
+int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status)
+{
+ return HCI_REG_WRITE(ctrl_hci, ADR_TX_SEG, status);
+}
+int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status)
+{
+ return HCI_REG_READ(ctrl_hci, ADR_TX_SEG, status);
+}
+int ssv6xxx_hci_reset_cpu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ u32 reset;
+ if (HCI_REG_READ(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, &reset));
+ if (HCI_REG_WRITE(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, reset & ~(1 << 24)));
+ return 0;
+}
+void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_LOAD_FW_PRE_CONFIG_DEVICE(ctrl_hci);
+}
+void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_LOAD_FW_POST_CONFIG_DEVICE(ctrl_hci);
+}
+#endif
+static void *ssv6xxx_hci_open_firmware(char *user_mainfw)
+{
+ struct file *fp;
+ fp = filp_open(user_mainfw, O_RDONLY, 0);
+ if (IS_ERR(fp))
+ fp = NULL;
+ return fp;
+}
+static int ssv6xxx_hci_read_fw_block(char *buf, int len, void *image)
+{
+ struct file *fp = (struct file *)image;
+ int rdlen;
+ if (!image)
+ return 0;
+ rdlen = kernel_read(fp, fp->f_pos, buf, len);
+ if (rdlen > 0)
+ fp->f_pos += rdlen;
+ return rdlen;
+}
+static void ssv6xxx_hci_close_firmware(void *image)
+{
+ if (image)
+ filp_close((struct file *)image, NULL);
+}
+static int ssv6xxx_hci_load_firmware_openfile(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+{
+ int ret = 0;
+ u8 *fw_buffer = NULL;
+ u32 sram_addr = FW_START_SRAM_ADDR;
+ u32 block_count = 0;
+ u32 res_size=0, len=0, tolen=0;
+ void *fw_fp = NULL;
+ u8 interface = HCI_DEVICE_TYPE(hci_ctrl);
+#ifdef ENABLE_FW_SELF_CHECK
+ u32 checksum = FW_CHECKSUM_INIT;
+ u32 fw_checksum, fw_clkcnt;
+ u32 retry_count = 3;
+ u32 *fw_data32;
+#else
+ int writesize = 0;
+ u32 retry_count = 1;
+#endif
+ u32 word_count, i;
+ if (hci_ctrl->redownload == 1) {
+ HCI_DBG_PRINT(hci_ctrl, "Re-download FW\n");
+ HCI_JUMP_TO_ROM(hci_ctrl);
+ }
+ fw_fp = ssv6xxx_hci_open_firmware(firmware_name);
+ if (!fw_fp) {
+ HCI_DBG_PRINT(hci_ctrl, "failed to find firmware (%s)\n", firmware_name);
+ ret = -1;
+ goto out;
+ }
+ fw_buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+ if (fw_buffer == NULL) {
+ HCI_DBG_PRINT(hci_ctrl, "Failed to allocate buffer for firmware.\n");
+ goto out;
+ }
+ do {
+ if (!(interface == SSV_HWIF_INTERFACE_USB)) {
+ ret = SSV_LOAD_FW_DISABLE_MCU(hci_ctrl);
+ if (ret == -1)
+ goto out;
+ }
+ HCI_DBG_PRINT(hci_ctrl, "Writing firmware to SSV6XXX...\n");
+ memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+ while ((len = ssv6xxx_hci_read_fw_block((char*)fw_buffer, FW_BLOCK_SIZE, fw_fp))) {
+ tolen += len;
+ if (len < FW_BLOCK_SIZE) {
+ res_size = len;
+ break;
+ }
+ if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+ break;
+ sram_addr += FW_BLOCK_SIZE;
+ word_count = (len / sizeof(u32));
+ fw_data32 = (u32 *)fw_buffer;
+ for (i = 0; i < word_count; i++) {
+ checksum += fw_data32[i];
+ }
+ memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+ }
+ if(res_size) {
+ u32 cks_blk_cnt,cks_blk_res;
+ cks_blk_cnt = res_size / CHECKSUM_BLOCK_SIZE;
+ cks_blk_res = res_size % CHECKSUM_BLOCK_SIZE;
+ ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, (cks_blk_cnt+1)*CHECKSUM_BLOCK_SIZE);
+ word_count = (cks_blk_cnt * CHECKSUM_BLOCK_SIZE / sizeof(u32));
+ fw_data32 = (u32 *)fw_buffer;
+ for (i = 0; i < word_count; i++)
+ checksum += *fw_data32++;
+ if(cks_blk_res) {
+ word_count = (CHECKSUM_BLOCK_SIZE / sizeof(u32));
+ for (i = 0; i < word_count; i++) {
+ checksum += *fw_data32++;
+ }
+ }
+ }
+ checksum = ((checksum >> 24) + (checksum >> 16) + (checksum >> 8) + checksum) & 0x0FF;
+ checksum <<= 16;
+ if (ret == 0) {
+ if (interface == SSV_HWIF_INTERFACE_USB) {
+ ret = SSV_RESET_CPU(hci_ctrl);
+ if (ret == -1)
+ goto out;
+ }
+ SSV_SET_SRAM_MODE(hci_ctrl, SRAM_MODE_ILM_160K_DLM_32K);
+ block_count = tolen / CHECKSUM_BLOCK_SIZE;
+ res_size = tolen % CHECKSUM_BLOCK_SIZE;
+ if(res_size)
+ block_count++;
+ SSV_LOAD_FW_SET_STATUS(hci_ctrl, (block_count << 16));
+ SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_clkcnt);
+ HCI_DBG_PRINT(hci_ctrl, "(block_count << 16) = %x,reg =%x\n", (block_count << 16),fw_clkcnt);
+ SSV_LOAD_FW_ENABLE_MCU(hci_ctrl);
+ HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" loaded\n", firmware_name);
+ msleep(50);
+ SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_checksum);
+ fw_checksum = fw_checksum & FW_STATUS_MASK;
+ if (fw_checksum == checksum) {
+ SSV_LOAD_FW_SET_STATUS(hci_ctrl, (~checksum & FW_STATUS_MASK));
+ ret = 0;
+ HCI_DBG_PRINT(hci_ctrl, "Firmware check OK.%04x = %04x\n", fw_checksum, checksum);
+ break;
+ } else {
+ HCI_DBG_PRINT(hci_ctrl, "FW checksum error: %04x != %04x\n", fw_checksum, checksum);
+ ret = -1;
+ }
+ } else {
+ HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" download failed. (%d)\n", firmware_name, ret);
+ ret = -1;
+ }
+ } while (--retry_count);
+ if (ret)
+ goto out;
+ hci_ctrl->redownload = 1;
+ ret = 0;
+out:
+ if(fw_fp)
+ ssv6xxx_hci_close_firmware(fw_fp);
+ if (fw_buffer != NULL)
+ kfree(fw_buffer);
+ return ret;
+}
+static int ssv6xxx_hci_get_firmware(struct device *dev, char *user_mainfw, const struct firmware **mainfw)
+{
+ int ret;
+ BUG_ON(mainfw == NULL);
+ if (*user_mainfw) {
+ ret = request_firmware(mainfw, user_mainfw, dev);
+ if (ret) {
+ goto fail;
+ }
+ if (*mainfw)
+ return 0;
+ }
+fail:
+ if (*mainfw) {
+ release_firmware(*mainfw);
+ *mainfw = NULL;
+ }
+ return -ENOENT;
+}
+static int ssv6xxx_hci_load_firmware_request(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+{
+ int ret = 0;
+ const struct firmware *ssv6xxx_fw = NULL;
+ u8 *fw_buffer = NULL;
+ u32 sram_addr = FW_START_SRAM_ADDR;
+ u32 block_count = 0;
+ u32 block_idx = 0;
+ u32 res_size;
+ u8 *fw_data;
+ u8 interface = HCI_DEVICE_TYPE(hci_ctrl);
+#ifdef ENABLE_FW_SELF_CHECK
+ u32 checksum = FW_CHECKSUM_INIT;
+ u32 fw_checksum;
+ u32 retry_count = 3;
+ u32 *fw_data32;
+#else
+ int writesize = 0;
+ u32 retry_count = 1;
+#endif
+ if (hci_ctrl->redownload == 1) {
+ HCI_DBG_PRINT(hci_ctrl, "Re-download FW\n");
+ HCI_JUMP_TO_ROM(hci_ctrl);
+ }
+ ret = ssv6xxx_hci_get_firmware(hci_ctrl->shi->dev, firmware_name, &ssv6xxx_fw);
+ if (ret) {
+ HCI_DBG_PRINT(hci_ctrl, "failed to find firmware (%d)\n", ret);
+ goto out;
+ }
+ fw_buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+ if (fw_buffer == NULL) {
+ HCI_DBG_PRINT(hci_ctrl, "Failed to allocate buffer for firmware.\n");
+ goto out;
+ }
+#ifdef ENABLE_FW_SELF_CHECK
+ block_count = ssv6xxx_fw->size / CHECKSUM_BLOCK_SIZE;
+ res_size = ssv6xxx_fw->size % CHECKSUM_BLOCK_SIZE;
+ {
+ int word_count = (int)(block_count * CHECKSUM_BLOCK_SIZE / sizeof(u32));
+ int i;
+ fw_data32 = (u32 *)ssv6xxx_fw->data;
+ for (i = 0; i < word_count; i++)
+ checksum += fw_data32[i];
+ if (res_size) {
+ memset(fw_buffer, 0xA5, CHECKSUM_BLOCK_SIZE);
+ memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * CHECKSUM_BLOCK_SIZE], res_size);
+ word_count = (int)(CHECKSUM_BLOCK_SIZE / sizeof(u32));
+ fw_data32 = (u32 *)fw_buffer;
+ for (i = 0; i < word_count; i++) {
+ checksum += fw_data32[i];
+ }
+ }
+ }
+ checksum = ((checksum >> 24) + (checksum >> 16) + (checksum >> 8) + checksum) & 0x0FF;
+ checksum <<= 16;
+#endif
+ do {
+ if (!(interface == SSV_HWIF_INTERFACE_USB)) {
+ ret = SSV_LOAD_FW_DISABLE_MCU(hci_ctrl);
+ if (ret == -1)
+ goto out;
+ }
+#ifdef ENABLE_FW_SELF_CHECK
+ block_count = ssv6xxx_fw->size / FW_BLOCK_SIZE;
+ res_size = ssv6xxx_fw->size % FW_BLOCK_SIZE;
+ HCI_DBG_PRINT(hci_ctrl, "Writing %d blocks to SSV6XXX...", block_count);
+ for (block_idx = 0, fw_data = (u8 *)ssv6xxx_fw->data, sram_addr = 0; block_idx < block_count;
+ block_idx++, fw_data += FW_BLOCK_SIZE, sram_addr += FW_BLOCK_SIZE) {
+ memcpy(fw_buffer, fw_data, FW_BLOCK_SIZE);
+ if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+ break;
+ }
+ if(res_size) {
+ memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+ memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * FW_BLOCK_SIZE], res_size);
+ if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer,
+ ((res_size/CHECKSUM_BLOCK_SIZE)+1)*CHECKSUM_BLOCK_SIZE)) != 0)
+ break;
+ }
+#else
+ block_count = ssv6xxx_fw->size / FW_BLOCK_SIZE;
+ res_size = ssv6xxx_fw->size % FW_BLOCK_SIZE;
+ writesize = sdio_align_size(func,res_size);
+ HCI_DBG_PRINT(hci_ctrl, "Writing %d blocks to SSV6XXX...", block_count);
+ for (block_idx = 0, fw_data = (u8 *)ssv6xxx_fw->data, sram_addr = 0; block_idx < block_count;
+ block_idx++, fw_data += FW_BLOCK_SIZE, sram_addr += FW_BLOCK_SIZE) {
+ memcpy(fw_buffer, fw_data, FW_BLOCK_SIZE);
+ if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+ break;
+ }
+ if(res_size) {
+ memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * FW_BLOCK_SIZE], res_size);
+ if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, writesize)) != 0)
+ break;
+ }
+#endif
+ if (ret == 0) {
+ if (interface == SSV_HWIF_INTERFACE_USB) {
+ ret = SSV_RESET_CPU(hci_ctrl);
+ if (ret == -1)
+ goto out;
+ }
+ SSV_SET_SRAM_MODE(hci_ctrl, SRAM_MODE_ILM_160K_DLM_32K);
+#ifdef ENABLE_FW_SELF_CHECK
+ block_count = ssv6xxx_fw->size / CHECKSUM_BLOCK_SIZE;
+ res_size = ssv6xxx_fw->size % CHECKSUM_BLOCK_SIZE;
+ if(res_size)
+ block_count++;
+ SSV_LOAD_FW_SET_STATUS(hci_ctrl, (block_count << 16));
+#endif
+ SSV_LOAD_FW_ENABLE_MCU(hci_ctrl);
+ HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" loaded\n", firmware_name);
+#ifdef ENABLE_FW_SELF_CHECK
+ msleep(50);
+ SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_checksum);
+ fw_checksum = fw_checksum & FW_STATUS_MASK;
+ if (fw_checksum == checksum) {
+ SSV_LOAD_FW_SET_STATUS(hci_ctrl, (~checksum & FW_STATUS_MASK));
+ ret = 0;
+ HCI_DBG_PRINT(hci_ctrl, "Firmware check OK.\n");
+ break;
+ } else {
+ HCI_DBG_PRINT(hci_ctrl, "FW checksum error: %04x != %04x\n", fw_checksum, checksum);
+ ret = -1;
+ }
+#endif
+ } else {
+ HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" download failed. (%d)\n", firmware_name, ret);
+ ret = -1;
+ }
+ } while (--retry_count);
+ if (ret)
+ goto out;
+ hci_ctrl->redownload = 1;
+ ret = 0;
+out:
+ if (ssv6xxx_fw)
+ release_firmware(ssv6xxx_fw);
+ if (fw_buffer != NULL)
+ kfree(fw_buffer);
+ return ret;
+}
+static int ssv6xxx_hci_start_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_START_USB_ACC(ctrl_hci, 4);
+ return 0;
+}
+static int ssv6xxx_hci_stop_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_STOP_USB_ACC(ctrl_hci, 4);
+ return 0;
+}
+static int ssv6xxx_hci_start(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ ssv6xxx_hci_irq_enable(ctrl_hci);
+ ssv6xxx_hci_start_acc(ctrl_hci);
+ ctrl_hci->hci_start = true;
+ HCI_IRQ_TRIGGER(ctrl_hci);
+ return 0;
+}
+static int ssv6xxx_hci_stop(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ ssv6xxx_hci_irq_disable(ctrl_hci);
+ ssv6xxx_hci_stop_acc(ctrl_hci);
+ ctrl_hci->hci_start = false;
+ return 0;
+}
+static void ssv6xxx_hci_write_hw_config(struct ssv6xxx_hci_ctrl *ctrl_hci, int val)
+{
+ ctrl_hci->write_hw_config = val;
+}
+static int ssv6xxx_hci_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+{
+ int ret = HCI_REG_READ(ctrl_hci, addr, regval);
+ return ret;
+}
+static int ssv6xxx_hci_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+{
+ int ret = HCI_REG_SAFE_READ(ctrl_hci, addr, regval);
+ return ret;
+}
+static int ssv6xxx_hci_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+{
+ if (ctrl_hci->write_hw_config && (ctrl_hci->shi->write_hw_config_cb != NULL))
+ ctrl_hci->shi->write_hw_config_cb((void *)SSV_SC(ctrl_hci), addr, regval);
+ return HCI_REG_WRITE(ctrl_hci, addr, regval);
+}
+static int ssv6xxx_hci_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+{
+ if (ctrl_hci->write_hw_config && (ctrl_hci->shi->write_hw_config_cb != NULL))
+ ctrl_hci->shi->write_hw_config_cb((void *)SSV_SC(ctrl_hci), addr, regval);
+ return HCI_REG_SAFE_WRITE(ctrl_hci, addr, regval);
+}
+static int ssv6xxx_hci_burst_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+ int ret = HCI_BURST_REG_READ(ctrl_hci, addr, regval, reg_amount);
+ return ret;
+}
+static int ssv6xxx_hci_burst_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+ return HCI_BURST_REG_WRITE(ctrl_hci, addr, regval, reg_amount);
+}
+static int ssv6xxx_hci_burst_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+ int ret = HCI_BURST_REG_SAFE_READ(ctrl_hci, addr, regval, reg_amount);
+ return ret;
+}
+static int ssv6xxx_hci_burst_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+ return HCI_BURST_REG_SAFE_WRITE(ctrl_hci, addr, regval, reg_amount);
+}
+static int ssv6xxx_hci_load_fw(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name, u8 openfile)
+{
+ int ret = 0;
+ SSV_LOAD_FW_PRE_CONFIG_DEVICE(hci_ctrl);
+ if (openfile)
+ ret = ssv6xxx_hci_load_firmware_openfile(hci_ctrl, firmware_name);
+ else
+ ret = ssv6xxx_hci_load_firmware_request(hci_ctrl, firmware_name);
+ msleep(50);
+ if (ret == 0)
+ SSV_LOAD_FW_POST_CONFIG_DEVICE(hci_ctrl);
+ return ret;
+}
+static int ssv6xxx_hci_write_sram(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u8 *data, u32 size)
+{
+ return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
+}
+static int ssv6xxx_hci_pmu_wakeup(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_PMU_WAKEUP(ctrl_hci);
+ return 0;
+}
+static int ssv6xxx_hci_interface_reset(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ HCI_IFC_RESET(ctrl_hci);
+ return 0;
+}
+static int ssv6xxx_hci_sysplf_reset(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 value)
+{
+ HCI_SYSPLF_RESET(ctrl_hci, addr, value);
+ return 0;
+}
+static int ssv6xxx_hci_send_cmd(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb)
+{
+ int ret;
+ ret = IF_SEND(ctrl_hci, (void *)skb, skb->len, 0);
+ if (ret < 0) {
+ HCI_DBG_PRINT(ctrl_hci, "ssv6xxx_hci_send_cmd fail......\n");
+ }
+ return ret;
+}
+static int ssv6xxx_hci_enqueue(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb, int txqid, u32 tx_flags)
+{
+ struct ssv_hw_txq *hw_txq;
+ int qlen = 0;
+ BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
+ if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
+ return -1;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ hw_txq->tx_flags = tx_flags;
+ if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
+ skb_queue_head(&hw_txq->qhead, skb);
+ else
+ skb_queue_tail(&hw_txq->qhead, skb);
+ qlen = (int)skb_queue_len(&hw_txq->qhead);
+ if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+ if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
+ ctrl_hci->shi->hci_tx_flow_ctrl_cb(
+ (void *)SSV_SC(ctrl_hci),
+ hw_txq->txq_no,
+ true,2000
+ );
+ }
+ }
+ ssv6xxx_hci_trigger_tx(ctrl_hci);
+ return qlen;
+}
+static bool ssv6xxx_hci_is_txq_empty(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+{
+ struct ssv_hw_txq *hw_txq;
+ BUG_ON(txqid >= SSV_HW_TXQ_NUM);
+ if (txqid >= SSV_HW_TXQ_NUM)
+ return false;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ if (skb_queue_len(&hw_txq->qhead) <= 0)
+ return true;
+ return false;
+}
+static int ssv6xxx_hci_txq_flush(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ struct sk_buff *skb = NULL;
+ int txqid;
+ for(txqid=0; txqidhw_txq[txqid];
+ while((skb = skb_dequeue(&hw_txq->qhead))) {
+ ctrl_hci->shi->hci_tx_buf_free_cb (skb, (void *)SSV_SC(ctrl_hci));
+ }
+ }
+ return 0;
+}
+static int ssv6xxx_hci_txq_flush_by_sta(struct ssv6xxx_hci_ctrl *ctrl_hci, int aid)
+{
+ return 0;
+}
+static int ssv6xxx_hci_txq_pause(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ int txqid;
+#ifdef SSV_SUPPORT_HAL
+ struct ssv_hw *sh;
+ if (SSV_SC(ctrl_hci) == NULL) {
+ HCI_DBG_PRINT(ctrl_hci, "%s: can't pause due to software structure not initialized !!\n", __func__);
+ return 1;
+ }
+ sh = ctrl_hci->shi->sh;
+#endif
+ mutex_lock(&ctrl_hci->txq_mask_lock);
+ ctrl_hci->txq_mask |= (txq_mask & 0x1F);
+ for(txqid=0; txqidtxq_mask&(1<hw_txq[txqid];
+ hw_txq->paused = true;
+ }
+#ifdef SSV_SUPPORT_HAL
+ HAL_UPDATE_TXQ_MASK(sh, ctrl_hci->txq_mask);
+#else
+ HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+ (ctrl_hci->txq_mask << MTX_HALT_Q_MB_SFT), MTX_HALT_Q_MB_MSK);
+#endif
+ mutex_unlock(&ctrl_hci->txq_mask_lock);
+ return 0;
+}
+static int ssv6xxx_hci_txq_resume(struct ssv6xxx_hci_ctrl *hci_ctrl, u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ int txqid;
+#ifdef SSV_SUPPORT_HAL
+ struct ssv_hw *sh;
+ if (SSV_SC(hci_ctrl) == NULL) {
+ HCI_DBG_PRINT(hci_ctrl, "%s: can't resume due to software structure not initialized !!\n", __func__);
+ return 1;
+ }
+ sh = hci_ctrl->shi->sh;
+#endif
+ mutex_lock(&hci_ctrl->txq_mask_lock);
+ hci_ctrl->txq_mask &= ~(txq_mask & 0x1F);
+#ifdef SSV_SUPPORT_HAL
+ HAL_UPDATE_TXQ_MASK(sh, hci_ctrl->txq_mask);
+#else
+ HCI_REG_SET_BITS(hci_ctrl, ADR_MTX_MISC_EN,
+ (hci_ctrl->txq_mask << MTX_HALT_Q_MB_SFT), MTX_HALT_Q_MB_MSK);
+#endif
+ for(txqid=0; txqidtxq_mask&(1<hw_txq[txqid];
+ hw_txq->paused = false;
+ }
+ mutex_unlock(&hci_ctrl->txq_mask_lock);
+ ssv6xxx_hci_trigger_tx(hci_ctrl);
+ return 0;
+}
+static int ssv6xxx_hci_force_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq,
+ int max_count, int *err, int free_tx_page)
+{
+ struct sk_buff_head tx_cb_list;
+ struct sk_buff *skb = NULL;
+ int tx_count, ret;
+ int reason = -1, page_count;
+ struct ssv6xxx_hci_info *shi = hci_ctrl->shi;
+#ifdef SSV_SUPPORT_HAL
+ struct ssv_hw *sh;
+#else
+ struct ssv6200_tx_desc *tx_desc = NULL;
+#endif
+ hci_ctrl->xmit_running = 1;
+ skb_queue_head_init(&tx_cb_list);
+ for (tx_count=0; tx_counthci_start == false) || (hw_txq->paused)) {
+ HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_force_xmit - hci_start = false\n");
+ *err = 1;
+ goto xmit_out;
+ }
+ skb = skb_dequeue(&hw_txq->qhead);
+ if (!skb) {
+ goto xmit_out;
+ }
+ if (free_tx_page != TX_PAGE_NOT_LIMITED ) {
+ page_count = (skb->len + SSV6200_ALLOC_RSVD);
+ if (page_count & HW_MMU_PAGE_MASK)
+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+ else
+ page_count = page_count >> HW_MMU_PAGE_SHIFT;
+ if (page_count > (SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2))
+ HCI_DBG_PRINT(hci_ctrl, "Asking page %d(%d) exceeds resource limit %d.\n",
+ page_count, skb->len,(SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2));
+ if (free_tx_page < page_count) {
+ skb_queue_head(&hw_txq->qhead, skb);
+ break;
+ }
+ free_tx_page -= page_count;
+ }
+#ifdef SSV_SUPPORT_HAL
+ sh = shi->sh;
+ reason = HAL_GET_TX_DESC_REASON(sh, skb);
+#else
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ reason = tx_desc->reason;
+#endif
+#if 1
+ if (shi->hci_skb_update_cb != NULL && reason != ID_TRAP_SW_TXTPUT) {
+ shi->hci_skb_update_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+ }
+#endif
+ if (shi->hci_pre_tx_cb)
+ shi->hci_pre_tx_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+ ret = IF_SEND(hci_ctrl, (void *)skb, skb->len, hw_txq->txq_no);
+ if (ret < 0) {
+ HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_force_xmit fail[%d]......\n", ret);
+ *err = ret;
+ skb_queue_head(&hw_txq->qhead, skb);
+ break;
+ }
+ if (reason != ID_TRAP_SW_TXTPUT)
+ skb_queue_tail(&tx_cb_list, skb);
+ else
+ shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+ hw_txq->tx_pkt ++;
+ if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+ shi->hci_tx_flow_ctrl_cb(
+ (void *)(SSV_SC(hci_ctrl)),
+ hw_txq->txq_no, false, 2000);
+ }
+ }
+xmit_out:
+ if (shi->hci_post_tx_cb && reason != -1 && reason != ID_TRAP_SW_TXTPUT) {
+ shi->hci_post_tx_cb (&tx_cb_list, (void *)(SSV_SC(hci_ctrl)));
+ }
+ hci_ctrl->xmit_running = 0;
+ return tx_count;
+}
+static int ssv6xxx_hci_force_tx_handler(struct ssv6xxx_hci_ctrl *hci_ctrl, void *dev,
+ int max_count, int *err)
+{
+ struct ssv_hw_txq *hw_txq=dev;
+ int tx_count=0;
+ struct ssv6xxx_hci_info *shi = hci_ctrl->shi;
+ int hci_free_id = 0, hci_used_id = -1;
+ int free_tx_page = TX_PAGE_NOT_LIMITED, tx_use_page = -1;
+ max_count = skb_queue_len(&hw_txq->qhead);
+ if (max_count == 0)
+ return 0;
+ if ((hci_ctrl->hci_start == false) || (hw_txq->paused)) {
+ *err = 1;
+ return 0;
+ }
+ if (shi->sh->cfg.usb_hw_resource != USB_HW_RESOURCE_CHK_NONE ) {
+ SSV_READRG_HCI_INQ_INFO(hci_ctrl, &hci_used_id, & tx_use_page);
+ if ((hci_used_id == -1) || (tx_use_page == -1)) {
+ *err = -EIO;
+ return 0;
+ }
+ if (shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXID ) {
+ if (hci_used_id != -1) {
+ hci_free_id = SSV6XXX_ID_HCI_INPUT_QUEUE - hci_used_id;
+ if (hci_free_id == 0) {
+ *err = 2;
+ return 0;
+ }
+ if (max_count > hci_free_id)
+ max_count = hci_free_id;
+ }
+ }
+ if ((shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXPAGE) ||
+ (shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_SCAN)) {
+ free_tx_page = SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) - tx_use_page;
+ if (free_tx_page < 0) {
+ *err = 2;
+ return 0;
+ }
+ }
+ }
+ tx_count = ssv6xxx_hci_force_xmit(hci_ctrl, hw_txq, max_count, err, free_tx_page);
+ if ( (shi->hci_tx_q_empty_cb != NULL)
+ && (skb_queue_len(&hw_txq->qhead) == 0)) {
+ shi->hci_tx_q_empty_cb(hw_txq->txq_no, (void *)(SSV_SC(hci_ctrl)));
+ }
+ return tx_count;
+}
+static int _do_force_tx (struct ssv6xxx_hci_ctrl *hctl, int *err)
+{
+ int q_num;
+ int tx_count = 0;
+ struct ssv_hw_txq *hw_txq;
+ u32 dev_type = HCI_DEVICE_TYPE(hctl);
+ int (*handler)(struct ssv6xxx_hci_ctrl *, void *, int, int *);
+ if ((dev_type == SSV_HWIF_INTERFACE_USB) &&
+ ( (hctl->shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXID ) == 0)) {
+ handler = ssv6xxx_hci_force_tx_handler;
+ } else {
+ handler = ssv6xxx_hci_usb_tx_handler;
+ }
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ hw_txq = &hctl->hw_txq[q_num];
+ tx_count += handler(hctl, hw_txq, 999, err);
+ if (*err < 0)
+ break;
+ }
+ return tx_count;
+}
+static int ssv6xxx_hci_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq, int max_count, struct ssv6xxx_hw_resource *phw_resource)
+{
+ struct sk_buff_head tx_cb_list;
+ struct sk_buff *skb = NULL;
+ int tx_count = 0, ret = 0, page_count;
+ int reason = -1;
+#ifdef SSV_SUPPORT_HAL
+ struct ssv_hw *sh;
+#else
+ struct ssv6200_tx_desc *tx_desc = NULL;
+#endif
+ hci_ctrl->xmit_running = 1;
+ skb_queue_head_init(&tx_cb_list);
+ for(tx_count=0; tx_counthci_start == false) || (hw_txq->paused)) {
+ HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit - hci_start = false\n");
+ goto xmit_out;
+ }
+ skb = skb_dequeue(&hw_txq->qhead);
+ if (!skb) {
+ HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit - queue empty\n");
+ goto xmit_out;
+ }
+ page_count = (skb->len + SSV6200_ALLOC_RSVD);
+ if (page_count & HW_MMU_PAGE_MASK)
+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+ else
+ page_count = page_count >> HW_MMU_PAGE_SHIFT;
+ if (page_count > (SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2))
+ HCI_DBG_PRINT(hci_ctrl, "Asking page %d(%d) exceeds resource limit %d.\n",
+ page_count, skb->len,(SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2));
+ if (page_count > SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl)) {
+ printk("Asking page %d(%d) > %d is impossible to send. Drop it!\n", page_count, skb->len, SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl));
+ hci_ctrl->shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+ break;
+ }
+ if ((phw_resource->free_tx_page < page_count) || (phw_resource->free_tx_id <= 0) || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
+ skb_queue_head(&hw_txq->qhead, skb);
+ udelay(1);
+ break;
+ }
+ phw_resource->free_tx_page -= page_count;
+ phw_resource->free_tx_id--;
+ phw_resource->max_tx_frame[hw_txq->txq_no]--;
+#ifdef SSV_SUPPORT_HAL
+ sh = hci_ctrl->shi->sh;
+ reason = HAL_GET_TX_DESC_REASON(sh, skb);
+#else
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ reason = tx_desc->reason;
+#endif
+#if 1
+ if (hci_ctrl->shi->hci_skb_update_cb != NULL && reason != ID_TRAP_SW_TXTPUT) {
+ hci_ctrl->shi->hci_skb_update_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+ }
+#endif
+ if (hci_ctrl->shi->hci_pre_tx_cb)
+ hci_ctrl->shi->hci_pre_tx_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+ ret = IF_SEND(hci_ctrl, (void *)skb, skb->len, hw_txq->txq_no);
+ if (ret < 0) {
+ HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit fail......\n");
+ skb_queue_head(&hw_txq->qhead, skb);
+ break;
+ }
+ if (reason != ID_TRAP_SW_TXTPUT)
+ skb_queue_tail(&tx_cb_list, skb);
+ else
+ hci_ctrl->shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+ hw_txq->tx_pkt ++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (hci_ctrl->irq_enable)
+ hci_ctrl->irq_tx_pkt_count++;
+#endif
+ if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+ hci_ctrl->shi->hci_tx_flow_ctrl_cb(
+ (void *)(SSV_SC(hci_ctrl)),
+ hw_txq->txq_no, false, 2000);
+ }
+ }
+xmit_out:
+ if (hci_ctrl->shi->hci_post_tx_cb && reason != -1 && reason != ID_TRAP_SW_TXTPUT) {
+ hci_ctrl->shi->hci_post_tx_cb (&tx_cb_list, (void *)(SSV_SC(hci_ctrl)));
+ }
+ hci_ctrl->xmit_running = 0;
+ return (ret == 0) ? tx_count : ret;
+}
+static int ssv6xxx_hci_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count)
+{
+ struct ssv6xxx_hci_txq_info txq_info;
+ struct ssv6xxx_hci_txq_info2 txq_info2;
+ struct ssv6xxx_hw_resource hw_resource;
+ struct ssv_hw_txq *hw_txq=dev;
+ int hci_used_id = -1;
+ int ret, tx_count=0;
+ max_count = skb_queue_len(&hw_txq->qhead);
+ if ((max_count == 0) || (hw_txq->paused))
+ return 0;
+ if (hw_txq->txq_no == 4) {
+#ifndef _x86_64
+retry_read:
+#endif
+#ifdef SSV_SUPPORT_HAL
+ if (SSV_SC(ctrl_hci) != NULL)
+ ret = HAL_READRG_TXQ_INFO2(ctrl_hci->shi->sh,(u32 *)&txq_info2, &hci_used_id);
+ else {
+ HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info2 due to software structure not initialized !!\n", __func__);
+ return 0;
+ }
+#else
+ ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2, (u32 *)&txq_info2);
+#endif
+ if (ret < 0) {
+ ctrl_hci->read_rs1_info_fail++;
+ return 0;
+ }
+#ifdef _x86_64
+ BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page);
+ BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id);
+#else
+ if(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page)
+ goto retry_read;
+ if(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id)
+ goto retry_read;
+ if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+ goto retry_read;
+#endif
+ hw_resource.free_tx_page =(int)
+ SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int)txq_info2.tx_use_page;
+ hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int)txq_info2.tx_use_id;
+ hw_resource.max_tx_frame[4] = (int)SSV6XXX_ID_MANAGER_QUEUE(ctrl_hci) - (int)txq_info2.txq4_size;
+ if (hci_used_id != -1)
+ max_count = (int) SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+ } else {
+#ifdef SSV_SUPPORT_HAL
+ if (SSV_SC(ctrl_hci) != NULL)
+ ret = HAL_READRG_TXQ_INFO(ctrl_hci->shi->sh,(u32 *)&txq_info, &hci_used_id);
+ else {
+ HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info due to software structure not initialized !!\n", __func__);
+ return 0;
+ }
+#else
+ ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO, (u32 *)&txq_info);
+#endif
+ if (ret < 0) {
+ ctrl_hci->read_rs0_info_fail++;
+ return 0;
+ }
+ if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+ return 0;
+ BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_page);
+ BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_id);
+ hw_resource.free_tx_page = (int) SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_page;
+ hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_id;
+ hw_resource.max_tx_frame[0] =
+ (int) SSV6XXX_ID_AC_BK_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq0_size;
+ hw_resource.max_tx_frame[1] =
+ (int)SSV6XXX_ID_AC_BE_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq1_size;
+ hw_resource.max_tx_frame[2] =
+ (int)SSV6XXX_ID_AC_VI_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq2_size;
+ hw_resource.max_tx_frame[3] =
+ (int)SSV6XXX_ID_AC_VO_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq3_size;
+ if (hci_used_id != -1)
+ max_count = (int)SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+ }
+ {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if(ctrl_hci->irq_enable)
+ ctrl_hci->real_tx_irq_count++;
+#endif
+ tx_count = ssv6xxx_hci_xmit(ctrl_hci, hw_txq, max_count, &hw_resource);
+ }
+ if ( (ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+ && (skb_queue_len(&hw_txq->qhead) == 0)) {
+ ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no, SSV_SC(ctrl_hci));
+ }
+ return tx_count;
+}
+static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err)
+{
+ struct ssv6xxx_hci_txq_info txq_info;
+ struct ssv6xxx_hci_txq_info2 txq_info2;
+ struct ssv6xxx_hw_resource hw_resource;
+ struct ssv_hw_txq *hw_txq=dev;
+ int hci_used_id = -1;
+ int ret, tx_count=0;
+ max_count = skb_queue_len(&hw_txq->qhead);
+ if (max_count == 0)
+ return 0;
+ if ((ctrl_hci->hci_start == false) || (hw_txq->paused)) {
+ *err = 1;
+ return 0;
+ }
+ if (hw_txq->txq_no == 4) {
+#ifndef _x86_64
+retry_read:
+#endif
+#ifdef SSV_SUPPORT_HAL
+ if (SSV_SC(ctrl_hci) != NULL)
+ ret = HAL_READRG_TXQ_INFO2(ctrl_hci->shi->sh,(u32 *)&txq_info2, &hci_used_id);
+ else {
+ HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info2 due to software structure not initialized !!\n", __func__);
+ *err = -EIO;
+ return 0;
+ }
+#else
+ ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2, (u32 *)&txq_info2);
+#endif
+ if (ret < 0) {
+ ctrl_hci->read_rs1_info_fail++;
+ *err = -EIO;
+ return 0;
+ }
+#ifdef _x86_64
+ BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page);
+ BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id);
+#else
+ if(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page)
+ goto retry_read;
+ if(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id)
+ goto retry_read;
+ if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+ goto retry_read;
+#endif
+ hw_resource.free_tx_page =
+ SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - txq_info2.tx_use_page;
+ hw_resource.free_tx_id = SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - txq_info2.tx_use_id;
+ hw_resource.max_tx_frame[4] = SSV6XXX_ID_USB_MANAGER_QUEUE(ctrl_hci) - txq_info2.txq4_size;
+ if (hci_used_id != -1)
+ max_count = SSV6XXX_ID_HCI_INPUT_QUEUE - hci_used_id;
+ } else {
+#ifdef SSV_SUPPORT_HAL
+ if (SSV_SC(ctrl_hci) != NULL)
+ ret = HAL_READRG_TXQ_INFO(ctrl_hci->shi->sh,(u32 *)&txq_info, &hci_used_id);
+ else {
+ HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info due to software structure not initialized !!\n", __func__);
+ *err = -EIO;
+ return 0;
+ }
+#else
+ ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO, (u32 *)&txq_info);
+#endif
+ if (ret < 0) {
+ ctrl_hci->read_rs0_info_fail++;
+ *err = -EIO;
+ return 0;
+ }
+ if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE) {
+ *err = 2;
+ return 0;
+ }
+ if (SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_page) {
+ *err = -EIO;
+ return 0;
+ }
+ if (SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_id) {
+ *err = -EIO;
+ return 0;
+ }
+ hw_resource.free_tx_page = (int) SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int)txq_info.tx_use_page;
+ hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_id;
+ hw_resource.max_tx_frame[0] =(int)
+ SSV6XXX_ID_USB_AC_BK_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq0_size;
+ hw_resource.max_tx_frame[1] =(int)
+ SSV6XXX_ID_USB_AC_BE_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq1_size;
+ hw_resource.max_tx_frame[2] =(int)
+ SSV6XXX_ID_USB_AC_VI_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq2_size;
+ hw_resource.max_tx_frame[3] =(int)
+ SSV6XXX_ID_USB_AC_VO_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq3_size;
+ if (hci_used_id != -1) {
+ max_count = (int)SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+ }
+ if (hw_resource.max_tx_frame[3] < 0) {
+ *err = -EIO;
+ return 0;
+ }
+ if (hw_resource.max_tx_frame[2] < 0) {
+ *err = -EIO;
+ return 0;
+ }
+ if (hw_resource.max_tx_frame[1] < 0) {
+ *err = -EIO;
+ return 0;
+ }
+ if (hw_resource.max_tx_frame[0] < 0) {
+ *err = -EIO;
+ return 0;
+ }
+ }
+ {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if(ctrl_hci->irq_enable)
+ ctrl_hci->real_tx_irq_count++;
+#endif
+ tx_count = ssv6xxx_hci_xmit(ctrl_hci, hw_txq, max_count, &hw_resource);
+ }
+ if ( (ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+ && (skb_queue_len(&hw_txq->qhead) == 0)) {
+ ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no, SSV_SC(ctrl_hci));
+ }
+ return tx_count;
+}
+void ssv6xxx_hci_tx_work(struct work_struct *work)
+{
+ struct ssv6xxx_hci_ctrl *ctrl_hci;
+ ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, hci_tx_work);
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ ssv6xxx_hci_irq_register(ctrl_hci, SSV6XXX_INT_RESOURCE_LOW);
+#else
+ int txqid;
+ for(txqid = SSV_HW_TXQ_NUM - 1; txqid >= 0; txqid--) {
+ u32 bitno;
+ if (&ctrl_hci->hci_tx_work[txqid] != work)
+ continue;
+ bitno = ssv6xxx_hci_get_int_bitno(txqid);
+ ssv6xxx_hci_irq_register(1<<(bitno));
+ break;
+ }
+#endif
+}
+static int _do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ int ret = 0;
+ int rx_cnt, next_pkt_len;
+ size_t dlen;
+ u32 status = isr_status;
+ u32 rx_mode, frame_size;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ memset(&rx_io_end_time, 0, sizeof(struct timespec));
+ memset(&rx_io_start_time, 0, sizeof(struct timespec));
+ memset(&rx_proc_start_time, 0, sizeof(struct timespec));
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ rx_mode = hctl->shi->hci_rx_mode_cb((void *)(SSV_SC(hctl)));
+ frame_size = (rx_mode & RX_HW_AGG_MODE) ? MAX_HCI_RX_AGGR_SIZE : MAX_FRAME_SIZE_DMG;
+ frame_size += MAX_RX_PKT_RSVD;
+ next_pkt_len = 0;
+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32 ); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_io_start_time);
+#endif
+ dlen = next_pkt_len;
+ ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen, rx_mode);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_io_end_time);
+#endif
+ if (ret < 0 || dlen<=0) {
+ HCI_DBG_PRINT(hctl, "%s(): IF_RECV() retruns %d (dlen=%d)\n", __FUNCTION__, ret, (int)dlen);
+ if (ret != -84 || dlen>frame_size)
+ break;
+ }
+ rx_mpdu = hctl->rx_buf;
+ hctl->rx_buf = hctl->shi->skb_alloc((void *)(SSV_SC(hctl)), frame_size);
+ if (hctl->rx_buf == NULL) {
+ HCI_DBG_PRINT(hctl, "RX buffer allocation failure!\n");
+ hctl->rx_buf = rx_mpdu;
+ break;
+ }
+ hctl->rx_pkt++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (hctl->irq_enable) {
+ hctl->irq_rx_pkt_count ++;
+ }
+#endif
+ skb_put(rx_mpdu, dlen);
+ next_pkt_len = hctl->shi->hci_peek_next_pkt_len_cb(rx_mpdu, (void *)(SSV_SC(hctl)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ hctl->shi->hci_rx_cb(rx_mpdu, (void *)(SSV_SC(hctl)));
+#endif
+ if (next_pkt_len == 0)
+ HCI_IRQ_STATUS(hctl, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ hctl->isr_rx_io_count++;
+ rx_io_diff_time = timespec_sub(rx_io_end_time, rx_io_start_time);
+ hctl->isr_rx_io_time += timespec_to_ns(&rx_io_diff_time);
+ rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+ hctl->shi->hci_rx_cb(&rx_list, (void *)(SSV_SC(hctl)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+#endif
+ return ret;
+}
+static void ssv6xxx_hci_rx_work(struct work_struct *work)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ int rx_cnt, ret, next_pkt_len;
+ size_t dlen;
+ int status;
+ u32 rx_mode, frame_size;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+ struct ssv6xxx_hci_ctrl *ctrl_hci;
+ struct ssv6xxx_hci_info *shi;
+ ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, hci_rx_work);
+ shi = ctrl_hci->shi;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ memset(&rx_io_end_time, 0, sizeof(struct timespec));
+ memset(&rx_io_start_time, 0, sizeof(struct timespec));
+ memset(&rx_proc_start_time, 0, sizeof(struct timespec));
+#endif
+ ctrl_hci->rx_work_running = 1;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ rx_mode = shi->hci_rx_mode_cb((void *)(SSV_SC(ctrl_hci)));
+ frame_size = (rx_mode & RX_HW_AGG_MODE) ? MAX_HCI_RX_AGGR_SIZE : MAX_FRAME_SIZE_DMG;
+ frame_size += MAX_RX_PKT_RSVD;
+ next_pkt_len = 0;
+ status = SSV6XXX_INT_RX;
+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32 ); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_io_start_time);
+#endif
+ dlen = next_pkt_len;
+ ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen, rx_mode);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_io_end_time);
+#endif
+ if (ret < 0 || dlen<=0) {
+ HCI_DBG_PRINT(ctrl_hci, "%s(): IF_RECV() retruns %d (dlen=%d)\n", __FUNCTION__, ret, (int)dlen);
+ if (ret != -84 || dlen>frame_size)
+ break;
+ }
+ rx_mpdu = ctrl_hci->rx_buf;
+ ctrl_hci->rx_buf = shi->skb_alloc((void *)(SSV_SC(ctrl_hci)), frame_size);
+ if (ctrl_hci->rx_buf == NULL) {
+ HCI_DBG_PRINT(ctrl_hci, "RX buffer allocation failure!\n");
+ ctrl_hci->rx_buf = rx_mpdu;
+ break;
+ }
+ ctrl_hci->rx_pkt ++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if(ctrl_hci->irq_enable) {
+ ctrl_hci->irq_rx_pkt_count ++;
+ }
+#endif
+ skb_put(rx_mpdu, dlen);
+ next_pkt_len = shi->hci_peek_next_pkt_len_cb(rx_mpdu, (void *)(SSV_SC(ctrl_hci)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ shi->hci_rx_cb(rx_mpdu, (void *)(SSV_SC(ctrl_hci)));
+#endif
+ if (next_pkt_len == 0)
+ HCI_IRQ_STATUS(ctrl_hci, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ ctrl_hci->isr_rx_io_count++;
+ rx_io_diff_time = timespec_sub(rx_io_end_time, rx_io_start_time);
+ ctrl_hci->isr_rx_io_time += timespec_to_ns(&rx_io_diff_time);
+ rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ ctrl_hci->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+ shi->hci_rx_cb(&rx_list, (void *)(SSV_SC(ctrl_hci)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ ctrl_hci->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+#endif
+ ctrl_hci->rx_work_running = 0;
+}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void ssv6xxx_isr_mib_reset (struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ ctrl_hci->isr_mib_reset = 0;
+ ctrl_hci->isr_total_time = 0;
+ ctrl_hci->isr_rx_io_time = 0;
+ ctrl_hci->isr_tx_io_time = 0;
+ ctrl_hci->isr_rx_io_count = 0;
+ ctrl_hci->isr_tx_io_count = 0;
+ ctrl_hci->isr_rx_proc_time =0;
+}
+static int hw_txq_len_open(struct inode *inode, struct file *filp)
+{
+ filp->private_data = inode->i_private;
+ return 0;
+}
+static ssize_t hw_txq_len_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+{
+ ssize_t ret;
+ struct ssv6xxx_hci_ctrl *hctl = (struct ssv6xxx_hci_ctrl *)filp->private_data;
+ char *summary_buf = kzalloc(1024, GFP_KERNEL);
+ char *prn_ptr = summary_buf;
+ int prt_size;
+ int buf_size = 1024;
+ int i=0;
+ if (!summary_buf)
+ return -ENOMEM;
+ for (i=0; ihw_txq[i].qhead));
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ }
+ buf_size = 1024 - buf_size;
+ ret = simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
+ kfree(summary_buf);
+ return ret;
+}
+#if 0
+static ssize_t hw_txq_len_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos)
+{
+ return 0;
+}
+#endif
+struct file_operations hw_txq_len_fops = {
+ .owner = THIS_MODULE,
+ .open = hw_txq_len_open,
+ .read = hw_txq_len_read,
+};
+bool tu_ssv6xxx_hci_init_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci, struct dentry *dev_deugfs_dir)
+{
+ ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
+ if (ctrl_hci->debugfs_dir == NULL) {
+ HCI_DBG_PRINT(ctrl_hci, "Failed to create HCI debugfs directory.\n");
+ return false;
+ }
+ debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->txq_mask);
+ debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir, &ctrl_hci->isr_mib_enable);
+ debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir, &ctrl_hci->isr_mib_reset);
+ debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_total_time);
+ debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_tx_io_time);
+ debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_io_time);
+ debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_tx_io_count);
+ debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_io_count);
+ debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_proc_time);
+ debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir, ctrl_hci, &hw_txq_len_fops);
+ return true;
+}
+void ssv6xxx_hci_deinit_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+ if (ctrl_hci->debugfs_dir == NULL)
+ return;
+ ctrl_hci->debugfs_dir = NULL;
+}
+#endif
+static int _isr_do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+ int retval;
+ u32 before = jiffies;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (hctl->irq_enable)
+ hctl->rx_irq_count++;
+#endif
+ if (hctl->isr_summary_eable
+ && hctl->prev_rx_isr_jiffes) {
+ if (hctl->isr_rx_idle_time) {
+ hctl->isr_rx_idle_time += (jiffies - hctl->prev_rx_isr_jiffes);
+ hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >>1;
+ } else {
+ hctl->isr_rx_idle_time += (jiffies - hctl->prev_rx_isr_jiffes);
+ }
+ }
+ retval = _do_rx(hctl, isr_status);
+ if(hctl->isr_summary_eable) {
+ if(hctl->isr_rx_time) {
+ hctl->isr_rx_time += (jiffies-before);
+ hctl->isr_rx_time = hctl->isr_rx_time >>1;
+ } else {
+ hctl->isr_rx_time += (jiffies-before);
+ }
+ hctl->prev_rx_isr_jiffes = jiffies;
+ }
+ return retval;
+}
+static bool ssv6xxx_hci_is_frame_send(struct ssv6xxx_hci_ctrl *hci_ctrl)
+{
+ int q_num;
+ struct ssv_hw_txq *hw_txq;
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ hw_txq = &hci_ctrl->hw_txq[q_num];
+ if (!hw_txq->paused && !ssv6xxx_hci_is_txq_empty(hci_ctrl, q_num))
+ return true;
+ }
+ return false;
+}
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+static int _do_tx (struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+ int q_num;
+ int tx_count = 0;
+ unsigned long flags;
+ struct ssv_hw_txq *hw_txq;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+ int ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ memset(&tx_io_start_time, 0, sizeof(struct timespec));
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if ((!(status & SSV6XXX_INT_RX)) && hctl->irq_enable)
+ hctl->tx_irq_count++;
+#endif
+ if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
+ return 0;
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ u32 before = jiffies;
+ hw_txq = &hctl->hw_txq[q_num];
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&tx_io_start_time);
+#endif
+ ret = ssv6xxx_hci_tx_handler(hctl, hw_txq, 999);
+ if (ret < 0) {
+ HCI_DBG_PRINT(hctl, "TX Handler failed.\n");
+ break;
+ } else
+ tx_count += ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&tx_io_end_time);
+ tx_io_diff_time = timespec_sub(tx_io_end_time, tx_io_start_time);
+ hctl->isr_tx_io_time += timespec_to_ns(&tx_io_diff_time);
+ }
+#endif
+ if (hctl->isr_summary_eable) {
+ if (hctl->isr_tx_time) {
+ hctl->isr_tx_time += (jiffies-before);
+ hctl->isr_tx_time = hctl->isr_tx_time >>1;
+ } else {
+ hctl->isr_tx_time += (jiffies-before);
+ }
+ }
+ }
+ mutex_lock(&hctl->hci_mutex);
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ if (!ssv6xxx_hci_is_frame_send(hctl)) {
+ u32 reg_val;
+ hctl->int_mask &= ~SSV6XXX_INT_RESOURCE_LOW;
+ reg_val = ~hctl->int_mask;
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ HCI_IRQ_SET_MASK(hctl, reg_val);
+ } else {
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ }
+ mutex_unlock(&hctl->hci_mutex);
+ return ((ret < 0) ? ret : tx_count);
+}
+#else
+static int _do_tx (struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+ int q_num;
+ int tx_count = 0;
+ int ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if ((!(status & SSV6XXX_INT_RX)) && hctl->irq_enable)
+ htcl->tx_irq_count++;
+#endif
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ int bitno;
+ struct ssv_hw_txq *hw_txq;
+ unsigned long flags;
+ u32 before = jiffies;
+ hw_txq = &hctl->hw_txq[q_num];
+ bitno = ssv6xxx_hci_get_int_bitno(hw_txq->txq_no);
+ if ((status & BIT(bitno)) == 0)
+ continue;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (htcl->isr_mib_enable) {
+ getnstimeofday(&tx_io_start_time);
+ }
+#endif
+ ret = ssv6xxx_hci_tx_handler(hctl, hw_txq, 999);
+ if (ret < 0) {
+ HCI_DBG_PRINT(hci_ctrl, "TX handler failed.\n");
+ break;
+ } else
+ tx_count += ret;
+ mutex_lock(&hctl->hci_mutex);
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ if (skb_queue_len(&hw_txq->qhead) <= 0) {
+ u32 reg_val;
+ hctl->int_mask &= ~(1<int_mask;
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ HCI_IRQ_SET_MASK(hctl, reg_val);
+ } else {
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ }
+ mutex_unlock(&hctl->hci_mutex);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (htcl->isr_mib_enable) {
+ getnstimeofday(&tx_io_end_time);
+ tx_io_diff_time = timespec_sub(tx_io_end_time, tx_io_start_time);
+ htcl->isr_tx_io_time += timespec_to_ns(&tx_io_diff_time);
+ }
+#endif
+ if (htcl->isr_summary_eable) {
+ if (htcl->isr_tx_time) {
+ htcl->isr_tx_time += (jiffies - before);
+ htcl->isr_tx_time = htcl->isr_tx_time >>1;
+ } else {
+ htcl->isr_tx_time += (jiffies - before);
+ }
+ }
+ }
+ return ((ret < 0) ? ret : tx_count);
+}
+#endif
+static void ssv6xxx_hci_isr_reset(struct work_struct *work)
+{
+ struct ssv6xxx_hci_ctrl *ctrl_hci;
+ ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, isr_reset_work);
+ HCI_DBG_PRINT(ctrl_hci, "ISR Reset!!!");
+ ssv6xxx_hci_irq_disable(ctrl_hci);
+ ssv6xxx_hci_irq_enable(ctrl_hci);
+}
+irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
+{
+ struct ssv6xxx_hci_ctrl *hctl = args;
+ u32 status;
+ unsigned long flags;
+ int ret = IRQ_HANDLED;
+ bool dbg_isr_miss = true;
+ bool isr_reset = false;
+ bool first_time_check = true;
+ if (hctl->isr_summary_eable
+ && hctl->prev_isr_jiffes) {
+ if(hctl->isr_idle_time) {
+ hctl->isr_idle_time += (jiffies - hctl->prev_isr_jiffes);
+ hctl->isr_idle_time = hctl->isr_idle_time >>1;
+ } else {
+ hctl->isr_idle_time += (jiffies - hctl->prev_isr_jiffes);
+ }
+ }
+ BUG_ON(!args);
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if(hctl->irq_enable)
+ hctl->irq_count++;
+#endif
+ do {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec start_time, end_time, diff_time;
+ memset(&start_time, 0, sizeof(struct timespec));
+ if (hctl->isr_mib_reset)
+ ssv6xxx_isr_mib_reset(hctl);
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&start_time);
+#endif
+ mutex_lock(&hctl->hci_mutex);
+ if (hctl->int_status) {
+ u32 regval;
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ hctl->int_mask |= hctl->int_status;
+ hctl->int_status = 0;
+ regval = ~hctl->int_mask;
+ smp_mb();
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ HCI_IRQ_SET_MASK(hctl, regval);
+ }
+ ret = HCI_IRQ_STATUS(hctl, &status);
+ if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
+ if (first_time_check) {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (hctl->irq_enable)
+ hctl->invalid_irq_count++;
+#endif
+ ret = IRQ_NONE;
+ }
+ mutex_unlock(&hctl->hci_mutex);
+ break;
+ }
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ status &= hctl->int_mask;
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ mutex_unlock(&hctl->hci_mutex);
+ hctl->isr_running = 1;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ if (status & SSV6XXX_INT_RESOURCE_LOW) {
+#else
+ if (status & (SSV6XXX_INT_TX|SSV6XXX_INT_LOW_EDCA_0|SSV6XXX_INT_LOW_EDCA_1|SSV6XXX_INT_LOW_EDCA_2|SSV6XXX_INT_LOW_EDCA_3)) {
+#endif
+ ret = _do_tx(hctl, status);
+ if (ret > 0) {
+ dbg_isr_miss = false;
+ } else if (ret < 0) {
+ isr_reset = true;
+ hctl->isr_running = 0;
+ break;
+ }
+ }
+ if (status & SSV6XXX_INT_RX) {
+ ret = _isr_do_rx(hctl, status);
+ if (ret < 0) {
+ isr_reset = true;
+ hctl->isr_running = 0;
+ HCI_DBG_PRINT(hctl, "do_rx failed\n");
+ break;
+ }
+ dbg_isr_miss = false;
+ } else {
+ hctl->isr_running = 0;
+ break;
+ }
+ hctl->isr_running = 0;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&end_time);
+ diff_time = timespec_sub(end_time, start_time);
+ hctl->isr_total_time += timespec_to_ns(&diff_time);
+ }
+#endif
+ first_time_check = false;
+ }
+ while (1);
+ if (hctl->isr_summary_eable ) {
+ if(dbg_isr_miss)
+ hctl->isr_miss_cnt++;
+ hctl->prev_isr_jiffes = jiffies;
+ }
+ if (isr_reset == true)
+ queue_work(hctl->hci_work_queue, &hctl->isr_reset_work);
+ return ret;
+}
+static int ssv6xxx_hci_tx_task (void *data)
+{
+#define MAX_HCI_TX_TASK_SEND_FAIL 3
+ struct ssv6xxx_hci_ctrl *hctl = (struct ssv6xxx_hci_ctrl *)data;
+ unsigned long wait_period = msecs_to_jiffies(200);
+ int err = 0, err_cnt = 0;
+ txrxboost_init();
+ printk("SSV6XXX HCI TX Task started.\n");
+ while (!kthread_should_stop()) {
+ wait_event_interruptible_timeout(hctl->tx_wait_q,
+ ( kthread_should_stop()
+ || ssv6xxx_hci_is_frame_send(hctl)),
+ wait_period);
+ if (kthread_should_stop()) {
+ hctl->hci_tx_task = NULL;
+ HCI_DBG_PRINT(hctl, "Quit HCI TX task loop...\n");
+ break;
+ }
+ txrxboost_change((u32)atomic_read(&SSV_SC(hctl)->ampdu_tx_frame),
+ SSV_SC(hctl)->sh->cfg.txrxboost_low_threshold,
+ SSV_SC(hctl)->sh->cfg.txrxboost_high_threshold,
+ SSV_SC(hctl)->sh->cfg.txrxboost_prio);
+ if ((hctl->hci_flags & SSV6XXX_HCI_OP_INVALID) ||
+ (hctl->hci_flags & SSV6XXX_HCI_OP_IFERR) ||
+ (err_cnt > MAX_HCI_TX_TASK_SEND_FAIL)) {
+ ssv6xxx_hci_txq_flush(hctl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+ //ssv6xxx_hci_txq_flush(hctl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+ err_cnt = 0;
+ } else {
+ if (ssv6xxx_hci_is_frame_send(hctl)) {
+ err = 0;
+ _do_force_tx(hctl, &err);
+ if ((err < 0) && (err != -1)) {
+ err_cnt++;
+ } else if (err == -1) {
+ hctl->hci_flags |= SSV6XXX_HCI_OP_IFERR;
+ }
+ }
+ }
+ }
+ return 0;
+}
+static struct ssv6xxx_hci_ops hci_ops = {
+ .hci_start = ssv6xxx_hci_start,
+ .hci_stop = ssv6xxx_hci_stop,
+ .hci_write_hw_config = ssv6xxx_hci_write_hw_config,
+ .hci_read_word = ssv6xxx_hci_read_word,
+ .hci_write_word = ssv6xxx_hci_write_word,
+ .hci_safe_read_word = ssv6xxx_hci_safe_read_word,
+ .hci_safe_write_word = ssv6xxx_hci_safe_write_word,
+ .hci_burst_read_word = ssv6xxx_hci_burst_read_word,
+ .hci_burst_write_word = ssv6xxx_hci_burst_write_word,
+ .hci_burst_safe_read_word = ssv6xxx_hci_burst_safe_read_word,
+ .hci_burst_safe_write_word = ssv6xxx_hci_burst_safe_write_word,
+ .hci_tx = ssv6xxx_hci_enqueue,
+ .hci_tx_pause = ssv6xxx_hci_txq_pause,
+ .hci_tx_resume = ssv6xxx_hci_txq_resume,
+ .hci_txq_flush = ssv6xxx_hci_txq_flush,
+ .hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
+ .hci_txq_empty = ssv6xxx_hci_is_txq_empty,
+ .hci_load_fw = ssv6xxx_hci_load_fw,
+ .hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
+ .hci_send_cmd = ssv6xxx_hci_send_cmd,
+ .hci_write_sram = ssv6xxx_hci_write_sram,
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ .hci_init_debugfs = tu_ssv6xxx_hci_init_debugfs,
+ .hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
+#endif
+ .hci_interface_reset = ssv6xxx_hci_interface_reset,
+ .hci_sysplf_reset = ssv6xxx_hci_sysplf_reset,
+};
+int tu_ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *shi)
+{
+ u32 regval;
+ struct ssv6xxx_hci_ctrl *hci_ctrl;
+ printk("%s(): \n", __FUNCTION__);
+ if (shi->hci_ctrl == NULL)
+ return -1;
+ hci_ctrl = shi->hci_ctrl;
+ hci_ctrl->hci_flags |= SSV6XXX_HCI_OP_INVALID;
+ regval = 1;
+ ssv6xxx_hci_txq_flush(hci_ctrl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+ ssv6xxx_hci_irq_disable(hci_ctrl);
+ flush_workqueue(hci_ctrl->hci_work_queue);
+ destroy_workqueue(hci_ctrl->hci_work_queue);
+ if (hci_ctrl->hci_tx_task != NULL) {
+ printk("Stopping HCI TX task...\n");
+ kthread_stop(hci_ctrl->hci_tx_task);
+ hci_ctrl->hci_tx_task = NULL;
+ printk("Stopped HCI TX task.\n");
+ }
+ if (hci_ctrl->rx_buf != NULL) {
+ dev_kfree_skb_any(hci_ctrl->rx_buf);
+ }
+ shi->hci_ctrl = NULL;
+ kfree(hci_ctrl);
+ return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_hci_deregister);
+int tu_ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
+{
+ int i, capability;
+ struct ssv6xxx_hci_ctrl *hci_ctrl;
+ if (shi == NULL ) {
+ printk(KERN_ERR "NULL sh when register HCI.\n");
+ return -1;
+ }
+ hci_ctrl = kzalloc(sizeof(*hci_ctrl), GFP_KERNEL);
+ if (hci_ctrl == NULL)
+ return -ENOMEM;
+ memset((void *)hci_ctrl, 0, sizeof(*hci_ctrl));
+ shi->hci_ctrl = hci_ctrl;
+ shi->hci_ops = &hci_ops;
+ hci_ctrl->shi = shi;
+ hci_ctrl->rx_buf = shi->skb_alloc((void *)(SSV_SC(hci_ctrl)), MAX_HCI_RX_AGGR_SIZE);
+ if (hci_ctrl->rx_buf == NULL) {
+ kfree(hci_ctrl);
+ return -ENOMEM;
+ }
+ hci_ctrl->txq_mask = 0;
+ mutex_init(&hci_ctrl->txq_mask_lock);
+ mutex_init(&hci_ctrl->hci_mutex);
+ spin_lock_init(&hci_ctrl->int_lock);
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ hci_ctrl->irq_enable = false;
+ hci_ctrl->irq_count = 0;
+ hci_ctrl->invalid_irq_count = 0;
+ hci_ctrl->tx_irq_count = 0;
+ hci_ctrl->real_tx_irq_count = 0;
+ hci_ctrl->rx_irq_count = 0;
+ hci_ctrl->irq_rx_pkt_count = 0;
+ hci_ctrl->irq_tx_pkt_count = 0;
+#endif
+ for (i=0; i < SSV_HW_TXQ_NUM; i++) {
+ memset(&hci_ctrl->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
+ skb_queue_head_init(&hci_ctrl->hw_txq[i].qhead);
+ hci_ctrl->hw_txq[i].txq_no = (u32)i;
+ hci_ctrl->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
+ hci_ctrl->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
+ }
+ hci_ctrl->hci_work_queue = create_singlethread_workqueue("ssv6xxx_hci_wq");
+ INIT_WORK(&hci_ctrl->isr_reset_work, ssv6xxx_hci_isr_reset);
+ INIT_WORK(&hci_ctrl->hci_rx_work, ssv6xxx_hci_rx_work);
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ INIT_WORK(&hci_ctrl->hci_tx_work, ssv6xxx_hci_tx_work);
+#else
+ for(i=0; ihci_tx_work[i], ssv6xxx_hci_tx_work);
+#endif
+ capability = (HCI_HWIF_PROPERTY(hci_ctrl) & SSV_HWIF_CAPABILITY_MASK);
+ switch (capability) {
+ case SSV_HWIF_CAPABILITY_INTERRUPT:
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+ hci_ctrl->int_mask = SSV6XXX_INT_RX|SSV6XXX_INT_RESOURCE_LOW;
+#else
+ hci_ctrl->int_mask = SSV6XXX_INT_RX|SSV6XXX_INT_TX|SSV6XXX_INT_LOW_EDCA_0|
+ SSV6XXX_INT_LOW_EDCA_1|SSV6XXX_INT_LOW_EDCA_2|SSV6XXX_INT_LOW_EDCA_3;
+#endif
+ hci_ctrl->isr_disable = false;
+ hci_ctrl->int_status= 0;
+ HCI_IRQ_SET_MASK(hci_ctrl, 0xFFFFFFFF);
+ ssv6xxx_hci_irq_disable(hci_ctrl);
+ HCI_IRQ_REQUEST(hci_ctrl, ssv6xxx_hci_isr);
+ break;
+ case SSV_HWIF_CAPABILITY_POLLING:
+ hci_ctrl->isr_disable = true;
+ init_waitqueue_head(&hci_ctrl->tx_wait_q);
+ hci_ctrl->hci_tx_task = kthread_run(ssv6xxx_hci_tx_task, hci_ctrl, "ssv6xxx_hci_tx_task");
+ HCI_RX_TASK(hci_ctrl, hci_ctrl->shi->hci_rx_cb, hci_ctrl->shi->hci_is_rx_q_full, (void *)(SSV_SC(hci_ctrl)), &hci_ctrl->rx_pkt);
+ break;
+ default:
+ printk("Detect unknown hardware capability\n");
+ return -1;
+ }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ hci_ctrl->debugfs_dir = NULL;
+ hci_ctrl->isr_mib_enable = false;
+ hci_ctrl->isr_mib_reset = 0;
+ hci_ctrl->isr_total_time = 0;
+ hci_ctrl->isr_rx_io_time = 0;
+ hci_ctrl->isr_tx_io_time = 0;
+ hci_ctrl->isr_rx_io_count = 0;
+ hci_ctrl->isr_tx_io_count = 0;
+ hci_ctrl->isr_rx_proc_time =0;
+#endif
+ return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_hci_register);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_hci_init(void)
+#else
+int __init tu_ssv6xxx_hci_init(void)
+#endif
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+ return 0;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssv6xxx_hci_exit(void)
+#else
+void __exit tu_ssv6xxx_hci_exit(void)
+#endif
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssv6xxx_hci_init);
+EXPORT_SYMBOL(tu_ssv6xxx_hci_exit);
+#else
+module_init(tu_ssv6xxx_hci_init);
+module_exit(tu_ssv6xxx_hci_exit);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h
new file mode 100644
index 000000000..9a2617a1b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV_HCI_H_
+#define _SSV_HCI_H_
+#define SSV_SC(_ctrl_hci) (_ctrl_hci->shi->sc)
+#define TX_PAGE_NOT_LIMITED 255
+#define SSV_HW_TXQ_NUM 5
+#define SSV_HW_TXQ_MAX_SIZE 64
+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
+#define SSV6XXX_ID_TX_THRESHOLD(_hctl) ((_hctl)->tx_info.tx_id_threshold)
+#define SSV6XXX_PAGE_TX_THRESHOLD(_hctl) ((_hctl)->tx_info.tx_page_threshold)
+#define SSV6XXX_TX_LOWTHRESHOLD_ID_TRIGGER(_hctl) ((_hctl)->tx_info.tx_lowthreshold_id_trigger)
+#define SSV6XXX_TX_LOWTHRESHOLD_PAGE_TRIGGER(_hctl) ((_hctl)->tx_info.tx_lowthreshold_page_trigger)
+#define SSV6XXX_ID_AC_BK_OUT_QUEUE(_hctl) ((_hctl)->tx_info.bk_txq_size)
+#define SSV6XXX_ID_AC_BE_OUT_QUEUE(_hctl) ((_hctl)->tx_info.be_txq_size)
+#define SSV6XXX_ID_AC_VI_OUT_QUEUE(_hctl) ((_hctl)->tx_info.vi_txq_size)
+#define SSV6XXX_ID_AC_VO_OUT_QUEUE(_hctl) ((_hctl)->tx_info.vo_txq_size)
+#define SSV6XXX_ID_MANAGER_QUEUE(_hctl) ((_hctl)->tx_info.manage_txq_size)
+#define SSV6XXX_ID_USB_AC_BK_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.bk_txq_size)
+#define SSV6XXX_ID_USB_AC_BE_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.be_txq_size)
+#define SSV6XXX_ID_USB_AC_VI_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.vi_txq_size)
+#define SSV6XXX_ID_USB_AC_VO_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.vo_txq_size)
+#define SSV6XXX_ID_USB_MANAGER_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.manage_txq_size)
+#define SSV6XXX_ID_HCI_INPUT_QUEUE 8
+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
+#define HCI_DBG_PRINT(_hci_ctrl,fmt,...) \
+ do { \
+ (_hci_ctrl)->shi->dbgprint((_hci_ctrl)->shi->sc, LOG_HCI, fmt, ##__VA_ARGS__); \
+ } while (0)
+struct ssv_hw_txq {
+ u32 txq_no;
+ struct sk_buff_head qhead;
+ int max_qsize;
+ int resum_thres;
+ bool paused;
+ u32 tx_pkt;
+ u32 tx_flags;
+};
+struct ssv6xxx_hci_ctrl;
+struct ssv6xxx_hci_ops {
+ int (*hci_start)(struct ssv6xxx_hci_ctrl *hctrl);
+ int (*hci_stop)(struct ssv6xxx_hci_ctrl *hctrl);
+ void (*hci_write_hw_config)(struct ssv6xxx_hci_ctrl *hctrl, int val);
+ int (*hci_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);
+ int (*hci_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);
+ int (*hci_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);
+ int (*hci_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);
+ int (*hci_burst_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+ int (*hci_burst_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+ int (*hci_burst_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+ int (*hci_burst_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+ int (*hci_load_fw)(struct ssv6xxx_hci_ctrl *hctrl, u8 *firmware_name, u8 openfile);
+ int (*hci_tx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *, int, u32);
+#if 0
+ int (*hci_rx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);
+#endif
+ int (*hci_tx_pause)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+ int (*hci_tx_resume)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+ int (*hci_txq_flush)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+ int (*hci_txq_flush_by_sta)(struct ssv6xxx_hci_ctrl *hctrl, int aid);
+ bool (*hci_txq_empty)(struct ssv6xxx_hci_ctrl *hctrl, int txqid);
+ int (*hci_pmu_wakeup)(struct ssv6xxx_hci_ctrl *hctrl);
+ int (*hci_send_cmd)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ bool (*hci_init_debugfs)(struct ssv6xxx_hci_ctrl *hctrl, struct dentry *dev_deugfs_dir);
+ void (*hci_deinit_debugfs)(struct ssv6xxx_hci_ctrl *hctrl);
+#endif
+ int (*hci_write_sram)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8* data, u32 size);
+ int (*hci_interface_reset)(struct ssv6xxx_hci_ctrl *hctrl);
+ int (*hci_sysplf_reset)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value);
+};
+struct ssv6xxx_hci_info {
+ struct device *dev;
+ struct ssv6xxx_hwif_ops *if_ops;
+ struct ssv6xxx_hci_ops *hci_ops;
+ struct ssv6xxx_hci_ctrl *hci_ctrl;
+ struct ssv_softc *sc;
+ struct ssv_hw *sh;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ int (*hci_rx_cb)(struct sk_buff_head *, void *);
+#else
+ int (*hci_rx_cb)(struct sk_buff *, void *);
+#endif
+ int (*hci_is_rx_q_full)(void *);
+ void (*hci_pre_tx_cb)(struct sk_buff *, void *);
+ void (*hci_post_tx_cb)(struct sk_buff_head *, void *);
+ int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
+ void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
+ void (*hci_skb_update_cb)(struct sk_buff *, void *);
+ void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
+ int (*hci_rx_mode_cb)(void *);
+ int (*hci_peek_next_pkt_len_cb)(struct sk_buff *, void *);
+ void (*dbgprint)(void *, u32 log_id, const char *fmt,...);
+ struct sk_buff *(*skb_alloc) (void *app_param, s32 len);
+ void (*skb_free) (void *app_param, struct sk_buff *skb);
+ void (*write_hw_config_cb)(void *param, u32 addr, u32 value);
+};
+int tu_ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *);
+int tu_ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_hci_init(void);
+void tu_ssv6xxx_hci_exit(void);
+#endif
+#ifdef SSV_SUPPORT_HAL
+#define SSV_READRG_HCI_INQ_INFO(_hci_ctrl,_used_id,_tx_use_page) \
+ HAL_READRG_HCI_INQ_INFO((_hci_ctrl)->shi->sh, _used_id, _tx_use_page)
+#define SSV_LOAD_FW_ENABLE_MCU(_hci_ctrl) HAL_LOAD_FW_ENABLE_MCU((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_DISABLE_MCU(_hci_ctrl) HAL_LOAD_FW_DISABLE_MCU((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_SET_STATUS(_hci_ctrl,_status) HAL_LOAD_FW_SET_STATUS((_hci_ctrl)->shi->sh, (_status))
+#define SSV_LOAD_FW_GET_STATUS(_hci_ctrl,_status) HAL_LOAD_FW_GET_STATUS((_hci_ctrl)->shi->sh, (_status))
+#define SSV_RESET_CPU(_hci_ctrl) HAL_RESET_CPU((_hci_ctrl)->shi->sh)
+#define SSV_SET_SRAM_MODE(_hci_ctrl,_mode) HAL_SET_SRAM_MODE((_hci_ctrl)->shi->sh, _mode)
+#define SSV_LOAD_FW_PRE_CONFIG_DEVICE(_hci_ctrl) HAL_LOAD_FW_PRE_CONFIG_DEVICE((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_POST_CONFIG_DEVICE(_hci_ctrl) HAL_LOAD_FW_POST_CONFIG_DEVICE((_hci_ctrl)->shi->sh)
+#else
+void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id);
+void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);
+int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);
+int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status);
+int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status);
+void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);
+void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);
+#define SSV_READRG_HCI_INQ_INFO(_hci_ctrl,_used_id,_tx_use_page) \
+ ssv6xxx_hci_hci_inq_info(_hci_ctrl, _used_id)
+#define SSV_LOAD_FW_ENABLE_MCU(_hci_ctrl) ssv6xxx_hci_load_fw_enable_mcu((_hci_ctrl))
+#define SSV_LOAD_FW_DISABLE_MCU(_hci_ctrl) ssv6xxx_hci_load_fw_disable_mcu((_hci_ctrl))
+#define SSV_LOAD_FW_SET_STATUS(_hci_ctrl,_status) ssv6xxx_hci_load_fw_set_status((_hci_ctrl), (_status))
+#define SSV_LOAD_FW_GET_STATUS(_hci_ctrl,_status) ssv6xxx_hci_load_fw_get_status((_hci_ctrl), (_status))
+#define SSV_RESET_CPU(_hci_ctrl) ssv6xxx_hci_reset_cpu((_hci_ctrl))
+#define SSV_SET_SRAM_MODE(_hci_ctrl,_mode)
+#define SSV_LOAD_FW_PRE_CONFIG_DEVICE(_hci_ctrl) ssv6xxx_hci_load_fw_pre_config_device(_hci_ctrl)
+#define SSV_LOAD_FW_POST_CONFIG_DEVICE(_hci_ctrl) ssv6xxx_hci_load_fw_post_config_device(_hci_ctrl)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile b/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile
new file mode 100755
index 000000000..e8e017859
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile
@@ -0,0 +1,19 @@
+ifeq ($(KBUILD_TOP),)
+ ifneq ($(KBUILD_EXTMOD),)
+ KBUILD_DIR := $(KBUILD_EXTMOD)
+ else
+ KBUILD_DIR := $(PWD)
+ endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci/Module.symvers
+
+
+KMODULE_NAME=hci_wrapper
+KERN_SRCS := ssv_huw.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c
new file mode 100644
index 000000000..e1a254d22
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c
@@ -0,0 +1,461 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ssv_huw.h"
+#define SSV6200_ID_NUMBER (128)
+#define BLOCKSIZE 0x40
+#define RXBUFLENGTH 1024*3
+#define RXBUFSIZE 512
+#define CHECK_RET(_fun) \
+ do { \
+ if (0 != _fun) \
+ printk("File = %s\nLine = %d\nFunc=%s\nDate=%s\nTime=%s\n", __FILE__, __LINE__, __FUNCTION__, __DATE__, __TIME__); \
+ } while (0)
+#define SMAC_SRAM_WRITE(_s,_r,_v,_sz) \
+ (_s)->hci.hci_ops->hci_write_sram(_r, _v, _sz)
+#define SMAC_REG_WRITE(_s,_r,_v) \
+ (_s)->hci.hci_ops->hci_write_word(_r, _v)
+#define SMAC_REG_READ(_s,_r,_v) \
+ (_s)->hci.hci_ops->hci_read_word(_r, _v)
+#define HCI_START(_sh) \
+ (_sh)->hci.hci_ops->hci_start()
+#define HCI_STOP(_sh) \
+ (_sh)->hci.hci_ops->hci_stop()
+#define HCI_SEND(_sh,_sk,_q) \
+ (_sh)->hci.hci_ops->hci_tx(_sk, _q, HCI_FLAGS_NO_FLOWCTRL)
+#define HCI_PAUSE(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_tx_pause(_mk)
+#define HCI_RESUME(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_tx_resume(_mk)
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_txq_flush(_mk)
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+ (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+ (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
+#define HCI_WAKEUP_PMU(_sh) \
+ (_sh)->hci.hci_ops->hci_pmu_wakeup()
+#define HCI_SEND_CMD(_sh,_sk) \
+ (_sh)->hci.hci_ops->hci_send_cmd(_sk)
+struct ssv_huw_dev {
+ struct device *dev;
+ struct ssv6xxx_platform_data *priv;
+ struct ssv6xxx_hci_info hci;
+ char chip_id[24];
+ u64 chip_tag;
+ u8 funcFocus;
+ wait_queue_head_t read_wq;
+ spinlock_t rxlock;
+ void *bufaddr;
+ struct sk_buff_head rx_skb_q;
+};
+struct ssv_rxbuf {
+ struct list_head list;
+ u32 rxsize;
+ u8 rxdata[RXBUFLENGTH];
+};
+struct ssv_huw_dev g_huw_dev;
+static unsigned int ssv_sdiobridge_ioctl_major = 0;
+static unsigned int num_of_dev = 1;
+static struct cdev ssv_sdiobridge_ioctl_cdev;
+static struct class *fc;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv_huw_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+int ssv_huw_rx(struct sk_buff *rx_skb, void *args)
+#endif
+{
+ struct ssv_huw_dev *phuw_dev = (struct ssv_huw_dev *)args;
+ unsigned long flags;
+ spin_lock_irqsave(&phuw_dev->rxlock, flags);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ while (skb_queue_len(rx_skb_q))
+ __skb_queue_tail(&phuw_dev->rx_skb_q, __skb_dequeue(rx_skb_q));
+#else
+ __skb_queue_tail(&phuw_dev->rx_skb_q, rx_skb);
+#endif
+ spin_unlock_irqrestore(&phuw_dev->rxlock, flags);
+ wake_up_interruptible(&phuw_dev->read_wq);
+ return 0;
+}
+void ssv_huw_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+ if (!skb)
+ return;
+ dev_kfree_skb_any(skb);
+}
+unsigned int skb_queue_len_bhsafe(struct sk_buff_head *head, spinlock_t *plock)
+{
+ unsigned int len = 0;
+ spin_lock_bh(plock);
+ len = skb_queue_len(head);
+ spin_unlock_bh(plock);
+ return len;
+}
+static long ssv_huw_ioctl_readReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->in_data_len < 4 || pcmd_data->out_data_len < 4) {
+ retval = -1;
+ } else {
+ u32 tmpdata;
+ u32 regval;
+ int ret = 0;
+#ifdef CONFIG_COMPAT
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+ } else
+#endif
+ {
+ CHECK_RET(copy_from_user(&tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+ }
+ ret = SMAC_REG_READ(phuw_dev, tmpdata, ®val);
+ if ( !ret ) {
+#ifdef CONFIG_COMPAT
+ if ( isCompat ) {
+ CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),®val,sizeof(regval)));
+ } else
+#endif
+ {
+ CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,®val,sizeof(regval)));
+ }
+ } else {
+ dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static long ssv_huw_ioctl_writeReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ if ( pcmd_data->in_data_len < 8) {
+ retval = -1;
+ } else {
+ u32 tmpdata[2];
+ int ret = 0;
+#ifdef CONFIG_COMPAT
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+ } else
+#endif
+ {
+ CHECK_RET(copy_from_user(&tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+ }
+ SMAC_REG_WRITE(phuw_dev, tmpdata[0], tmpdata[1]);
+ if ( ret ) {
+ dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ }
+ return retval;
+}
+static long ssv_huw_ioctl_writeSram(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+ long retval =0;
+ unsigned char *ptr = NULL;
+ unsigned int addr;
+ if (( pcmd_data->in_data_len != 4) || ( pcmd_data->out_data_len <= 0)) {
+ retval = -1;
+ } else {
+ int ret = 0;
+ ptr = kzalloc(pcmd_data->out_data_len, GFP_KERNEL);
+ if(ptr == NULL)
+ return -ENOMEM;
+#ifdef CONFIG_COMPAT
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&addr, (int __user *)compat_ptr((unsigned long)pucmd_data->in_data), sizeof(addr)));
+ CHECK_RET(copy_from_user(ptr, (int __user *)compat_ptr((unsigned long)pucmd_data->out_data), pcmd_data->out_data_len));
+ } else
+#endif
+ {
+ CHECK_RET(copy_from_user(&addr, (int __user *)pucmd_data->in_data, sizeof(addr)));
+ CHECK_RET(copy_from_user(ptr, (int __user *)pucmd_data->out_data, pcmd_data->out_data_len));
+ }
+ SMAC_SRAM_WRITE(phuw_dev, addr, ptr, pcmd_data->out_data_len);
+ if ( ret ) {
+ dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+ retval = -1;
+ }
+ kfree(ptr);
+ }
+ return retval;
+}
+static long ssv_huw_ioctl_process(struct ssv_huw_dev *glue, unsigned int cmd, struct ssv_huw_cmd *pucmd_data, bool isCompat)
+{
+ struct ssv_huw_cmd cmd_data;
+ long retval=0;
+ if ( isCompat ) {
+ CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+ } else {
+ CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+ }
+ switch (cmd) {
+ case IOCTL_SSVSDIO_READ_REG:
+ retval = ssv_huw_ioctl_readReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_WRITE_REG:
+ retval = ssv_huw_ioctl_writeReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_WRITE_SRAM:
+ retval = ssv_huw_ioctl_writeSram(glue,cmd,&cmd_data,pucmd_data,isCompat);
+ break;
+ case IOCTL_SSVSDIO_START:
+ retval = HCI_START(glue);
+ break;
+ case IOCTL_SSVSDIO_STOP:
+ retval = HCI_STOP(glue);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return retval;
+}
+#ifdef CONFIG_COMPAT
+static long ssv_huw_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ long retval=0;
+ struct ssv_huw_cmd *pucmd_data;
+ pucmd_data = (struct ssv_huw_cmd *)arg;
+ retval = ssv_huw_ioctl_process(&g_huw_dev, cmd, pucmd_data, true);
+ return retval;
+}
+#endif
+static long ssv_huw_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ long retval=0;
+ struct ssv_huw_cmd *pucmd_data;
+ pucmd_data = (struct ssv_huw_cmd *)arg;
+ retval = ssv_huw_ioctl_process( &g_huw_dev,cmd,pucmd_data,false);
+ return retval;
+}
+static int ssv_huw_open(struct inode *inode, struct file *fp)
+{
+ fp->private_data = &g_huw_dev;
+ return 0;
+}
+static int ssv_huw_release(struct inode *inode, struct file *fp)
+{
+ struct sk_buff *skb = NULL;
+ while((skb = skb_dequeue(&(g_huw_dev.rx_skb_q))) != NULL) {
+ dev_kfree_skb_any(skb);
+ skb = NULL;
+ }
+ return 0;
+}
+static ssize_t ssv_huw_read(struct file *fp, char __user * buf, size_t length, loff_t * offset)
+{
+ int ret = 0, copy_length = 0;
+ struct sk_buff *skb = NULL;
+ if (skb_queue_len_bhsafe(&(g_huw_dev.rx_skb_q), &(g_huw_dev.rxlock)) == 0) {
+ ret = wait_event_interruptible((g_huw_dev.read_wq), (skb_queue_len_bhsafe(&(g_huw_dev.rx_skb_q), &(g_huw_dev.rxlock)) != 0));
+ if (ret != 0)
+ return -1;
+ }
+ spin_lock_bh(&(g_huw_dev.rxlock));
+ if (skb_queue_len(&(g_huw_dev.rx_skb_q)) > 0)
+ skb = skb_dequeue(&(g_huw_dev.rx_skb_q));
+ spin_unlock_bh(&(g_huw_dev.rxlock));
+ if (skb != NULL) {
+ copy_length = min(skb->len,(u32)length);
+ CHECK_RET(copy_to_user((int __user *)buf, skb->data, copy_length));
+ dev_kfree_skb_any(skb);
+ }
+ return copy_length;
+}
+static ssize_t ssv_huw_write(struct file *fp, const char __user * buf, size_t length, loff_t * offset)
+{
+ struct sk_buff *skb;
+ unsigned int len = (unsigned int)length;
+ len = (len & 0x1f)?(((len>>5) + 1)<<5):len;
+ skb = __dev_alloc_skb(len, GFP_KERNEL);
+ if (skb == NULL) {
+ dev_err(g_huw_dev.dev,"%s: error : alloc buf error size:%d",__FUNCTION__,(u32)len);
+ return -ENOMEM;
+ }
+ CHECK_RET(copy_from_user(skb->data, (int __user *)buf, length));
+ skb_put(skb, length);
+ HCI_SEND(&g_huw_dev, skb, 1);
+ return length;
+}
+void ssv_huw_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+ struct sk_buff *skb = NULL;
+ while ((skb=skb_dequeue(skb_head))) {
+ dev_kfree_skb_any(skb);
+ skb = NULL;
+ }
+}
+int ssv_huw_read_hci_info(struct ssv_huw_dev *phuw_dev)
+{
+ struct ssv6xxx_hci_info *pinfo = &(phuw_dev->hci);
+ pinfo->hci_ops = NULL;
+ pinfo->dev = phuw_dev->dev;
+ pinfo->hci_rx_cb = ssv_huw_rx;
+ pinfo->rx_cb_args = (void *)phuw_dev;
+ pinfo->hci_post_tx_cb= ssv_huw_tx_cb;
+ pinfo->post_tx_cb_args = NULL;
+ pinfo->hci_skb_update_cb = NULL;
+ pinfo->skb_update_args = NULL;
+ pinfo->hci_tx_flow_ctrl_cb = NULL;
+ pinfo->tx_fctrl_cb_args = NULL;
+ pinfo->hci_tx_q_empty_cb = NULL;
+ pinfo->tx_q_empty_args = NULL;
+ pinfo->hci_tx_buf_free_cb = ssv_huw_txbuf_free_skb;
+ pinfo->tx_buf_free_args = NULL;
+ pinfo->if_ops = phuw_dev->priv->ops;
+ return 0;
+}
+struct file_operations s_huw_ops = {
+ .read = ssv_huw_read,
+ .write = ssv_huw_write,
+ .unlocked_ioctl = ssv_huw_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = ssv_huw_compat_ioctl,
+#endif
+ .open = ssv_huw_open,
+ .release = ssv_huw_release,
+};
+static int ssv_huw_init_buf(struct ssv_huw_dev *hdev)
+{
+ init_waitqueue_head(&hdev->read_wq);
+ spin_lock_init(&hdev->rxlock);
+ skb_queue_head_init(&(hdev->rx_skb_q));
+ return 0;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+static char *ssv_huw_devnode(struct device *dev, umode_t *mode)
+#else
+static char *ssv_huw_devnode(struct device *dev, mode_t *mode)
+#endif
+{
+ if (!mode)
+ return NULL;
+ *mode = 0644;
+ return NULL;
+}
+int ssv_huw_probe(struct platform_device *pdev)
+{
+ dev_t dev;
+ int alloc_ret = 0;
+ int cdev_ret = 0;
+ if (!pdev->dev.platform_data) {
+ dev_err(&pdev->dev, "no platform data specified!\n");
+ return -EINVAL;
+ }
+ ssv_huw_init_buf(&g_huw_dev);
+ g_huw_dev.priv = (pdev->dev.platform_data);
+ g_huw_dev.dev = &(pdev->dev);
+ ssv_huw_read_hci_info(&g_huw_dev);
+ tu_ssv6xxx_hci_register(&(g_huw_dev.hci));
+ dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+ alloc_ret = alloc_chrdev_region(&dev, 0, num_of_dev, FILE_DEVICE_SSVSDIO_NAME);
+ if (alloc_ret)
+ goto error;
+ ssv_sdiobridge_ioctl_major = MAJOR(dev);
+ cdev_init(&ssv_sdiobridge_ioctl_cdev, &s_huw_ops);
+ cdev_ret = cdev_add(&ssv_sdiobridge_ioctl_cdev, dev, num_of_dev);
+ if (cdev_ret)
+ goto error;
+ fc=class_create(THIS_MODULE, FILE_DEVICE_SSVSDIO_NAME);
+ fc->devnode = ssv_huw_devnode;
+ device_create(fc,NULL,dev,NULL,"%s",FILE_DEVICE_SSVSDIO_NAME);
+ dev_err(&pdev->dev, "%s driver(major: %d) installed.\n", FILE_DEVICE_SSVSDIO_NAME, ssv_sdiobridge_ioctl_major);
+ return 0;
+error:
+ if (cdev_ret == 0)
+ cdev_del(&ssv_sdiobridge_ioctl_cdev);
+ if (alloc_ret == 0)
+ unregister_chrdev_region(dev, num_of_dev);
+ return -ENODEV;
+}
+EXPORT_SYMBOL(ssv_huw_probe);
+int ssv_huw_remove(struct platform_device *pdev)
+{
+ dev_t dev;
+ int ret = 0;
+ tu_ssv6xxx_hci_deregister();
+ memset(&g_huw_dev, 0, sizeof(g_huw_dev));
+ dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+ device_destroy(fc,dev);
+ class_destroy(fc);
+ cdev_del(&ssv_sdiobridge_ioctl_cdev);
+ unregister_chrdev_region(dev, num_of_dev);
+ return ret;
+}
+EXPORT_SYMBOL(ssv_huw_remove);
+static const struct platform_device_id huw_id_table[] = {
+ {
+ .name = "ssv6200",
+ .driver_data = 0x00,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, huw_id_table);
+static struct platform_driver ssv_huw_driver = {
+ .probe = ssv_huw_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+ .remove = __devexit_p(ssv_huw_remove),
+#else
+ .remove = ssv_huw_remove,
+#endif
+ .id_table = huw_id_table,
+ .driver = {
+ .name = "TU SSV WLAN driver",
+ .owner = THIS_MODULE,
+ }
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv_huw_init(void)
+#else
+static int __init ssv_huw_init(void)
+#endif
+{
+ int ret;
+ memset(&g_huw_dev, 0, sizeof(g_huw_dev));
+ ret = platform_driver_register(&ssv_huw_driver);
+ if (ret < 0) {
+ printk(KERN_ALERT "[HCI user-space wrapper]: Fail to register huw\n");
+ }
+ return ret;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void ssv_huw_exit(void)
+#else
+static void __exit ssv_huw_exit(void)
+#endif
+{
+ platform_driver_unregister(&ssv_huw_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(ssv_huw_init);
+EXPORT_SYMBOL(ssv_huw_exit);
+#else
+module_init(ssv_huw_init);
+module_exit(ssv_huw_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h
new file mode 100644
index 000000000..42bb30932
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV_HUW_H_
+#define _SSV_HUW_H_
+#include
+struct ssv_huw_cmd {
+ __u32 in_data_len;
+ u8* in_data;
+#ifndef __x86_64
+ __u32 padding1;
+#endif
+ __u32 out_data_len;
+ u8* out_data;
+#ifndef __x86_64
+ __u32 padding2;
+#endif
+ __u32 response;
+} __attribute__((packed));
+#define FILE_DEVICE_SSVSDIO MMC_BLOCK_MAJOR
+#define FILE_DEVICE_SSVSDIO_SEQ 0x50
+#define FILE_DEVICE_SSVSDIO_NAME "ssvhuwdev"
+#if 0
+#define IOCTL_SSVSDIO_GET_DRIVER_VERSION \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x01, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_NUMBER \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x02, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x03, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x04, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x05, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x06, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x07, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x08, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x09, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0a, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0b, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0c, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0d, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0e, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0f, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x10, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x11, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x12, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x13, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x14, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x15, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x16, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x17, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x18, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x19, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1a, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1b, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1c, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1d, struct ssv_huw_cmd)
+#endif
+#define IOCTL_SSVSDIO_READ_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1e, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1f, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_DATA \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x20, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_SRAM \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x21, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_START \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x22, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_STOP \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x23, struct ssv_huw_cmd)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/hwif.h b/drivers/net/wireless/ssv6x5x/hwif/hwif.h
new file mode 100644
index 000000000..d4c6141cc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/hwif.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef __HWIF_H__
+#define __HWIF_H__
+#include
+#include
+#define SYS_REG_BASE 0xc0000000
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
+#define SSV_HWIF_CAPABILITY_MASK 0x00000001
+#define SSV_HWIF_INTERFACE_MASK 0x00000002
+#define SSV_HWIF_CAPABILITY_SFT 0
+#define SSV_HWIF_INTERFACE_SFT 1
+#define SSV_HWIF_CAPABILITY_INTERRUPT (0 << SSV_HWIF_CAPABILITY_SFT)
+#define SSV_HWIF_CAPABILITY_POLLING (1 << SSV_HWIF_CAPABILITY_SFT)
+#define SSV_HWIF_INTERFACE_SDIO (0 << SSV_HWIF_INTERFACE_SFT)
+#define SSV_HWIF_INTERFACE_USB (1 << SSV_HWIF_INTERFACE_SFT)
+#define SSV_REG_WRITE(dev,reg,val) \
+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(dev,reg,buf) \
+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define HWIF_DBG_PRINT(_pdata,format,args...) \
+ do { \
+ if ((_pdata != NULL) && ((_pdata)->dbg_control)) \
+ printk(format, ##args); \
+ } while (0)
+#if 0
+#define SSV_REG_WRITE(sh,reg,val) \
+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(sh,reg,buf) \
+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define SSV_REG_CONFIRM(sh,reg,val) \
+{ \
+ u32 regval; \
+ SSV_REG_READ(sh, reg, ®val); \
+ if (regval != (val)) { \
+ printk("[0x%08x]: 0x%08x!=0x%08x\n",\
+ (reg), (val), regval); \
+ return -1; \
+ } \
+}
+#define SSV_REG_SET_BITS(sh,reg,set,clr) \
+{ \
+ u32 reg_val; \
+ SSV_REG_READ(sh, reg, ®_val); \
+ reg_val &= ~(clr); \
+ reg_val |= (set); \
+ SSV_REG_WRITE(sh, reg, reg_val); \
+}
+#endif
+struct sdio_scatter_req;
+struct ssv6xxx_hwif_ops {
+ int __must_check (*read)(struct device *child, void *buf,size_t *size, int mode);
+ int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
+ int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
+ int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
+ int __must_check (*safe_readreg)(struct device *child, u32 addr, u32 *buf);
+ int __must_check (*safe_writereg)(struct device *child, u32 addr, u32 buf);
+ int __must_check (*burst_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+ int __must_check (*burst_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+ int __must_check (*burst_safe_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+ int __must_check (*burst_safe_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+ int (*trigger_tx_rx)(struct device *child);
+ int (*irq_getmask)(struct device *child, u32 *mask);
+ void (*irq_setmask)(struct device *child,int mask);
+ void (*irq_enable)(struct device *child);
+ void (*irq_disable)(struct device *child,bool iswaitirq);
+ int (*irq_getstatus)(struct device *child,int *status);
+ void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
+ void (*irq_trigger)(struct device *child);
+ void (*pmu_wakeup)(struct device *child);
+ int __must_check (*load_fw)(struct device *child, u32 start_addr, u8 *data, int data_length);
+ void (*load_fw_pre_config_device)(struct device *child);
+ void (*load_fw_post_config_device)(struct device *child);
+ int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
+ int (*cmd52_write)(struct device *child, u32 addr, u32 value);
+ bool (*support_scatter)(struct device *child);
+ int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
+ bool (*is_ready)(struct device *child);
+ int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
+ void (*interface_reset)(struct device *child);
+ int (*start_usb_acc)(struct device *child, u8 epnum);
+ int (*stop_usb_acc)(struct device *child, u8 epnum);
+ int (*jump_to_rom)(struct device *child);
+ int (*property)(struct device *child);
+ void (*sysplf_reset)(struct device *child, u32 addr, u32 value);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);
+#else
+ void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff *rx_skb, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);
+#endif
+};
+struct ssv6xxx_platform_data {
+ atomic_t irq_handling;
+ bool is_enabled;
+ u8 chip_id[SSV6XXX_CHIP_ID_LENGTH];
+ u8 short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH+1];
+ unsigned short vendor;
+ unsigned short device;
+ struct ssv6xxx_hwif_ops *ops;
+ bool dbg_control;
+ struct sk_buff *(*skb_alloc) (void *param, s32 len, gfp_t gfp_mask);
+ void (*skb_free) (void *param, struct sk_buff *skb);
+ void *skb_param;
+#ifdef CONFIG_PM
+ void (*suspend)(void *param);
+ void (*resume)(void *param);
+ void *pm_param;
+#endif
+ void (*enable_usb_acc)(void *param, u8 epnum);
+ void (*disable_usb_acc)(void *param, u8 epnum);
+ void (*jump_to_rom)(void *param);
+ void *usb_param;
+ int (*rx_burstread_size)(void *param);
+ void *rx_burstread_param;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile b/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile
new file mode 100755
index 000000000..0f10136ce
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile
@@ -0,0 +1,21 @@
+ifeq ($(KBUILD_TOP),)
+ ifneq ($(KBUILD_EXTMOD),)
+ KBUILD_DIR := $(KBUILD_EXTMOD)
+ else
+ KBUILD_DIR := $(PWD)
+ endif
+KBUILD_TOP := $(KBUILD_DIR)/../../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/smac/Module.symvers
+ifeq ($(DRV_OPT), HUW_DRV)
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci_wrapper/Module.symvers
+endif
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+KMODULE_NAME=ssv6200_sdio
+KERN_SRCS := sdio.c
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c
new file mode 100644
index 000000000..349514054
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c
@@ -0,0 +1,1921 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#include
+#else
+#include
+#endif
+#include
+#include "sdio_def.h"
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+#include "sdio.h"
+#endif
+#define LOW_SPEED_SDIO_CLOCK (25000000)
+#define HIGH_SPEED_SDIO_CLOCK (50000000)
+#define MAX_RX_FRAME_SIZE 0x900
+#define MAX_REG_RETRY_CNT (3)
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define CHECK_IO_RET(GLUE,RET) \
+ do { \
+ if (RET) { \
+ if ((++((GLUE)->err_count)) > MAX_ERR_COUNT) \
+ printk(KERN_ERR "MAX SDIO Error\n"); \
+ } else \
+ (GLUE)->err_count = 0; \
+ } while (0)
+#define MAX_ERR_COUNT (10)
+struct ssv6xxx_sdio_glue {
+ struct device *dev;
+ struct platform_device *core;
+ struct ssv6xxx_platform_data *p_wlan_data;
+ struct ssv6xxx_platform_data tmp_data;
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ PLATFORM_DMA_ALIGNED u8 rreg_data[4];
+ PLATFORM_DMA_ALIGNED u8 wreg_data[8];
+ PLATFORM_DMA_ALIGNED u32 brreg_data[MAX_BURST_READ_REG_AMOUNT];
+ PLATFORM_DMA_ALIGNED u8 bwreg_data[MAX_BURST_WRITE_REG_AMOUNT][8];
+ PLATFORM_DMA_ALIGNED u32 aggr_readsz;
+#endif
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+ struct sk_buff *dmaSkb;
+#endif
+
+
+ /* for ssv SDIO */
+ unsigned int dataIOPort;
+ unsigned int regIOPort;
+
+ irq_handler_t irq_handler;
+ void *irq_dev;
+ bool dev_ready;
+ unsigned int err_count;
+};
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,
+ struct sdio_func *func, struct ssv6xxx_sdio_glue *glue);
+#define IS_GLUE_INVALID(glue) \
+ ( (glue == NULL) \
+ || (glue->dev_ready == false) \
+ || ( (glue->p_wlan_data != NULL) \
+ && (glue->p_wlan_data->is_enabled == false)) \
+ || (glue->err_count > MAX_ERR_COUNT))
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+static const struct sdio_device_id ssv6xxx_sdio_devices[] __devinitconst =
+#else
+static const struct sdio_device_id ssv6xxx_sdio_devices[] =
+#endif
+{
+ { SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID) },
+ {}
+};
+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
+static bool ssv6xxx_is_ready (struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue))
+ return false;
+ return glue->dev_ready;
+}
+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr,
+ u32 *value)
+{
+ int ret = -1;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ *value = sdio_readb(func, addr, &ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ }
+ return ret;
+}
+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr,
+ u32 value)
+{
+ int ret = -1;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func, value, addr, &ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ }
+ return ret;
+}
+static int __must_check __ssv6xxx_sdio_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+ u32 *buf)
+{
+ int ret = (-1);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[4];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[4];
+#endif
+
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ //dev_err(&func->dev, "sdio read reg device[%08x] parent[%08x]\n",child,child->parent);
+
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+ // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->rreg_data[0] = (addr >> ( 0 )) &0xff;
+ glue->rreg_data[1] = (addr >> ( 8 )) &0xff;
+ glue->rreg_data[2] = (addr >> ( 16 )) &0xff;
+ glue->rreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+ data[0] = (addr >> ( 0 )) &0xff;
+ data[1] = (addr >> ( 8 )) &0xff;
+ data[2] = (addr >> ( 16 )) &0xff;
+ data[3] = (addr >> ( 24 )) &0xff;
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, glue->regIOPort, glue->rreg_data, 4);
+#else
+ ret = sdio_memcpy_toio(func, glue->regIOPort, data, 4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(&func->dev, "sdio read reg write address failed (%d)\n", ret);
+ goto io_err;
+ }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_fromio(func, glue->rreg_data, glue->regIOPort, 4);
+#else
+ ret = sdio_memcpy_fromio(func, data, glue->regIOPort, 4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(&func->dev, "sdio read reg from I/O failed (%d)\n",ret);
+ goto io_err;
+ }
+ if(ret == 0) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ *buf = (glue->rreg_data[0]&0xff);
+ *buf = *buf | ((glue->rreg_data[1]&0xff)<<( 8 ));
+ *buf = *buf | ((glue->rreg_data[2]&0xff)<<( 16 ));
+ *buf = *buf | ((glue->rreg_data[3]&0xff)<<( 24 ));
+#else
+ *buf = (data[0]&0xff);
+ *buf = *buf | ((data[1]&0xff)<<( 8 ));
+ *buf = *buf | ((data[2]&0xff)<<( 16 ));
+ *buf = *buf | ((data[3]&0xff)<<( 24 ));
+#endif
+ } else
+ *buf = 0xffffffff;
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(&func->dev, "sdio read reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check __ssv6xxx_sdio_safe_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+ u32 *buf)
+{
+ int ret = (-1), rdy_flag_cnt = 0;
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[4];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[4];
+#endif
+
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ //dev_err(&func->dev, "sdio read reg device[%08x] parent[%08x]\n",child,child->parent);
+
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+ // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->rreg_data[0] = (addr >> ( 0 )) &0xff;
+ glue->rreg_data[1] = (addr >> ( 8 )) &0xff;
+ glue->rreg_data[2] = (addr >> ( 16 )) &0xff;
+ glue->rreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+ data[0] = (addr >> ( 0 )) &0xff;
+ data[1] = (addr >> ( 8 )) &0xff;
+ data[2] = (addr >> ( 16 )) &0xff;
+ data[3] = (addr >> ( 24 )) &0xff;
+#endif
+
+ //8 byte ( 4 bytes address , 4 bytes data )
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, glue->regIOPort, glue->rreg_data, 4);
+#else
+ ret = sdio_memcpy_toio(func, glue->regIOPort, data, 4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(&func->dev, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+ goto io_err;
+ }
+ rdy_flag_cnt = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_fromio(func, glue->rreg_data, glue->regIOPort, 4);
+#else
+ ret = sdio_memcpy_fromio(func, data, glue->regIOPort, 4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(&func->dev, "%s: sdio read from I/O failed (%d)\n", __func__,ret);
+ goto io_err;
+ }
+ if(ret == 0) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ *buf = (glue->rreg_data[0]&0xff);
+ *buf = *buf | ((glue->rreg_data[1]&0xff)<<( 8 ));
+ *buf = *buf | ((glue->rreg_data[2]&0xff)<<( 16 ));
+ *buf = *buf | ((glue->rreg_data[3]&0xff)<<( 24 ));
+#else
+ *buf = (data[0]&0xff);
+ *buf = *buf | ((data[1]&0xff)<<( 8 ));
+ *buf = *buf | ((data[2]&0xff)<<( 16 ));
+ *buf = *buf | ((data[3]&0xff)<<( 24 ));
+#endif
+ } else
+ *buf = 0xffffffff;
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(&func->dev, "sdio read reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_read_reg(struct device *child, u32 addr,
+ u32 *buf)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ int i, ret;
+ for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+ ret = __ssv6xxx_sdio_read_reg(glue, addr, buf);
+ if (!ret)
+ return ret;
+ }
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register, addr 0x%08x\n", __FUNCTION__, addr);
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_safe_read_reg(struct device *child, u32 addr,
+ u32 *buf)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ int i, ret;
+ for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+ ret = __ssv6xxx_sdio_safe_read_reg(glue, addr, buf);
+ if (!ret)
+ return ret;
+ }
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register, addr 0x%08x\n", __FUNCTION__, addr);
+ return ret;
+}
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+static int ssv6xxx_sdio_trigger_tx_rx (struct device *child)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ struct mmc_host *host;
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ func = dev_to_sdio_func(glue->dev);
+ host = func->card->host;
+ mmc_signal_sdio_irq(host);
+ return 0;
+}
+#endif
+static int __must_check __ssv6xxx_sdio_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+ u32 buf)
+{
+ int ret = (-1);
+ struct sdio_func *func;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[8];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[8];
+#endif
+
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+ // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->wreg_data[0] = (addr >> ( 0 )) &0xff;
+ glue->wreg_data[1] = (addr >> ( 8 )) &0xff;
+ glue->wreg_data[2] = (addr >> ( 16 )) &0xff;
+ glue->wreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+ data[0] = (addr >> ( 0 )) &0xff;
+ data[1] = (addr >> ( 8 )) &0xff;
+ data[2] = (addr >> ( 16 )) &0xff;
+ data[3] = (addr >> ( 24 )) &0xff;
+#endif
+
+ // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->wreg_data[4] = (buf >> ( 0 )) &0xff;
+ glue->wreg_data[5] = (buf >> ( 8 )) &0xff;
+ glue->wreg_data[6] = (buf >> ( 16 )) &0xff;
+ glue->wreg_data[7] = (buf >> ( 24 )) &0xff;
+#else
+ data[4] = (buf >> ( 0 )) &0xff;
+ data[5] = (buf >> ( 8 )) &0xff;
+ data[6] = (buf >> ( 16 )) &0xff;
+ data[7] = (buf >> ( 24 )) &0xff;
+#endif
+
+ //8 byte ( 4 bytes address , 4 bytes data )
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, glue->regIOPort, glue->wreg_data, 8);
+#else
+ ret = sdio_memcpy_toio(func, glue->regIOPort, data, 8);
+#endif
+
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(&func->dev, "sdio write reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check __ssv6xxx_sdio_safe_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+ u32 buf)
+{
+ int ret = (-1);
+ struct sdio_func *func;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[8];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[8];
+#endif
+#if (defined(SSV_SUPPORT_SSV6006))
+ int rdy_flag_cnt = 0;
+#endif
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->wreg_data[0] = (addr >> ( 0 )) &0xff;
+ glue->wreg_data[1] = (addr >> ( 8 )) &0xff;
+ glue->wreg_data[2] = (addr >> ( 16 )) &0xff;
+ glue->wreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+ data[0] = (addr >> ( 0 )) &0xff;
+ data[1] = (addr >> ( 8 )) &0xff;
+ data[2] = (addr >> ( 16 )) &0xff;
+ data[3] = (addr >> ( 24 )) &0xff;
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->wreg_data[4] = (buf >> ( 0 )) &0xff;
+ glue->wreg_data[5] = (buf >> ( 8 )) &0xff;
+ glue->wreg_data[6] = (buf >> ( 16 )) &0xff;
+ glue->wreg_data[7] = (buf >> ( 24 )) &0xff;
+#else
+ data[4] = (buf >> ( 0 )) &0xff;
+ data[5] = (buf >> ( 8 )) &0xff;
+ data[6] = (buf >> ( 16 )) &0xff;
+ data[7] = (buf >> ( 24 )) &0xff;
+#endif
+
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, glue->regIOPort, glue->wreg_data, 8);
+#else
+ ret = sdio_memcpy_toio(func, glue->regIOPort, data, 8);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(&func->dev, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+ goto io_err;
+ }
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(&func->dev, "sdio write reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_write_reg(struct device *child, u32 addr,
+ u32 buf)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ int i, ret;
+ for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+ ret = __ssv6xxx_sdio_write_reg(glue, addr, buf);
+ if (!ret) {
+#ifdef __x86_64
+ udelay(50);
+#endif
+ return ret;
+ }
+ }
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register, addr 0x%08x, value 0x%08x\n", __FUNCTION__, addr, buf);
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_safe_write_reg(struct device *child, u32 addr,
+ u32 buf)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ int i, ret;
+ for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+ ret = __ssv6xxx_sdio_safe_write_reg(glue, addr, buf);
+ if (!ret) {
+#ifdef __x86_64
+ udelay(50);
+#endif
+ return ret;
+ }
+ }
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register, addr 0x%08x, value 0x%08x\n", __FUNCTION__, addr, buf);
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_read_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#endif
+ u8 i = 0;
+
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ if (reg_amount > MAX_BURST_READ_REG_AMOUNT) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+ MAX_BURST_READ_REG_AMOUNT);
+ return ret;
+ }
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ for (i=0; ibrreg_data[i], &addr[i], 4);
+#else
+ memcpy(&data[i], &addr[i], 4);
+#endif
+ }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, glue->brreg_data, reg_amount*4);
+#else
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, data, reg_amount*4);
+#endif
+
+ if (WARN_ON(ret)) {
+ dev_err(child->parent, "sdio burst-read reg write address failed (%d)\n", ret);
+ goto io_err;
+ }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_fromio(func, glue->brreg_data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#else
+ ret = sdio_memcpy_fromio(func, data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(child->parent, "sdio burst-read reg from I/O failed (%d)\n",ret);
+ goto io_err;
+ }
+ if(ret == 0)
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ memcpy(buf, glue->brreg_data, reg_amount*4);
+#else
+ memcpy(buf, data, reg_amount*4);
+#endif
+ else
+ memset(buf, 0xffffffff, reg_amount*4);
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(child->parent, "sdio burst-read reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_safe_read_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#endif
+ u8 i = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+ int rdy_flag_cnt = 0;
+#endif
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ if (reg_amount > MAX_BURST_READ_REG_AMOUNT) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+ MAX_BURST_READ_REG_AMOUNT);
+ return ret;
+ }
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ for (i=0; ibrreg_data[i], &addr[i], 4);
+#else
+ memcpy(&data[i], &addr[i], 4);
+#endif
+ }
+
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, glue->brreg_data, reg_amount*4);
+#else
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, data, reg_amount*4);
+#endif
+
+ if (WARN_ON(ret)) {
+ dev_err(child->parent, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+ goto io_err;
+ }
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_fromio(func, glue->brreg_data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#else
+ ret = sdio_memcpy_fromio(func, data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(child->parent, "%s: sdio read from I/O failed (%d)\n", __func__, ret);
+ goto io_err;
+ }
+ if(ret == 0)
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ memcpy(buf, glue->brreg_data, reg_amount*4);
+#else
+ memcpy(buf, data, reg_amount*4);
+#endif
+ else
+ memset(buf, 0xffffffff, reg_amount*4);
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(child->parent, "sdio burst-read reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_write_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#endif
+ u8 i = 0;
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+
+ if (reg_amount > MAX_BURST_WRITE_REG_AMOUNT) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+ MAX_BURST_WRITE_REG_AMOUNT);
+ return ret;
+ }
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ for (i=0; ibwreg_data[i][0] = (addr[i] >> ( 0 )) &0xff;
+ glue->bwreg_data[i][1] = (addr[i] >> ( 8 )) &0xff;
+ glue->bwreg_data[i][2] = (addr[i] >> ( 16 )) &0xff;
+ glue->bwreg_data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#else
+ data[i][0] = (addr[i] >> ( 0 )) &0xff;
+ data[i][1] = (addr[i] >> ( 8 )) &0xff;
+ data[i][2] = (addr[i] >> ( 16 )) &0xff;
+ data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#endif
+
+ // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->bwreg_data[i][4] = (buf[i] >> ( 0 )) &0xff;
+ glue->bwreg_data[i][5] = (buf[i] >> ( 8 )) &0xff;
+ glue->bwreg_data[i][6] = (buf[i] >> ( 16 )) &0xff;
+ glue->bwreg_data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#else
+ data[i][4] = (buf[i] >> ( 0 )) &0xff;
+ data[i][5] = (buf[i] >> ( 8 )) &0xff;
+ data[i][6] = (buf[i] >> ( 16 )) &0xff;
+ data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#endif
+ }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, glue->bwreg_data, reg_amount*8);
+#else
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, data, reg_amount*8);
+#endif
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(child->parent, "sdio burst-write reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_safe_write_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+ u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#endif
+ u8 i = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+ int rdy_flag_cnt = 0;
+#endif
+ if (IS_GLUE_INVALID(glue)) {
+ return ret;
+ }
+ if (reg_amount > MAX_BURST_WRITE_REG_AMOUNT) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+ MAX_BURST_WRITE_REG_AMOUNT);
+ return ret;
+ }
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ for (i=0; ibwreg_data[i][0] = (addr[i] >> ( 0 )) &0xff;
+ glue->bwreg_data[i][1] = (addr[i] >> ( 8 )) &0xff;
+ glue->bwreg_data[i][2] = (addr[i] >> ( 16 )) &0xff;
+ glue->bwreg_data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#else
+ data[i][0] = (addr[i] >> ( 0 )) &0xff;
+ data[i][1] = (addr[i] >> ( 8 )) &0xff;
+ data[i][2] = (addr[i] >> ( 16 )) &0xff;
+ data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#endif
+
+ // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->bwreg_data[i][4] = (buf[i] >> ( 0 )) &0xff;
+ glue->bwreg_data[i][5] = (buf[i] >> ( 8 )) &0xff;
+ glue->bwreg_data[i][6] = (buf[i] >> ( 16 )) &0xff;
+ glue->bwreg_data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#else
+ data[i][4] = (buf[i] >> ( 0 )) &0xff;
+ data[i][5] = (buf[i] >> ( 8 )) &0xff;
+ data[i][6] = (buf[i] >> ( 16 )) &0xff;
+ data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#endif
+ }
+
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, glue->bwreg_data, reg_amount*8);
+#else
+ ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, data, reg_amount*8);
+#endif
+ if (WARN_ON(ret)) {
+ dev_err(child->parent, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+ goto io_err;
+ }
+#if (defined(SSV_SUPPORT_SSV6006))
+ while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+ if (ret != 0) {
+ printk("%s: ret=%d", __func__, ret);
+ goto io_err;
+ } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+ ret = -EBUSY;
+ dev_err(&func->dev, "%s: bus is busy\n", __func__);
+ goto io_err;
+ }
+ udelay(SDIO_READY_FLAG_BUSY_DELAY);
+ }
+#endif
+io_err:
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ } else {
+ dev_err(child->parent, "sdio burst-write reg glue == NULL!!!\n");
+ }
+ return ret;
+}
+static int ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 *data, u32 size)
+{
+ int ret = -1;
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func=NULL;
+ glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ do {
+ if (ssv6xxx_sdio_write_reg(child,0xc0000860,addr)) ;
+ sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
+ if (unlikely(ret)) break;
+ ret = sdio_memcpy_toio(func, glue->dataIOPort, data, size);
+ if (unlikely(ret)) break;
+ sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
+ if (unlikely(ret)) break;
+ } while (0);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ return ret;
+}
+static int ssv6xxx_sdio_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)
+{
+ return ssv6xxx_sdio_write_sram(child, start_addr, data, data_length);
+}
+static void ssv6xxx_sdio_load_fw_pre_config_hwif(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func=NULL;
+ glue = dev_get_drvdata(child->parent);
+ if (!IS_GLUE_INVALID(glue)) {
+ func = dev_to_sdio_func(glue->dev);
+ ssv6xxx_low_sdio_clk(func);
+ }
+}
+static void ssv6xxx_sdio_load_fw_post_config_hwif(struct device *child)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func=NULL;
+ glue = dev_get_drvdata(child->parent);
+ if (!IS_GLUE_INVALID(glue)) {
+ func = dev_to_sdio_func(glue->dev);
+ ssv6xxx_high_sdio_clk(func);
+ }
+#endif
+}
+static int ssv6xxx_sdio_irq_getstatus(struct device *child,int *status)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func;
+ glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ *status = sdio_readb(func, REG_INT_STATUS, &ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ }
+ return ret;
+}
+#if 0
+static void _sdio_hexdump(const u8 *buf,
+ size_t len)
+{
+ size_t i;
+ printk("\n-----------------------------\n");
+ printk("hexdump(len=%lu):\n", (unsigned long) len);
+ {
+ for (i = 0; i < len; i++) {
+ printk(" %02x", buf[i]);
+ if((i+1)%40 ==0)
+ printk("\n");
+ }
+ }
+ printk("\n-----------------------------\n");
+}
+#endif
+static size_t ssv6xxx_sdio_get_readsz(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+ size_t size = 0;
+ int ret = -1;
+ u32 addr = SD_REG_BASE+REG_CARD_PKT_LEN_0;
+ u32 buf;
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ ret = ssv6xxx_sdio_safe_read_reg(child, addr, &buf);
+ if (ret) {
+ dev_err(child->parent, "sdio read len failed ret[%d]\n",ret);
+ size = 0;
+ } else {
+ size = (size_t)(buf&0xffff);
+ }
+ sdio_release_host(func);
+ return size;
+}
+static size_t ssv6xxx_sdio_get_aggr_readsz(struct device *child, int mode)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+ PLATFORM_DMA_ALIGNED u32 size = 0;
+#else
+ u32 size = 0;
+#endif
+ int ret = -1;
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ ret = sdio_memcpy_fromio(func, &glue->aggr_readsz, glue->dataIOPort, sizeof(u32)/* jmp_mpdu_len + accu_rx_len, total 4 bytes */);
+#else
+ ret = sdio_memcpy_fromio(func, &size, glue->dataIOPort, sizeof(u32)/* jmp_mpdu_len + accu_rx_len, total 4 bytes */);
+#endif
+ if (ret) {
+ dev_err(child->parent, "%s(): sdio read failed size ret[%d]\n", __func__, ret);
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ glue->aggr_readsz = 0;
+#else
+ size = 0;
+#endif
+ }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+ size = sdio_align_size(func, (glue->aggr_readsz >> 16));// accu_rx_len
+#else
+ size = sdio_align_size(func, (size >> 16));// accu_rx_len
+#endif
+
+ sdio_release_host(func);
+ return (size_t)size;
+}
+static int __must_check ssv6xxx_sdio_read(struct device *child,
+ void *buf, size_t *size, int mode)
+{
+ int ret = (-1), readsize = 0;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func ;
+ int readtype = 0;
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if (mode == RX_NORMAL_MODE) {
+ *size = ssv6xxx_sdio_get_readsz(child);
+ if (*size == 0)
+ return ret;
+ } else if ((mode == RX_HW_AGG_MODE) || (mode == RX_HW_AGG_MODE_METH3)) {
+ if (*size == 0) {
+ *size = ssv6xxx_sdio_get_aggr_readsz(child, mode);
+ if (*size == 0)
+ return ret;
+ }
+ } else {
+ readtype = glue->p_wlan_data->rx_burstread_size(glue->p_wlan_data->rx_burstread_param);
+ if (readtype == RX_BURSTREAD_SZ_FROM_CMD) {
+ *size = ssv6xxx_sdio_get_readsz(child);
+ if (*size == 0)
+ return ret;
+ } else if (readtype == RX_BURSTREAD_SZ_MAX_FRAME) {
+ *size = MAX_FRAME_SIZE;
+ } else {
+ *size = MAX_FRAME_SIZE_DMG;
+ }
+ }
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ readsize = sdio_align_size(func,*size);
+ *size = readsize;
+ ret = sdio_memcpy_fromio(func, buf, glue->dataIOPort, readsize);
+ if (ret)
+ dev_err(child->parent, "sdio read failed size ret[%d]\n",ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+#if 0
+ if(*size > 1500)
+ _sdio_hexdump(buf,*size);
+#endif
+ return ret;
+}
+static int __must_check ssv6xxx_sdio_write(struct device *child,
+ void *buf, size_t len,u8 queue_num)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ int writesize;
+ void *tempPointer;
+ struct sk_buff *skb = (struct sk_buff *)buf;
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if ( glue != NULL ) {
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+#ifdef CONFIG_ARM64
+ if (((u64)(skb->data)) & 3) {
+#else
+ if (((u32)(skb->data)) & 3) {
+#endif
+ memcpy(glue->dmaSkb->data,skb->data,len);
+ tempPointer = glue->dmaSkb->data;
+ } else
+#endif
+ tempPointer = skb->data;
+#if 0
+ if(len > 1500)
+ _sdio_hexdump(skb->data,len);
+#endif
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ writesize = sdio_align_size(func,len);
+ do {
+ ret = sdio_memcpy_toio(func, glue->dataIOPort, tempPointer, writesize);
+ if ( ret == -EILSEQ || ret == -ETIMEDOUT ) {
+ ret = -1;
+ break;
+ } else {
+ if(ret)
+ dev_err(&func->dev,"Unexpected return value ret=[%d]\n",ret);
+ }
+ } while( ret == -EILSEQ || ret == -ETIMEDOUT);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+ if (ret)
+ dev_err(&func->dev, "sdio write failed (%d)\n", ret);
+ }
+ return ret;
+}
+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
+{
+ int status;
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ struct ssv6xxx_platform_data *pwlan_data;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ pwlan_data = glue->p_wlan_data;
+ if (glue != NULL && glue->irq_handler != NULL) {
+ atomic_set(&pwlan_data->irq_handling, 1);
+ sdio_release_host(func);
+ if ( glue->irq_handler != NULL )
+ status = glue->irq_handler(0, glue->irq_dev);
+ sdio_claim_host(func);
+ atomic_set(&pwlan_data->irq_handling, 0);
+ }
+}
+static void ssv6xxx_sdio_irq_setmask(struct device *child,int mask)
+{
+ int err_ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func,mask, REG_INT_MASK, &err_ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, err_ret);
+ }
+}
+static void ssv6xxx_sdio_irq_trigger(struct device *child)
+{
+ int err_ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func,0x2, REG_INT_TRIGGER, &err_ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, err_ret);
+ }
+}
+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 *mask)
+{
+ u8 imask = 0;
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (IS_GLUE_INVALID(glue))
+ return ret;
+ if ( glue != NULL ) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ imask = sdio_readb(func,REG_INT_MASK, &ret);
+ *mask = imask;
+ sdio_release_host(func);
+ }
+ return ret;
+}
+static void ssv6xxx_sdio_irq_enable(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ int ret;
+ struct ssv6xxx_platform_data *pwlan_data;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ pwlan_data = glue->p_wlan_data;
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
+ if (ret)
+ dev_err(&func->dev, "Failed to claim sdio irq: %d\n", ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, ret);
+}
+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ struct ssv6xxx_platform_data *pwlan_data;
+ int ret;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "ssv6xxx_sdio_irq_disable\n");
+ pwlan_data = glue->p_wlan_data;
+ func = dev_to_sdio_func(glue->dev);
+ if (func == NULL) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "func == NULL\n");
+ return;
+ }
+ sdio_claim_host(func);
+ while (atomic_read(&pwlan_data->irq_handling)) {
+ sdio_release_host(func);
+ schedule_timeout(HZ / 10);
+ sdio_claim_host(func);
+ }
+ ret = sdio_release_irq(func);
+ if (ret)
+ dev_err(&func->dev, "Failed to release sdio irq: %d\n", ret);
+ sdio_release_host(func);
+}
+static void ssv6xxx_sdio_irq_request(struct device *child,irq_handler_t irq_handler,void *irq_dev)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ bool isIrqEn = false;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ func = dev_to_sdio_func(glue->dev);
+ glue->irq_handler = irq_handler;
+ glue->irq_dev = irq_dev;
+ if (isIrqEn) {
+ ssv6xxx_sdio_irq_enable(child);
+ }
+}
+static void ssv6xxx_sdio_read_parameter(struct sdio_func *func,
+ struct ssv6xxx_sdio_glue *glue)
+{
+ int err_ret;
+ sdio_claim_host(func);
+ glue->dataIOPort = 0;
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret) << ( 8*0 ));
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret) << ( 8*1 ));
+ glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret) << ( 8*2 ));
+ glue->regIOPort = 0;
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) << ( 8*0 ));
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) << ( 8*1 ));
+ glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) << ( 8*2 ));
+ dev_err(&func->dev, "dataIOPort 0x%x regIOPort 0x%x\n",glue->dataIOPort,glue->regIOPort);
+#ifdef CONFIG_PLATFORM_SDIO_BLOCK_SIZE
+ err_ret = sdio_set_block_size(func,CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
+#else
+ err_ret = sdio_set_block_size(func,SDIO_DEF_BLOCK_SIZE);
+#endif
+ if (err_ret != 0) {
+ printk("SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
+ }
+#ifdef CONFIG_PLATFORM_SDIO_OUTPUT_TIMING
+ sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,REG_OUTPUT_TIMING_REG, &err_ret);
+#else
+ sdio_writeb(func, SDIO_DEF_OUTPUT_TIMING,REG_OUTPUT_TIMING_REG, &err_ret);
+#endif
+ sdio_writeb(func, 0x00,REG_Fn1_STATUS, &err_ret);
+#if 0
+ sdio_writeb(func,SDIO_TX_ALLOC_SIZE_SHIFT|SDIO_TX_ALLOC_ENABLE,REG_SDIO_TX_ALLOC_SHIFT, &err_ret);
+#endif
+ sdio_release_host(func);
+}
+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
+{
+ int err_ret;
+ if(func != NULL) {
+ sdio_claim_host(func);
+ sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
+ mdelay(10);
+ sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
+ sdio_release_host(func);
+ }
+}
+static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (glue != NULL) {
+ func = dev_to_sdio_func(glue->dev);
+ ssv6xxx_do_sdio_wakeup(func);
+ }
+}
+static bool ssv6xxx_sdio_support_scatter(struct device *child)
+{
+ bool support = false;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ do {
+ if (IS_GLUE_INVALID(glue)) {
+ dev_err(child, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+ break;
+ }
+ func = dev_to_sdio_func(glue->dev);
+ if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+ dev_err(&func->dev, "host controller only supports scatter of :%d entries, driver need: %d\n",
+ func->card->host->max_segs,
+ MAX_SCATTER_ENTRIES_PER_REQ);
+ break;
+ }
+ support = true;
+ } while (0);
+#endif
+ return support;
+}
+static void ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
+ struct mmc_data *data)
+{
+ struct scatterlist *sg;
+ int i;
+ data->blksz = SDIO_DEF_BLOCK_SIZE;
+ data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
+ printk("scatter: (%s) (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
+ (scat_req->req & SDIO_WRITE) ? "WR" : "RD",
+ data->blksz, data->blocks, scat_req->len,
+ scat_req->scat_entries);
+ data->flags = (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE :
+ MMC_DATA_READ;
+ sg = scat_req->sgentries;
+ sg_init_table(sg, scat_req->scat_entries);
+ for (i = 0; i < scat_req->scat_entries; i++, sg++) {
+ printk("%d: addr:0x%p, len:%d\n",
+ i, scat_req->scat_list[i].buf,
+ scat_req->scat_list[i].len);
+ sg_set_buf(sg, scat_req->scat_list[i].buf,
+ scat_req->scat_list[i].len);
+ }
+ data->sg = scat_req->sgentries;
+ data->sg_len = scat_req->scat_entries;
+}
+static inline void ssv6xxx_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
+ u8 mode, u8 opcode, u32 addr,
+ u16 blksz)
+{
+ *arg = (((rw & 1) << 31) |
+ ((func & 0x7) << 28) |
+ ((mode & 1) << 27) |
+ ((opcode & 1) << 26) |
+ ((addr & 0x1FFFF) << 9) |
+ (blksz & 0x1FF));
+}
+static int ssv6xxx_sdio_rw_scatter(struct device *child,
+ struct sdio_scatter_req *scat_req)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ struct mmc_request mmc_req;
+ struct mmc_command cmd;
+ struct mmc_data data;
+ u8 opcode, rw;
+ int status = 1;
+ do {
+ if(!glue) {
+ dev_err(child, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+ break;
+ }
+ func = dev_to_sdio_func(glue->dev);
+ memset(&mmc_req, 0, sizeof(struct mmc_request));
+ memset(&cmd, 0, sizeof(struct mmc_command));
+ memset(&data, 0, sizeof(struct mmc_data));
+ ssv6xxx_sdio_setup_scat_data(scat_req, &data);
+ opcode = 0;
+ rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
+ ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
+ CMD53_ARG_BLOCK_BASIS, opcode, glue->dataIOPort,
+ data.blocks);
+ cmd.opcode = SD_IO_RW_EXTENDED;
+ cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+ mmc_req.cmd = &cmd;
+ mmc_req.data = &data;
+ mmc_set_data_timeout(&data, func->card);
+ mmc_wait_for_req(func->card->host, &mmc_req);
+ status = cmd.error ? cmd.error : data.error;
+ if (cmd.error)
+ return cmd.error;
+ if (data.error)
+ return data.error;
+ } while(0);
+ return status;
+}
+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
+{
+ struct mmc_host *host;
+ host = func->card->host;
+ if (sdio_hz < host->f_min)
+ sdio_hz = host->f_min;
+ else if (sdio_hz > host->f_max)
+ sdio_hz = host->f_max;
+ printk("%s: set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
+ sdio_claim_host(func);
+ host->ios.clock = sdio_hz;
+ host->ops->set_ios(host, &host->ios);
+ mdelay(20);
+ sdio_release_host(func);
+}
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
+{
+ ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
+}
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+ ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
+#endif
+}
+static void ssv6xxx_sdio_reset(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ if (IS_GLUE_INVALID(glue))
+ return;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s\n", __FUNCTION__);
+ ssv6xxx_do_sdio_reset_reinit(glue->p_wlan_data, func, glue);
+}
+static int ssv6xxx_sdio_property(struct device *child)
+{
+ return SSV_HWIF_CAPABILITY_INTERRUPT | SSV_HWIF_INTERFACE_SDIO;
+}
+static void ssv6xxx_sdio_sysplf_reset(struct device *child, u32 addr, u32 value)
+{
+ int retval = 0;
+ retval = ssv6xxx_sdio_write_reg(child, addr, value);
+ if (retval)
+ printk("Fail to reset sysplf.\n");
+}
+static struct ssv6xxx_hwif_ops sdio_ops = {
+ .read = ssv6xxx_sdio_read,
+ .write = ssv6xxx_sdio_write,
+ .readreg = ssv6xxx_sdio_read_reg,
+ .writereg = ssv6xxx_sdio_write_reg,
+ .safe_readreg = ssv6xxx_sdio_safe_read_reg,
+ .safe_writereg = ssv6xxx_sdio_safe_write_reg,
+ .burst_readreg = ssv6xxx_sdio_burst_read_reg,
+ .burst_writereg = ssv6xxx_sdio_burst_write_reg,
+ .burst_safe_readreg = ssv6xxx_sdio_burst_safe_read_reg,
+ .burst_safe_writereg = ssv6xxx_sdio_burst_safe_write_reg,
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+ .trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
+#endif
+ .irq_getmask = ssv6xxx_sdio_irq_getmask,
+ .irq_setmask = ssv6xxx_sdio_irq_setmask,
+ .irq_enable = ssv6xxx_sdio_irq_enable,
+ .irq_disable = ssv6xxx_sdio_irq_disable,
+ .irq_getstatus = ssv6xxx_sdio_irq_getstatus,
+ .irq_request = ssv6xxx_sdio_irq_request,
+ .irq_trigger = ssv6xxx_sdio_irq_trigger,
+ .pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
+ .load_fw = ssv6xxx_sdio_load_firmware,
+ .load_fw_pre_config_device = ssv6xxx_sdio_load_fw_pre_config_hwif,
+ .load_fw_post_config_device = ssv6xxx_sdio_load_fw_post_config_hwif,
+ .cmd52_read = ssv6xxx_sdio_cmd52_read,
+ .cmd52_write = ssv6xxx_sdio_cmd52_write,
+ .support_scatter = ssv6xxx_sdio_support_scatter,
+ .rw_scatter = ssv6xxx_sdio_rw_scatter,
+ .is_ready = ssv6xxx_is_ready,
+ .write_sram = ssv6xxx_sdio_write_sram,
+ .interface_reset = ssv6xxx_sdio_reset,
+ .property = ssv6xxx_sdio_property,
+ .sysplf_reset = ssv6xxx_sdio_sysplf_reset,
+};
+#ifdef CONFIG_PCIEASPM
+#include
+#include
+static int cabrio_sdio_pm_check(struct sdio_func *func)
+{
+ struct pci_dev *pci_dev = NULL;
+ struct mmc_card *card = func->card;
+ struct mmc_host *host = card->host;
+ if (strcmp(host->parent->bus->name, "pci")) {
+ dev_info(&func->dev, "SDIO host is not PCI device, but \"%s\".", host->parent->bus->name);
+ return 0;
+ }
+ for_each_pci_dev(pci_dev) {
+ if ( ((pci_dev->class >> 8) != PCI_CLASS_SYSTEM_SDHCI)
+ && ( (pci_dev->driver == NULL)
+ || (strcmp(pci_dev->driver->name, "sdhci-pci") != 0)))
+ continue;
+ if (pci_is_pcie(pci_dev)) {
+ u8 aspm;
+ int pos;
+ pos = pci_pcie_cap(pci_dev);
+ if (pos) {
+ struct pci_dev *parent = pci_dev->bus->self;
+ pci_read_config_byte(pci_dev, pos + PCI_EXP_LNKCTL, &aspm);
+ aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+ pci_write_config_byte(pci_dev, pos + PCI_EXP_LNKCTL, aspm);
+ pos = pci_pcie_cap(parent);
+ pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
+ aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+ pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
+ dev_info(&pci_dev->dev, "Clear PCI-E device and its parent link state L0S and L1 and CLKPM.\n");
+ }
+ }
+ }
+ return 0;
+}
+#endif
+static int ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+{
+ int ret = 0;
+ if (pdata->is_enabled == true)
+ return 0;
+
+ sdio_claim_host(func);
+ ret = sdio_enable_func(func);
+ sdio_release_host(func);
+ if (ret) {
+ printk("Unable to enable sdio func: %d)\n", ret);
+ return ret;
+ }
+ msleep(10);
+ pdata->is_enabled = true;
+ return ret;
+}
+static int ssv6xxx_do_sdio_init_seq_5537(struct sdio_func *func)
+{
+ int status = 1;
+ struct mmc_command cmd = {0};
+ cmd.opcode = SD_IO_SEND_OP_COND;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR;
+ sdio_claim_host(func);
+ status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+ sdio_release_host(func);
+ if (status != 0) {
+ printk("%s(): The 1st CMD5 failed.", __func__);
+ return -1;
+ }
+ cmd.opcode = SD_IO_SEND_OP_COND;
+ cmd.arg = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34|MMC_VDD_34_35;
+ cmd.flags = MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR;
+ sdio_claim_host(func);
+ status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+ sdio_release_host(func);
+ if (status != 0) {
+ printk("%s(): The 2nd CMD5 failed.", __func__);
+ return -1;
+ }
+ cmd.opcode = SD_SEND_RELATIVE_ADDR;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
+ sdio_claim_host(func);
+ status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+ sdio_release_host(func);
+ if (status == 0) {
+ func->card->rca = cmd.resp[0] >> 16;
+ } else {
+ printk("%s(): CMD3 failed.", __func__);
+ return -1;
+ }
+ cmd.opcode = MMC_SELECT_CARD;
+ cmd.arg = func->card->rca << 16;
+ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
+ sdio_claim_host(func);
+ status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+ sdio_release_host(func);
+ if (status != 0) {
+ printk("%s(): CMD7 failed.", __func__);
+ return -1;
+ }
+ return 0;
+}
+static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,
+ struct sdio_func *func, struct ssv6xxx_sdio_glue *glue)
+{
+ int err_ret;
+ struct mmc_host *host;
+ if (IS_GLUE_INVALID(glue)) {
+ printk("%s(): glue is invalid.\n", __func__);
+ return;
+ }
+ sdio_claim_host(func);
+ sdio_f0_writeb(func, 0x08, SDIO_CCCR_ABORT, &err_ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, err_ret);
+ err_ret = ssv6xxx_do_sdio_init_seq_5537(func);
+ CHECK_IO_RET(glue, err_ret);
+ sdio_claim_host(func);
+ host = func->card->host;
+ host->ios.bus_width = MMC_BUS_WIDTH_4;
+ host->ops->set_ios(host, &host->ios);
+ mdelay(20);
+ sdio_release_host(func);
+ sdio_claim_host(func);
+ sdio_f0_writeb(func, SDIO_BUS_WIDTH_4BIT, SDIO_CCCR_IF, &err_ret);
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, err_ret);
+ ssv6xxx_sdio_power_on(pwlan_data, func);
+ ssv6xxx_sdio_read_parameter(func, glue);
+}
+static void ssv6xxx_sdio_direct_int_mux_mode(struct ssv6xxx_sdio_glue *glue, bool enable)
+{
+ int err_ret = (-1);
+ struct sdio_func *func;
+ u8 host_cfg;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ if (glue != NULL) {
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ host_cfg = sdio_readb(func, MCU_NOTIFY_HOST_CFG, &err_ret);
+ if (err_ret == 0) {
+ if (!enable) {
+ host_cfg &= ~(0x04);
+ sdio_writeb(func, host_cfg, MCU_NOTIFY_HOST_CFG, &err_ret);
+ } else {
+ host_cfg |= (0x04);
+ sdio_writeb(func, host_cfg, MCU_NOTIFY_HOST_CFG, &err_ret);
+ }
+ }
+ sdio_release_host(func);
+ CHECK_IO_RET(glue, err_ret);
+ }
+}
+static int ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+{
+ int ret;
+ if (pdata->is_enabled == false)
+ return 0;
+ printk("ssv6xxx_sdio_power_off\n");
+ sdio_claim_host(func);
+ ret = sdio_disable_func(func);
+ sdio_release_host(func);
+ if (ret)
+ return ret;
+ pdata->is_enabled = false;
+ return ret;
+}
+static void _read_chip_id (struct ssv6xxx_sdio_glue *glue)
+{
+ u32 regval;
+ int ret;
+ u8 _chip_id[SSV6XXX_CHIP_ID_LENGTH];
+ u8 *c = _chip_id;
+ int i = 0;
+ ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_3, ®val);
+ *((u32 *)&_chip_id[0]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_2, ®val);
+ *((u32 *)&_chip_id[4]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_1, ®val);
+ *((u32 *)&_chip_id[8]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_0, ®val);
+ *((u32 *)&_chip_id[12]) = __be32_to_cpu(regval);
+ _chip_id[12+sizeof(u32)] = 0;
+ while (*c == 0) {
+ i++;
+ c++;
+ if (i == 16) {
+ c = _chip_id;
+ break;
+ }
+ }
+ if (*c != 0) {
+ strncpy(glue->tmp_data.chip_id, c, SSV6XXX_CHIP_ID_LENGTH);
+ dev_info(glue->dev, "CHIP ID: %s \n", glue->tmp_data.chip_id);
+ strncpy(glue->tmp_data.short_chip_id, c, SSV6XXX_CHIP_ID_SHORT_LENGTH);
+ glue->tmp_data.short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH] = 0;
+ } else {
+ dev_err(glue->dev, "Failed to read chip ID");
+ glue->tmp_data.chip_id[0] = 0;
+ }
+ if ( strstr(glue->tmp_data.chip_id, SSV6051_CHIP)
+ || strstr(glue->tmp_data.chip_id, SSV6051_CHIP_ECO3)) {
+ struct ssv6xxx_platform_data *pwlan_data;
+ pwlan_data = &glue->tmp_data;
+ pwlan_data->ops->safe_readreg = ssv6xxx_sdio_read_reg;
+ pwlan_data->ops->safe_writereg = ssv6xxx_sdio_write_reg;
+ printk("SWAP ops for 6051\n");
+ }
+}
+#if (defined(CONFIG_SSV_SDIO_INPUT_DELAY) && defined(CONFIG_SSV_SDIO_OUTPUT_DELAY))
+static void ssv6xxx_sdio_delay_chain(struct sdio_func *func, u32 input_delay, u32 output_delay)
+{
+ u8 in_delay, out_delay;
+ u8 delay[4];
+ int ret = 0, i = 0;
+ if ((input_delay == 0) && (output_delay == 0))
+ return;
+ for (i = 0; i < 4; i++) {
+ delay[i] = 0;
+ in_delay = (input_delay >> ( i * 8 )) & 0xff;
+ out_delay = (output_delay >> ( i * 8 )) & 0xff;
+ if (in_delay == SDIO_DELAY_LEVEL_OFF)
+ delay[i] |= (1 << SDIO_INPUT_DELAY_SFT);
+ else
+ delay[i] |= ((in_delay-1) << SDIO_INPUT_DELAY_LEVEL_SFT);
+ if (out_delay == SDIO_DELAY_LEVEL_OFF)
+ delay[i] |= (1 << SDIO_OUTPUT_DELAY_SFT);
+ else
+ delay[i] |= ((out_delay-1) << SDIO_OUTPUT_DELAY_LEVEL_SFT);
+ }
+ printk("%s: delay chain data0[%02x], data1[%02x], data2[%02x], data3[%02x]\n",
+ __FUNCTION__, delay[0], delay[1], delay[2], delay[3]);
+ sdio_claim_host(func);
+ sdio_writeb(func, delay[0], REG_SDIO_DAT0_DELAY, &ret);
+ sdio_writeb(func, delay[1], REG_SDIO_DAT1_DELAY, &ret);
+ sdio_writeb(func, delay[2], REG_SDIO_DAT2_DELAY, &ret);
+ sdio_writeb(func, delay[3], REG_SDIO_DAT3_DELAY, &ret);
+ sdio_release_host(func);
+}
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+int __devinit tu_ssv6xxx_sdio_probe(struct sdio_func *func,
+ const struct sdio_device_id *id)
+#else
+int tu_ssv6xxx_sdio_probe(struct sdio_func *func,
+ const struct sdio_device_id *id)
+#endif
+{
+ struct ssv6xxx_platform_data *pwlan_data;
+ struct ssv6xxx_sdio_glue *glue;
+ int ret = -ENOMEM;
+ dev_info(&func->dev, "Probing SDIO bus");
+ if (func->num != 0x01)
+ return -ENODEV;
+ glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+ if (!glue) {
+ dev_err(&func->dev, "can't allocate glue");
+ goto out;
+ }
+#if (defined(CONFIG_SSV_SDIO_INPUT_DELAY) && defined(CONFIG_SSV_SDIO_OUTPUT_DELAY))
+ ssv6xxx_sdio_delay_chain(func, CONFIG_SSV_SDIO_INPUT_DELAY, CONFIG_SSV_SDIO_OUTPUT_DELAY);
+#endif
+ ssv6xxx_low_sdio_clk(func);
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+ glue->dmaSkb=__dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
+#endif
+ pwlan_data = &glue->tmp_data;
+ memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+ atomic_set(&pwlan_data->irq_handling, 0);
+ glue->dev = &func->dev;
+ func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+ glue->dev_ready = true;
+ pwlan_data->vendor = func->vendor;
+ pwlan_data->device = func->device;
+ dev_info(glue->dev, "vendor = 0x%x device = 0x%x",
+ pwlan_data->vendor, pwlan_data->device);
+#ifdef CONFIG_PCIEASPM
+ cabrio_sdio_pm_check(func);
+#endif
+ pwlan_data->ops = &sdio_ops;
+ sdio_set_drvdata(func, glue);
+#ifdef CONFIG_PM
+ ssv6xxx_do_sdio_wakeup(func);
+#endif
+ ssv6xxx_sdio_power_on(pwlan_data, func);
+ ssv6xxx_sdio_read_parameter(func, glue);
+ ssv6xxx_do_sdio_reset_reinit(pwlan_data, func, glue);
+ ssv6xxx_sdio_direct_int_mux_mode(glue, false);
+ _read_chip_id(glue);
+ glue->core = platform_device_alloc(pwlan_data->short_chip_id, -1);
+ if (!glue->core) {
+ dev_err(glue->dev, "can't allocate platform_device");
+ ret = -ENOMEM;
+ goto out_free_glue;
+ }
+ glue->core->dev.parent = &func->dev;
+ ret = platform_device_add_data(glue->core, pwlan_data,
+ sizeof(*pwlan_data));
+ if (ret) {
+ dev_err(glue->dev, "can't add platform data\n");
+ goto out_dev_put;
+ }
+ glue->p_wlan_data = glue->core->dev.platform_data;
+ ret = platform_device_add(glue->core);
+ if (ret) {
+ dev_err(glue->dev, "can't add platform device\n");
+ goto out_dev_put;
+ }
+ ssv6xxx_sdio_irq_setmask(&glue->core->dev,0xff);
+#if 0
+ ssv6xxx_sdio_irq_enable(&glue->core->dev);
+#else
+#endif
+#if 0
+ glue->dev->platform_data = (void *)pwlan_data;
+ ret = tu_ssv6xxx_dev_probe(glue->dev);
+ if (ret) {
+ dev_err(glue->dev, "failed to initial ssv6xxx device !!\n");
+ platform_device_del(glue->core);
+ goto out_dev_put;
+ }
+#endif
+ return 0;
+out_dev_put:
+ platform_device_put(glue->core);
+out_free_glue:
+ if (glue != NULL)
+ kfree(glue);
+out:
+ return ret;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_probe);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+void __devexit tu_ssv6xxx_sdio_remove(struct sdio_func *func)
+#else
+void tu_ssv6xxx_sdio_remove(struct sdio_func *func)
+#endif
+{
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ printk("tu_ssv6xxx_sdio_remove..........\n");
+ if ( glue ) {
+ printk("tu_ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
+ ssv6xxx_sdio_irq_disable(&glue->core->dev,false);
+ glue->dev_ready = false;
+#if 0
+ tu_ssv6xxx_dev_remove(glue->dev);
+#endif
+ ssv6xxx_low_sdio_clk(func);
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+ if(glue->dmaSkb != NULL)
+ dev_kfree_skb(glue->dmaSkb);
+#endif
+ printk("tu_ssv6xxx_sdio_remove - disable mask\n");
+ ssv6xxx_sdio_irq_setmask(&glue->core->dev,0xff);
+ ssv6xxx_sdio_power_off(glue->p_wlan_data, func);
+ printk("platform_device_del \n");
+ platform_device_del(glue->core);
+ printk("platform_device_put \n");
+ platform_device_put(glue->core);
+ kfree(glue);
+ }
+ sdio_set_drvdata(func, NULL);
+ printk("tu_ssv6xxx_sdio_remove leave..........\n");
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_remove);
+
+#ifdef CONFIG_PM
+int tu_ssv6xxx_sdio_suspend(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
+ int ret = 0;
+ dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
+ sdio_func_id(func), flags);
+ ssv6xxx_low_sdio_clk(func);
+ glue->p_wlan_data->suspend(glue->p_wlan_data->pm_param);
+ if (!(flags & MMC_PM_KEEP_POWER)) {
+ dev_err(dev, "%s: cannot remain alive while host is suspended\n",
+ sdio_func_id(func));
+ }
+ ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+ if (ret)
+ return ret;
+#if 0
+ if (softc->wow_enabled) {
+ sdio_flags = sdio_get_host_pm_caps(func);
+ if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
+ dev_err(dev, "can't keep power while host "
+ "is suspended\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+ if (ret) {
+ dev_err(dev, "error while trying to keep power\n");
+ goto out;
+ }
+ } else {
+ ssv6xxx_sdio_irq_disable(&glue->core->dev,true);
+ }
+#endif
+ return ret;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_suspend);
+
+int tu_ssv6xxx_sdio_resume(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ dev_info(dev, "%s: resume.\n", __FUNCTION__);
+ if (!glue)
+ return 0;
+ glue->p_wlan_data->resume(glue->p_wlan_data->pm_param);
+ return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_resume);
+
+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
+ .suspend = tu_ssv6xxx_sdio_suspend,
+ .resume = tu_ssv6xxx_sdio_resume,
+};
+#endif
+struct sdio_driver tu_ssv6xxx_sdio_driver = {
+ .name = "TU_SSV6XXX_SDIO",
+ .id_table = ssv6xxx_sdio_devices,
+ .probe = tu_ssv6xxx_sdio_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+ .remove = __devexit_p(tu_ssv6xxx_sdio_remove),
+#else
+ .remove = tu_ssv6xxx_sdio_remove,
+#endif
+#ifdef CONFIG_PM
+ .drv = {
+ .pm = &ssv6xxx_sdio_pm_ops,
+ },
+#endif
+};
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_driver);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_sdio_init(void)
+#else
+static int __init tu_ssv6xxx_sdio_init(void)
+#endif
+{
+ printk(KERN_INFO "tu_ssv6xxx_sdio_init, probe @%p\n", tu_ssv6xxx_sdio_driver.probe);
+ return sdio_register_driver(&tu_ssv6xxx_sdio_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssv6xxx_sdio_exit(void)
+#else
+static void __exit tu_ssv6xxx_sdio_exit(void)
+#endif
+{
+ printk(KERN_INFO "tu_ssv6xxx_sdio_exit\n");
+ sdio_unregister_driver(&tu_ssv6xxx_sdio_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_init);
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_exit);
+#else
+module_init(tu_ssv6xxx_sdio_init);
+module_exit(tu_ssv6xxx_sdio_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h
new file mode 100644
index 000000000..907c6ace1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SDIO_H_
+#define _SDIO_H_
+int tu_ssv6xxx_sdio_init(void);
+void tu_ssv6xxx_sdio_exit(void);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h
new file mode 100644
index 000000000..ade196765
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SDIO_DEF_H_
+#define _SDIO_DEF_H_
+#include
+#define BASE_SDIO 0
+#define SD_REG_BASE 0xc0000800
+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
+#define REG_INT_MASK (BASE_SDIO + 0x04)
+#define REG_INT_STATUS (BASE_SDIO + 0x08)
+#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
+#define REG_SD_READY_FLAG (BASE_SDIO + 0x0f)
+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
+#define MCU_NOTIFY_HOST_CFG (BASE_SDIO + 0x56)
+#define REG_SDIO_DAT3_DELAY (BASE_SDIO + 0x59)
+#define REG_SDIO_DAT2_DELAY (BASE_SDIO + 0x5a)
+#define REG_SDIO_DAT1_DELAY (BASE_SDIO + 0x5b)
+#define REG_SDIO_DAT0_DELAY (BASE_SDIO + 0x5c)
+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
+#if 0
+#define SDIO_TX_ALLOC_SUCCESS 0x01
+#define SDIO_TX_NO_ALLOC 0x02
+#define SDIO_TX_DULPICATE_ALLOC 0x04
+#define SDIO_TX_TX_DONE 0x08
+#define SDIO_TX_AHB_HANG 0x10
+#define SDIO_TX_MB_FULL 0x80
+#define SDIO_HCI_IN_QUEUE_EMPTY 0x04
+#define SDIO_EDCA0_SHIFT 4
+#define SDIO_TX_ALLOC_SIZE_SHIFT 0x07
+#define SDIO_TX_ALLOC_ENABLE 0x10
+#endif
+#define SDIO_DEF_BLOCK_SIZE 0x80
+#if (SDIO_DEF_BLOCK_SIZE % 8)
+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_OUTPUT_TIMING 0
+#define SDIO_DEF_BLOCK_MODE_THRD 128
+#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_FORCE_BLOCK_MODE 0
+#define MAX_SCATTER_ENTRIES_PER_REQ 8
+struct sdio_scatter_item {
+ u8 *buf;
+ int len;
+};
+struct sdio_scatter_req {
+ u32 req;
+ u32 len;
+ int scat_entries;
+ struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
+ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+};
+#define SDIO_READ 0x00000001
+#define SDIO_WRITE 0x00000002
+#define CMD53_ARG_READ 0
+#define CMD53_ARG_WRITE 1
+#define CMD53_ARG_BLOCK_BASIS 1
+#define CMD53_ARG_FIXED_ADDRESS 0
+#define CMD53_ARG_INCR_ADDRESS 1
+
+
+#if defined(CONFIG_FW_ALIGNMENT_CHECK)
+#define SDIO_DMA_BUFFER_LEN 2048
+#endif
+#ifdef CONFIG_PM
+#define SDIO_COMMAND_BUFFER_LEN 256
+#endif
+#define IO_REG_BURST_RD_PORT_REG 0x10080
+#define IO_REG_BURST_WR_PORT_REG 0x10040
+#define MAX_BURST_READ_REG_AMOUNT 2
+#define MAX_BURST_WRITE_REG_AMOUNT 2
+#define SDIO_INPUT_DELAY_MSK 0x04
+#define SDIO_INPUT_DELAY_SFT 2
+#define SDIO_INPUT_DELAY_LEVEL_MSK 0x03
+#define SDIO_INPUT_DELAY_LEVEL_SFT 0
+#define SDIO_OUTPUT_DELAY_MSK 0x40
+#define SDIO_OUTPUT_DELAY_SFT 6
+#define SDIO_OUTPUT_DELAY_LEVEL_MSK 0x30
+#define SDIO_OUTPUT_DELAY_LEVEL_SFT 4
+#define SDIO_DELAY_LEVEL_OFF 0
+#define SDIO_DELAY_LEVEL_0 1
+#define SDIO_DELAY_LEVEL_1 2
+#define SDIO_DELAY_LEVEL_2 3
+#define SDIO_DELAY_LEVEL_3 4
+#define SDIO_READY_FLAG_BUSY 0x0
+#define SDIO_READY_FLAG_IDLE 0x2
+#define SDIO_READY_FLAG_BUSY_THRESHOLD 10000
+#define SDIO_READY_FLAG_BUSY_DELAY 5
+#define PLATFORM_DEF_DMA_ALIGN_SIZE 32
+#define PLATFORM_DMA_ALIGNED __attribute__ ((aligned(PLATFORM_DEF_DMA_ALIGN_SIZE)))
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile b/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile
new file mode 100755
index 000000000..36a3019c8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile
@@ -0,0 +1,21 @@
+ifeq ($(KBUILD_TOP),)
+ ifneq ($(KBUILD_EXTMOD),)
+ KBUILD_DIR := $(KBUILD_EXTMOD)
+ else
+ KBUILD_DIR := $(PWD)
+ endif
+KBUILD_TOP := $(KBUILD_DIR)/../../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssv6200smac/Module.symvers
+ifeq ($(DRV_OPT), HUW_DRV)
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci_wrapper/Module.symvers
+endif
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+KMODULE_NAME=ssv6200_usb
+KERN_SRCS := usb.c
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c
new file mode 100644
index 000000000..d61118d0b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c
@@ -0,0 +1,926 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#include
+#else
+#include
+#endif
+#include
+#include
+#include "usb.h"
+#include
+#define USB_SSV_VENDOR_ID 0x8065
+#define USB_SSV_PRODUCT_ID 0x6000
+#define TRANSACTION_TIMEOUT (3000)
+#define SSV6XXX_MAX_TXCMDSZ (sizeof(struct ssv6xxx_cmd_hdr))
+#define SSV6XXX_MAX_RXCMDSZ (sizeof(struct ssv6xxx_cmd_hdr))
+#define SSV6XXX_CMD_HEADER_SIZE (sizeof(struct ssv6xxx_cmd_hdr) - sizeof(union ssv6xxx_payload))
+#define USB_CMD_SEQUENCE 255
+#define MAX_RETRY_SSV6XXX_ALLOC_BUF 3
+#define IS_GLUE_INVALID(glue) \
+ ( (glue == NULL) \
+ || (glue->dev_ready == false) \
+ || ( (glue->p_wlan_data != NULL) \
+ && (glue->p_wlan_data->is_enabled == false)) \
+ )
+static const struct usb_device_id ssv_usb_table[] = {
+ { USB_DEVICE(USB_SSV_VENDOR_ID, USB_SSV_PRODUCT_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(usb, ssv_usb_table);
+extern int ssv_rx_nr_recvbuff;
+extern int ssv_rx_use_wq;
+struct ssv6xxx_usb_glue {
+ struct device *dev;
+ struct platform_device *core;
+ struct usb_device *udev;
+ struct usb_interface *interface;
+ struct ssv6xxx_platform_data *p_wlan_data;
+ struct ssv6xxx_platform_data tmp_data;
+ struct ssv6xxx_cmd_endpoint cmd_endpoint;
+ struct ssv6xxx_cmd_endpoint rsp_endpoint;
+ struct ssv6xxx_tx_endpoint tx_endpoint;
+ struct ssv6xxx_rx_endpoint rx_endpoint;
+ struct ssv6xxx_rx_buf ssv_rx_buf[MAX_NR_RECVBUFF];
+ struct ssv6xxx_queue ssv_rx_queue;
+ struct kref kref;
+ struct mutex io_mutex;
+ struct mutex cmd_mutex;
+ u16 sequence;
+ u16 err_cnt;
+ bool dev_ready;
+ struct workqueue_struct *wq;
+ struct ssv6xxx_usb_work_struct rx_work;
+ struct tasklet_struct rx_tasklet;
+ u32 *rx_pkt;
+ void *rx_cb_args;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ int (*rx_cb)(struct sk_buff_head *rxq, void *args);
+#else
+ int (*rx_cb)(struct sk_buff *rx_skb, void *args);
+#endif
+ int (*is_rx_q_full)(void *);
+};
+static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf);
+#define to_ssv6xxx_usb_dev(d) container_of(d, struct ssv6xxx_usb_glue, kref)
+static struct usb_driver ssv_usb_driver;
+#if 0
+static void ssv6xxx_dump_tx_desc(const u8 *buf)
+{
+ struct ssv6200_tx_desc *tx_desc;
+ tx_desc = (struct ssv6200_tx_desc *)buf;
+ printk(">> Tx Frame:\n");
+ printk("length: %d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, sec=%d\n",
+ tx_desc->len, tx_desc->c_type, tx_desc->f80211, tx_desc->qos, tx_desc->ht,
+ tx_desc->use_4addr, tx_desc->security);
+ printk("more_data=%d, sub_type=%x, extra_info=%d\n", tx_desc->more_data,
+ tx_desc->stype_b5b4, tx_desc->extra_info);
+ printk("fcmd=0x%08x, hdr_offset=%d, frag=%d, unicast=%d, hdr_len=%d\n",
+ tx_desc->fCmd, tx_desc->hdr_offset, tx_desc->frag, tx_desc->unicast,
+ tx_desc->hdr_len);
+ printk("tx_burst=%d, ack_policy=%d, do_rts_cts=%d, reason=%d, payload_offset=%d\n",
+ tx_desc->tx_burst, tx_desc->ack_policy, tx_desc->do_rts_cts,
+ tx_desc->reason, tx_desc->payload_offset);
+ printk("fcmdidx=%d, wsid=%d, txq_idx=%d\n",
+ tx_desc->fCmdIdx, tx_desc->wsid, tx_desc->txq_idx);
+ printk("RTS/CTS Nav=%d, frame_time=%d, crate_idx=%d, drate_idx=%d, dl_len=%d\n",
+ tx_desc->rts_cts_nav, tx_desc->frame_consume_time, tx_desc->crate_idx, tx_desc->drate_idx,
+ tx_desc->dl_length);
+ printk("\n\n\n");
+}
+#endif
+#if 0
+static void ssv6xxx_dump_rx_desc(const u8 *buf)
+{
+ struct ssv6200_rx_desc *rx_desc;
+ rx_desc = (struct ssv6200_rx_desc *)buf;
+ printk(">> RX Descriptor:\n");
+ printk("len=%d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, l3cs_err=%d, l4_cs_err=%d\n",
+ rx_desc->len, rx_desc->c_type, rx_desc->f80211, rx_desc->qos, rx_desc->ht, rx_desc->use_4addr,
+ rx_desc->l3cs_err, rx_desc->l4cs_err);
+ printk("align2=%d, psm=%d, stype_b5b4=%d, extra_info=%d\n",
+ rx_desc->align2, rx_desc->psm, rx_desc->stype_b5b4, rx_desc->extra_info);
+ printk("hdr_offset=%d, reason=%d, rx_result=%d\n", rx_desc->hdr_offset,
+ rx_desc->reason, rx_desc->RxResult);
+ printk("\n\n\n");
+}
+#endif
+static u16 ssv6xxx_get_cmd_sequence(struct ssv6xxx_usb_glue *glue)
+{
+ glue->sequence = glue->sequence % USB_CMD_SEQUENCE;
+ (glue->sequence)++;
+ return glue->sequence;
+}
+static void ssv6xxx_usb_delete(struct kref *kref)
+{
+ struct ssv6xxx_usb_glue *glue = to_ssv6xxx_usb_dev(kref);
+ int i;
+ for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+ usb_kill_urb(glue->ssv_rx_buf[i].rx_urb);
+ }
+ if (glue->cmd_endpoint.buff)
+ kfree(glue->cmd_endpoint.buff);
+ if (glue->rsp_endpoint.buff)
+ kfree(glue->rsp_endpoint.buff);
+ if (glue->ssv_rx_buf[0].rx_buf) {
+ for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+ usb_free_coherent(glue->udev, MAX_HCI_RX_AGGR_SIZE,
+ glue->ssv_rx_buf[i].rx_buf,
+ glue->ssv_rx_buf[i].rx_urb->transfer_dma);
+ usb_free_urb(glue->ssv_rx_buf[i].rx_urb);
+ }
+ }
+ if (ssv_rx_use_wq) {
+ destroy_workqueue(glue->wq);
+ } else {
+ tasklet_kill(&glue->rx_tasklet);
+ }
+ usb_put_dev(glue->udev);
+ kfree(glue);
+}
+static int ssv6xxx_usb_recv_rsp(struct ssv6xxx_usb_glue *glue, int size, int *rsp_len)
+{
+ int retval = 0, foolen = 0;
+ if (!glue || !glue->interface) {
+ retval = -ENODEV;
+ return retval;
+ }
+ retval = usb_bulk_msg(glue->udev,
+ usb_rcvbulkpipe(glue->udev, glue->rsp_endpoint.address),
+ glue->rsp_endpoint.buff, size,
+ &foolen, TRANSACTION_TIMEOUT);
+ if (retval) {
+ *rsp_len = 0;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot receive response, error=%d\n", retval);
+ } else {
+ *rsp_len = foolen;
+ glue->err_cnt = 0;
+ }
+ return retval;
+}
+static int ssv6xxx_usb_send_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, u16 seq, const void *data, u32 data_len)
+{
+ int retval = 0, foolen = 0;
+ struct ssv6xxx_cmd_hdr *hdr;
+ if (!glue || !glue->interface) {
+ retval = -ENODEV;
+ return retval;
+ }
+ hdr = (struct ssv6xxx_cmd_hdr *)glue->cmd_endpoint.buff;
+ memset(hdr, 0, sizeof(struct ssv6xxx_cmd_hdr));
+ hdr->plen = (data_len >> (0))& 0xff;
+ hdr->cmd = cmd;
+ hdr->seq = cpu_to_le16(seq);
+ memcpy(&hdr->payload, data, data_len);
+ retval = usb_bulk_msg(glue->udev,
+ usb_sndbulkpipe(glue->udev, glue->cmd_endpoint.address),
+ glue->cmd_endpoint.buff, (data_len+SSV6XXX_CMD_HEADER_SIZE),
+ &foolen, TRANSACTION_TIMEOUT);
+ if (retval) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot send cmd data, error=%d\n", retval);
+ } else {
+ glue->err_cnt = 0;
+ }
+ return retval;
+}
+static int ssv6xxx_usb_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, void *data, u32 data_len, void *result)
+{
+ int retval = (-1), rsp_len = 0, i = 0;
+ struct ssv6xxx_cmd_hdr *rsphdr;
+ u16 sequence;
+ mutex_lock(&glue->cmd_mutex);
+ sequence = ssv6xxx_get_cmd_sequence(glue);
+ retval = ssv6xxx_usb_send_cmd(glue, cmd, sequence, data, data_len);
+ if (retval) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to send cmd, sequence=%d, retval=%d\n",
+ __FUNCTION__, sequence, retval);
+ goto exit;
+ }
+ for (i = 0; i < USB_CMD_SEQUENCE; i++) {
+ retval = ssv6xxx_usb_recv_rsp(glue, SSV6XXX_MAX_RXCMDSZ, &rsp_len);
+ if (retval) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to receive response, sequence=%d, retval=%d\n",
+ __FUNCTION__, sequence, retval);
+ goto exit;
+ }
+ if (rsp_len < SSV6XXX_CMD_HEADER_SIZE) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Receviced abnormal response length[%d]\n", rsp_len);
+ goto exit;
+ }
+ rsphdr = (struct ssv6xxx_cmd_hdr *)glue->rsp_endpoint.buff;
+ if (sequence == rsphdr->seq)
+ break;
+ else
+ HWIF_DBG_PRINT(glue->p_wlan_data, "received incorrect sequence=%d[%d]\n", sequence, rsphdr->seq);
+ }
+ switch (rsphdr->cmd) {
+ case SSV6200_CMD_WRITE_REG:
+ break;
+ case SSV6200_CMD_READ_REG:
+ if (result)
+ memcpy(result, &rsphdr->payload, sizeof(struct ssv6xxx_read_reg_result));
+ break;
+ default:
+ retval = -1;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: unknown response cmd[%d]\n", __FUNCTION__, rsphdr->cmd);
+ break;
+ }
+exit:
+ mutex_unlock(&glue->cmd_mutex);
+ return retval;
+}
+static void ssv6xxx_usb_recv_rx_work(struct work_struct *work)
+{
+ struct ssv6xxx_usb_glue *glue = ((struct ssv6xxx_usb_work_struct *)work)->glue;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ struct ssv6xxx_rx_buf *ssv_rx_buf;
+ unsigned char *data;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ while (NULL != (ssv_rx_buf = (struct ssv6xxx_rx_buf *)ssv6xxx_dequeue_list_node(&glue->ssv_rx_queue))) {
+ if (glue->is_rx_q_full(glue->rx_cb_args)) {
+ ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+ queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+ break;
+ }
+ (*glue->rx_pkt)++;
+ rx_mpdu = glue->p_wlan_data->skb_alloc(glue->p_wlan_data->skb_param, ssv_rx_buf->rx_filled,
+ GFP_KERNEL
+ );
+ if (rx_mpdu == NULL) {
+ ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+ queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+ break;
+ }
+ data = skb_put(rx_mpdu, ssv_rx_buf->rx_filled);
+ memcpy(data, ssv_rx_buf->rx_buf, ssv_rx_buf->rx_filled);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ glue->rx_cb(rx_mpdu, glue->rx_cb_args);
+#endif
+ ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ if (skb_queue_len(&rx_list)) {
+ glue->rx_cb(&rx_list, glue->rx_cb_args);
+ }
+#endif
+}
+static void ssv6xxx_usb_recv_rx_tasklet(unsigned long priv)
+{
+ struct ssv6xxx_usb_glue *glue = (struct ssv6xxx_usb_glue *)priv;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ struct ssv6xxx_rx_buf *ssv_rx_buf;
+ unsigned char *data;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ while (NULL != (ssv_rx_buf = (struct ssv6xxx_rx_buf *)ssv6xxx_dequeue_list_node(&glue->ssv_rx_queue))) {
+ if (glue->is_rx_q_full(glue->rx_cb_args)) {
+ ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+ tasklet_schedule(&glue->rx_tasklet);
+ break;
+ }
+ (*glue->rx_pkt)++;
+ rx_mpdu = glue->p_wlan_data->skb_alloc(glue->p_wlan_data->skb_param, ssv_rx_buf->rx_filled,
+ GFP_ATOMIC
+ );
+ if (rx_mpdu == NULL) {
+ ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+ tasklet_schedule(&glue->rx_tasklet);
+ break;
+ }
+ data = skb_put(rx_mpdu, ssv_rx_buf->rx_filled);
+ memcpy(data, ssv_rx_buf->rx_buf, ssv_rx_buf->rx_filled);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ glue->rx_cb(rx_mpdu, glue->rx_cb_args);
+#endif
+ ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ if (skb_queue_len(&rx_list)) {
+ glue->rx_cb(&rx_list, glue->rx_cb_args);
+ }
+#endif
+}
+static void ssv6xxx_usb_recv_rx_complete(struct urb *urb)
+{
+ struct ssv6xxx_rx_buf *ssv_rx_buf = (struct ssv6xxx_rx_buf *)urb->context;
+ struct ssv6xxx_usb_glue *glue = ssv_rx_buf->glue;
+ ssv_rx_buf->rx_res = urb->status;
+ if (urb->status) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "fail rx status received:%d\n", urb->status);
+ goto skip;
+ }
+ glue->err_cnt = 0;
+ ssv_rx_buf->rx_filled = urb->actual_length;
+ if (ssv_rx_buf->rx_filled > MAX_HCI_RX_AGGR_SIZE) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "recv invalid data length %d\n", ssv_rx_buf->rx_filled);
+ goto skip;
+ }
+ ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+ if (ssv_rx_use_wq) {
+ queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+ } else {
+ tasklet_schedule(&glue->rx_tasklet);
+ }
+ return;
+skip:
+ ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+}
+static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf)
+{
+ int size = MAX_HCI_RX_AGGR_SIZE;
+ int retval;
+ usb_fill_bulk_urb(ssv_rx_buf->rx_urb,
+ glue->udev, usb_rcvbulkpipe(glue->udev, glue->rx_endpoint.address),
+ ssv_rx_buf->rx_buf, size,
+ ssv6xxx_usb_recv_rx_complete, ssv_rx_buf);
+ ssv_rx_buf->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+ ssv_rx_buf->rx_filled = 0;
+ retval = usb_submit_urb(ssv_rx_buf->rx_urb, GFP_ATOMIC);
+ if (retval) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Fail to submit rx urb, error=%d\n", retval);
+ }
+}
+static int __must_check ssv6xxx_usb_read(struct device *child,
+ void *buf, size_t *size, int mode)
+{
+ *size = 0;
+ return 0;
+}
+static int ssv6xxx_usb_send_tx(struct ssv6xxx_usb_glue *glue, struct sk_buff *skb, size_t size)
+{
+ int foolen = 0, retval = 0;
+ int tx_len = size;
+ if ((tx_len % glue->tx_endpoint.packet_size) == 0) {
+ skb_put(skb, 1);
+ tx_len++;
+ }
+ retval = usb_bulk_msg(glue->udev,
+ usb_sndbulkpipe(glue->udev, glue->tx_endpoint.address),
+ skb->data, tx_len, &foolen, TRANSACTION_TIMEOUT);
+ if (retval)
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot send tx data, retval=%d\n", retval);
+ return retval;
+}
+static int __must_check ssv6xxx_usb_write(struct device *child,
+ void *buf, size_t len, u8 queue_num)
+{
+ int retval = (-1);
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue))
+ return retval;
+ if ((retval = ssv6xxx_usb_send_tx(glue, (struct sk_buff *)buf, len)) < 0) {
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to send tx data\n", __FUNCTION__);
+ } else {
+ glue->err_cnt = 0;
+ }
+ return retval;
+}
+static int __must_check __ssv6xxx_usb_read_reg(struct ssv6xxx_usb_glue *glue, u32 addr,
+ u32 *buf)
+{
+ int retval = (-1);
+ struct ssv6xxx_read_reg read_reg;
+ struct ssv6xxx_read_reg_result result;
+ if (IS_GLUE_INVALID(glue))
+ return retval;
+ memset(&read_reg, 0, sizeof(struct ssv6xxx_read_reg));
+ memset(&result, 0, sizeof(struct ssv6xxx_read_reg_result));
+ read_reg.addr = cpu_to_le32(addr);
+ retval = ssv6xxx_usb_cmd(glue, SSV6200_CMD_READ_REG, &read_reg, sizeof(struct ssv6xxx_read_reg), &result);
+ if (!retval)
+ *buf = le32_to_cpu(result.value);
+ else {
+ *buf = 0xffffffff;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register address %x\n", __FUNCTION__, addr);
+ }
+ return retval;
+}
+static int __must_check ssv6xxx_usb_read_reg(struct device *child, u32 addr,
+ u32 *buf)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ return __ssv6xxx_usb_read_reg(glue, addr, buf);
+}
+static int __must_check __ssv6xxx_usb_write_reg(struct ssv6xxx_usb_glue *glue, u32 addr,
+ u32 buf)
+{
+ int retval = (-1);
+ struct ssv6xxx_write_reg write_reg;
+ if (IS_GLUE_INVALID(glue))
+ return retval;
+ memset(&write_reg, 0, sizeof(struct ssv6xxx_write_reg));
+ write_reg.addr = cpu_to_le32(addr);
+ write_reg.value = cpu_to_le32(buf);
+ retval = ssv6xxx_usb_cmd(glue, SSV6200_CMD_WRITE_REG, &write_reg, sizeof(struct ssv6xxx_write_reg), NULL);
+ if (retval)
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register address %x, value %x\n", __FUNCTION__, addr, buf);
+ return retval;
+}
+static int __must_check ssv6xxx_usb_write_reg(struct device *child, u32 addr,
+ u32 buf)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ return __ssv6xxx_usb_write_reg(glue, addr, buf);
+}
+static int __must_check ssv6xxx_usb_burst_read_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = -1, i;
+ printk("%s(): Not support atomic burst register reading!\n", __func__);
+ WARN_ON(1);
+ for (i = 0 ; i < reg_amount ; i++) {
+ ret = ssv6xxx_usb_read_reg(child, addr[i], &buf[i]);
+ if (ret != 0) {
+ printk("%s(): read 0x%08x failed.\n", __func__, addr[i]);
+ }
+ }
+ return -EOPNOTSUPP;
+}
+static int __must_check ssv6xxx_usb_burst_write_reg(struct device *child, u32 *addr,
+ u32 *buf, u8 reg_amount)
+{
+ int ret = -1, i;
+ printk("%s(): Not support atomic burst register writing!\n", __func__);
+ WARN_ON(1);
+ for (i = 0 ; i < reg_amount ; i++) {
+ ret = ssv6xxx_usb_write_reg(child, addr[i], buf[i]);
+ if (ret != 0) {
+ printk("%s(): write 0x%08x failed.\n", __func__, addr[i]);
+ }
+ }
+ return -EOPNOTSUPP;
+}
+static int ssv6xxx_usb_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ u16 laddr, haddr;
+ u32 addr;
+ int retval = 0, max_usb_block = 512;
+ u8 *pdata;
+ int res_length, offset, send_length;
+ if (IS_GLUE_INVALID(glue))
+ return -1;
+ offset = 0;
+ pdata = data;
+ addr = start_addr;
+ res_length = data_length;
+ while (offset < data_length) {
+ int transfer = min_t(int, res_length, max_usb_block);
+ laddr = (addr & 0x0000ffff);
+ haddr = (addr >> 16);
+ send_length = usb_control_msg(glue->udev, usb_sndctrlpipe(glue->udev, 0),
+ FIRMWARE_DOWNLOAD, (USB_DIR_OUT | USB_TYPE_VENDOR),
+ laddr, haddr, pdata, transfer, TRANSACTION_TIMEOUT);
+ if (send_length < 0) {
+ retval = send_length;
+ HWIF_DBG_PRINT(glue->p_wlan_data, "Load Firmware Fail, retval=%d, sram=0x%08x\n", retval, (laddr|haddr));
+ break;
+ }
+ addr += transfer;
+ pdata += transfer;
+ offset += transfer;
+ res_length -= transfer;
+ }
+ return retval;
+}
+static int ssv6xxx_usb_property(struct device *child)
+{
+ return SSV_HWIF_CAPABILITY_POLLING | SSV_HWIF_INTERFACE_USB;
+}
+static int ssv6xxx_chk_usb_speed(struct ssv6xxx_usb_glue *glue)
+{
+ if (IS_GLUE_INVALID(glue)) {
+ return -1;
+ }
+ return glue->udev->speed;
+}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+static void ssv6xxx_usb_rx_task(struct device *child,
+ int (*rx_cb)(struct sk_buff_head *rxq, void *args),
+ int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#else
+static void ssv6xxx_usb_rx_task(struct device *child,
+ int (*rx_cb)(struct sk_buff *rx_skb, void *args),
+ int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#endif
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ int i;
+ int nr_recvbuff = (ssv_rx_nr_recvbuff > MAX_NR_RECVBUFF)?MAX_NR_RECVBUFF:((ssv_rx_nr_recvbuff < MIN_NR_RECVBUFF)?MIN_NR_RECVBUFF:ssv_rx_nr_recvbuff);
+ printk("%s: nr_recvbuff=%d\n", __func__, nr_recvbuff);
+ glue->rx_cb = rx_cb;
+ glue->rx_cb_args = args;
+ glue->is_rx_q_full = is_rx_q_full;
+ glue->rx_pkt = pkt;
+ for (i = 0 ; i < nr_recvbuff ; ++i) {
+ ssv6xxx_usb_recv_rx(glue, &(glue->ssv_rx_buf[i]));
+ }
+}
+static int ssv6xxx_usb_start_acc(struct device *child, u8 epnum)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue)) {
+ printk("failed to start usb acc of ep%d\n", epnum);
+ return -1;
+ }
+ if (ssv6xxx_chk_usb_speed(glue) == USB_SPEED_HIGH)
+ glue->p_wlan_data->enable_usb_acc(glue->p_wlan_data->usb_param, epnum);
+ return 0;
+}
+static int ssv6xxx_usb_stop_acc(struct device *child, u8 epnum)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue)) {
+ printk("failed to stop usb acc of ep%d\n", epnum);
+ return -1;
+ }
+ if (ssv6xxx_chk_usb_speed(glue) == USB_SPEED_HIGH)
+ glue->p_wlan_data->disable_usb_acc(glue->p_wlan_data->usb_param, epnum);
+ return 0;
+}
+static int ssv6xxx_usb_jump_to_rom(struct device *child)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ if (IS_GLUE_INVALID(glue)) {
+ printk("failed to jump to ROM\n");
+ return -1;
+ }
+ glue->p_wlan_data->jump_to_rom(glue->p_wlan_data->usb_param);
+ return 0;
+}
+static void ssv6xxx_usb_sysplf_reset(struct device *child, u32 addr, u32 value)
+{
+ struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+ int retval = (-1), rsp_len = 0;
+ u16 sequence;
+ struct ssv6xxx_write_reg write_reg;
+ if (IS_GLUE_INVALID(glue))
+ return;
+ mutex_lock(&glue->cmd_mutex);
+ sequence = ssv6xxx_get_cmd_sequence(glue);
+ memset(&write_reg, 0, sizeof(struct ssv6xxx_write_reg));
+ write_reg.addr = cpu_to_le32(addr);
+ write_reg.value = cpu_to_le32(value);
+ retval = ssv6xxx_usb_send_cmd(glue, SSV6200_CMD_WRITE_REG, sequence, &write_reg, sizeof(struct ssv6xxx_write_reg));
+ if (retval)
+ HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to reset sysplf\n", __FUNCTION__);
+ retval = ssv6xxx_usb_recv_rsp(glue, SSV6XXX_MAX_RXCMDSZ, &rsp_len);
+ mutex_unlock(&glue->cmd_mutex);
+}
+static struct ssv6xxx_hwif_ops usb_ops = {
+ .read = ssv6xxx_usb_read,
+ .write = ssv6xxx_usb_write,
+ .readreg = ssv6xxx_usb_read_reg,
+ .writereg = ssv6xxx_usb_write_reg,
+ .safe_readreg = ssv6xxx_usb_read_reg,
+ .safe_writereg = ssv6xxx_usb_write_reg,
+ .burst_readreg = ssv6xxx_usb_burst_read_reg,
+ .burst_writereg = ssv6xxx_usb_burst_write_reg,
+ .burst_safe_readreg = ssv6xxx_usb_burst_read_reg,
+ .burst_safe_writereg = ssv6xxx_usb_burst_write_reg,
+ .load_fw = ssv6xxx_usb_load_firmware,
+ .property = ssv6xxx_usb_property,
+ .hwif_rx_task = ssv6xxx_usb_rx_task,
+ .start_usb_acc = ssv6xxx_usb_start_acc,
+ .stop_usb_acc = ssv6xxx_usb_stop_acc,
+ .jump_to_rom = ssv6xxx_usb_jump_to_rom,
+ .sysplf_reset = ssv6xxx_usb_sysplf_reset,
+};
+static void ssv6xxx_usb_power_on(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+{
+ if (pdata->is_enabled == true)
+ return;
+ pdata->is_enabled = true;
+}
+static void ssv6xxx_usb_power_off(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+{
+ if (pdata->is_enabled == false)
+ return;
+ pdata->is_enabled = false;
+}
+static void _read_chip_id (struct ssv6xxx_usb_glue *glue)
+{
+ u32 regval;
+ int ret;
+ u8 _chip_id[SSV6XXX_CHIP_ID_LENGTH];
+ u8 *c = _chip_id;
+ int i = 0;
+ ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_3, ®val);
+ *((u32 *)&_chip_id[0]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_2, ®val);
+ *((u32 *)&_chip_id[4]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_1, ®val);
+ *((u32 *)&_chip_id[8]) = __be32_to_cpu(regval);
+ if (ret == 0)
+ ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_0, ®val);
+ *((u32 *)&_chip_id[12]) = __be32_to_cpu(regval);
+ _chip_id[12+sizeof(u32)] = 0;
+ while (*c == 0) {
+ i++;
+ c++;
+ if (i == 16) {
+ c = _chip_id;
+ break;
+ }
+ }
+ if (*c != 0) {
+ strncpy(glue->tmp_data.chip_id, c, SSV6XXX_CHIP_ID_LENGTH);
+ dev_info(glue->dev, "CHIP ID: %s \n", glue->tmp_data.chip_id);
+ strncpy(glue->tmp_data.short_chip_id, c, SSV6XXX_CHIP_ID_SHORT_LENGTH);
+ glue->tmp_data.short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH] = 0;
+ } else {
+ dev_err(glue->dev, "Failed to read chip ID");
+ glue->tmp_data.chip_id[0] = 0;
+ }
+}
+static int ssv_usb_probe(struct usb_interface *interface,
+ const struct usb_device_id *id)
+{
+ struct ssv6xxx_platform_data *pwlan_data;
+ struct ssv6xxx_usb_glue *glue;
+ struct usb_host_interface *iface_desc;
+ struct usb_endpoint_descriptor *endpoint;
+ int i, j;
+ int retval = -ENOMEM;
+ unsigned int epnum;
+ printk(KERN_INFO "=======================================\n");
+ printk(KERN_INFO "== TURISMO - USB ==\n");
+ printk(KERN_INFO "=======================================\n");
+ glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+ if (!glue) {
+ dev_err(&interface->dev, "Out of memory\n");
+ goto error;
+ }
+ glue->sequence = 0;
+ glue->err_cnt = 0;
+ kref_init(&glue->kref);
+ mutex_init(&glue->io_mutex);
+ mutex_init(&glue->cmd_mutex);
+ tu_ssv6xxx_init_queue(&glue->ssv_rx_queue);
+ if (ssv_rx_use_wq) {
+ glue->rx_work.glue = glue;
+ INIT_WORK((struct work_struct *)&glue->rx_work, ssv6xxx_usb_recv_rx_work);
+ glue->wq = create_singlethread_workqueue("ssv6xxx_usb_wq");
+ if (!glue->wq) {
+ dev_err(&interface->dev, "Could not allocate Work Queue\n");
+ goto error;
+ }
+ } else {
+ tasklet_init(&glue->rx_tasklet, ssv6xxx_usb_recv_rx_tasklet, (unsigned long)glue);
+ }
+ pwlan_data = &glue->tmp_data;
+ memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+ atomic_set(&pwlan_data->irq_handling, 0);
+ glue->dev = &interface->dev;
+ glue->udev = usb_get_dev(interface_to_usbdev(interface));
+ glue->interface = interface;
+ glue->dev_ready = true;
+ pwlan_data->vendor = id->idVendor;
+ pwlan_data->device = id->idProduct;
+ pwlan_data->ops = &usb_ops;
+ iface_desc = interface->cur_altsetting;
+ for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+ endpoint = &iface_desc->endpoint[i].desc;
+ epnum = endpoint->bEndpointAddress & 0x0f;
+ if (epnum == SSV_EP_CMD) {
+ glue->cmd_endpoint.address = endpoint->bEndpointAddress;
+ glue->cmd_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+ glue->cmd_endpoint.buff = kmalloc(SSV6XXX_MAX_TXCMDSZ, GFP_ATOMIC);
+ if (!glue->cmd_endpoint.buff) {
+ dev_err(&interface->dev, "Could not allocate cmd buffer\n");
+ goto error;
+ }
+ }
+ if (epnum == SSV_EP_RSP) {
+ glue->rsp_endpoint.address = endpoint->bEndpointAddress;
+ glue->rsp_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+ glue->rsp_endpoint.buff = kmalloc(SSV6XXX_MAX_RXCMDSZ, GFP_ATOMIC);
+ if (!glue->rsp_endpoint.buff) {
+ dev_err(&interface->dev, "Could not allocate rsp buffer\n");
+ goto error;
+ }
+ }
+ if (epnum == SSV_EP_TX) {
+ glue->tx_endpoint.address = endpoint->bEndpointAddress;
+ glue->tx_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+ }
+ if (epnum == SSV_EP_RX) {
+ glue->rx_endpoint.address = endpoint->bEndpointAddress;
+ glue->rx_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+ for (j = 0 ; j < MAX_NR_RECVBUFF ; ++j) {
+ glue->ssv_rx_buf[j].rx_urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!glue->ssv_rx_buf[j].rx_urb) {
+ dev_err(&interface->dev, "Could not allocate rx urb\n");
+ goto error;
+ }
+ glue->ssv_rx_buf[j].rx_buf = usb_alloc_coherent(
+ glue->udev, MAX_HCI_RX_AGGR_SIZE,
+ GFP_ATOMIC, &glue->ssv_rx_buf[j].rx_urb->transfer_dma);
+ if (!glue->ssv_rx_buf[j].rx_buf) {
+ dev_err(&interface->dev, "Could not allocate rx buffer\n");
+ goto error;
+ }
+ glue->ssv_rx_buf[j].glue = glue;
+ tu_ssv6xxx_init_list_node((struct ssv6xxx_list_node *)&glue->ssv_rx_buf[j]);
+ }
+ }
+ }
+ if (!(glue->cmd_endpoint.address &&
+ glue->rsp_endpoint.address &&
+ glue->tx_endpoint.address &&
+ glue->rx_endpoint.address)) {
+ dev_err(&interface->dev, "Could not find all endpoints\n");
+ goto error;
+ }
+ usb_set_intfdata(interface, glue);
+ ssv6xxx_usb_power_on(pwlan_data, interface);
+ _read_chip_id(glue);
+ glue->core = platform_device_alloc(pwlan_data->short_chip_id, -1);
+ if (!glue->core) {
+ dev_err(glue->dev, "can't allocate platform_device");
+ retval = -ENOMEM;
+ goto error;
+ }
+ glue->core->dev.parent = &interface->dev;
+ retval = platform_device_add_data(glue->core, pwlan_data, sizeof(*pwlan_data));
+ if (retval) {
+ dev_err(glue->dev, "can't add platform data\n");
+ goto out_dev_put;
+ }
+ glue->p_wlan_data = glue->core->dev.platform_data;
+ retval = platform_device_add(glue->core);
+ if (retval) {
+ dev_err(glue->dev, "can't add platform device\n");
+ goto out_dev_put;
+ }
+#ifdef SSV_SUPPORT_USB_LPM
+ printk("---------- USB LPM capability ---------- \n");
+ printk("device supports LPM: %d\n", glue->udev->lpm_capable);
+ printk("device can perform USB2 hardware LPM: %d\n", glue->udev->usb2_hw_lpm_capable);
+ printk("USB2 (Host) hardware LPM is enabled: %d\n", glue->udev->usb2_hw_lpm_enabled);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,12,2)
+ printk("Userspace allows USB 2.0 LPM to be enabled: %d\n", glue->udev->usb2_hw_lpm_allowed);
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,11,0)
+ printk("device can perform USB2 hardware BESL LPM: %d\n", glue->udev->usb2_hw_lpm_besl_capable);
+#endif
+ printk("----------------------------------------\n");
+#endif
+ return 0;
+out_dev_put:
+ platform_device_put(glue->core);
+error:
+ if (glue)
+ kref_put(&glue->kref, ssv6xxx_usb_delete);
+ return retval;
+}
+static void ssv_usb_disconnect(struct usb_interface *interface)
+{
+ struct ssv6xxx_usb_glue *glue;
+ glue = usb_get_intfdata(interface);
+ usb_set_intfdata(interface, NULL);
+ if (glue) {
+ glue->dev_ready = false;
+ ssv6xxx_usb_power_off(glue->p_wlan_data, interface);
+ printk("platform_device_del \n");
+ platform_device_del(glue->core);
+ printk("platform_device_put \n");
+ platform_device_put(glue->core);
+ }
+ mutex_lock(&glue->io_mutex);
+ glue->interface = NULL;
+ mutex_unlock(&glue->io_mutex);
+ kref_put(&glue->kref, ssv6xxx_usb_delete);
+ dev_info(&interface->dev, "SSV USB is disconnected");
+}
+#ifdef CONFIG_PM
+static int ssv_usb_suspend(struct usb_interface *interface, pm_message_t message)
+{
+ struct ssv6xxx_usb_glue *glue = usb_get_intfdata(interface);
+ int i;
+ dev_info(glue->dev, "%s(): suspend.\n", __FUNCTION__);
+ if (!glue)
+ return 0;
+ glue->p_wlan_data->suspend(glue->p_wlan_data->pm_param);
+ for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+ usb_kill_urb(glue->ssv_rx_buf[i].rx_urb);
+ }
+ return 0;
+}
+static int ssv_usb_resume(struct usb_interface *interface)
+{
+ struct ssv6xxx_usb_glue *glue = usb_get_intfdata(interface);
+ int i;
+ int nr_recvbuff = (ssv_rx_nr_recvbuff > MAX_NR_RECVBUFF)?MAX_NR_RECVBUFF:((ssv_rx_nr_recvbuff < MIN_NR_RECVBUFF)?MIN_NR_RECVBUFF:ssv_rx_nr_recvbuff);
+ dev_info(glue->dev, "%s(): resume.\n", __FUNCTION__);
+ if (!glue)
+ return 0;
+ for (i = 0 ; i < nr_recvbuff ; ++i) {
+ ssv6xxx_usb_recv_rx(glue, &(glue->ssv_rx_buf[i]));
+ }
+ glue->p_wlan_data->resume(glue->p_wlan_data->pm_param);
+ return 0;
+}
+#endif
+static struct usb_driver ssv_usb_driver = {
+ .name = "SSV6XXX_USB",
+ .probe = ssv_usb_probe,
+ .disconnect = ssv_usb_disconnect,
+#ifdef CONFIG_PM
+ .suspend = ssv_usb_suspend,
+ .resume = ssv_usb_resume,
+#endif
+ .id_table = ssv_usb_table,
+ .supports_autosuspend = 1,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
+ .disable_hub_initiated_lpm = 0,
+#endif
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv6xxx_usb_init(void)
+#else
+static int __init ssv6xxx_usb_init(void)
+#endif
+{
+ printk(KERN_INFO "ssv6xxx_usb_init\n");
+ return usb_register(&ssv_usb_driver);
+}
+static int ssv_usb_do_device_exit(struct device *d, void *arg)
+{
+ struct usb_interface *intf = to_usb_interface(d);
+ struct ssv6xxx_usb_glue *glue = usb_get_intfdata(intf);
+ u32 regval;
+ int ret;
+ if (glue != NULL) {
+ printk(KERN_INFO "ssv_usb_do_device_exit: JUMP to ROM\n");
+ ret = __ssv6xxx_usb_read_reg(glue, 0xc000001c, ®val);
+ if (__ssv6xxx_usb_write_reg(glue, 0xc000001c, (regval & 0xfeffffff)));
+ ret = __ssv6xxx_usb_read_reg(glue, 0xc00000ec, ®val);
+ if (__ssv6xxx_usb_write_reg(glue, 0xc00000ec, (regval & 0xffffefff)));
+ ret = __ssv6xxx_usb_read_reg(glue, 0xc00000e8, ®val);
+ if (__ssv6xxx_usb_write_reg(glue, 0xc00000e8, (regval | 0x00000004)));
+ ret = __ssv6xxx_usb_read_reg(glue, 0xc000001c, ®val);
+ if (__ssv6xxx_usb_write_reg(glue, 0xc000001c, (regval | 0x01000000)));
+ }
+ msleep(50);
+ return 0;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void ssv6xxx_usb_exit(void)
+#else
+static void __exit ssv6xxx_usb_exit(void)
+#endif
+{
+ if (driver_for_each_device(&ssv_usb_driver.drvwrap.driver, NULL,
+ NULL, ssv_usb_do_device_exit)) {};
+ printk(KERN_INFO "ssv6xxx_usb_exit\n");
+ usb_deregister(&ssv_usb_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(ssv6xxx_usb_init);
+EXPORT_SYMBOL(ssv6xxx_usb_exit);
+#else
+module_init(ssv6xxx_usb_init);
+module_exit(ssv6xxx_usb_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h
new file mode 100644
index 000000000..14fccf1c3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _USB_DEF_H_
+#define _USB_DEF_H_
+#include
+#define USB_DBG(fmt,...) pr_debug(fmt "\n", ##__VA_ARGS__)
+#define FW_START_ADDR 0x00
+#define FIRMWARE_DOWNLOAD 0xf0
+#define SSV_EP_CMD 0x01
+#define SSV_EP_RSP 0x02
+#define SSV_EP_TX 0x03
+#define SSV_EP_RX 0x04
+#define SSV6200_CMD_WRITE_REG 0x01
+#define SSV6200_CMD_READ_REG 0x02
+struct ssv6xxx_read_reg_result {
+ u32 value;
+} __attribute__ ((packed));
+struct ssv6xxx_read_reg {
+ u32 addr;
+ u32 value;
+} __attribute__ ((packed));
+struct ssv6xxx_write_reg {
+ u32 addr;
+ u32 value;
+} __attribute__ ((packed));
+union ssv6xxx_payload {
+ struct ssv6xxx_read_reg rreg;
+ struct ssv6xxx_read_reg_result rreg_res;
+ struct ssv6xxx_write_reg wreg;
+};
+struct ssv6xxx_cmd_hdr {
+ u8 plen;
+ u8 cmd;
+ u16 seq;
+ union ssv6xxx_payload payload;
+} __attribute__ ((packed));
+struct ssv6xxx_cmd_endpoint {
+ u8 address;
+ u16 packet_size;
+ void *buff;
+};
+struct ssv6xxx_tx_endpoint {
+ u8 address;
+ u16 packet_size;
+ int tx_res;
+};
+struct ssv6xxx_rx_endpoint {
+ u8 address;
+ u16 packet_size;
+};
+#define MAX_NR_RECVBUFF (8)
+#define MIN_NR_RECVBUFF (1)
+struct ssv6xxx_rx_buf {
+ struct ssv6xxx_list_node node;
+ struct ssv6xxx_usb_glue *glue;
+ struct urb *rx_urb;
+ void *rx_buf;
+ unsigned int rx_filled;
+ int rx_res;
+};
+struct ssv6xxx_usb_work_struct {
+ struct work_struct work;
+ struct ssv6xxx_usb_glue *glue;
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv6xxx_usb_init(void);
+void ssv6xxx_usb_exit(void);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/cabrio.h b/drivers/net/wireless/ssv6x5x/include/cabrio.h
new file mode 100644
index 000000000..092c5fe16
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/cabrio.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef CABRIO_H
+#define CABRIO_H
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define SSV_SUBVENDOR_ID_NOG 0x0e11
+#define SSV_SUBVENDOR_ID_NEW_A 0x7065
+#define SSV_CABRIO_MAGIC 0x19641014
+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
+#define SSV_DEFAULT_NOISE_FLOOR -95
+#define SSVCABRIO_RSSI_BAD -128
+#define SSVCABRIO_NUM_CHANNELS 38
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/hal.h b/drivers/net/wireless/ssv6x5x/include/hal.h
new file mode 100644
index 000000000..931c6c4b5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/hal.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _HAL_H_
+#define _HAL_H_
+#ifdef SSV_SUPPORT_HAL
+extern u32 phy_info_tbl[];
+extern size_t phy_info_tbl_size;
+#include
+enum ssv6xxx_beacon_type {
+ SSV6xxx_BEACON_0,
+ SSV6xxx_BEACON_1,
+};
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+#define HW_ID_OFFSET 7
+#define ADDRESS_OFFSET 16
+int tu_ssv6xxx_init_hal(struct ssv_softc *sc);
+int ssvxxx_get_sta_assco_cnt(struct ssv_softc *sc);
+#define HAL_ADJ_CONFIG(_sh) _sh->hal_ops.adj_config(_sh)
+#define HAL_NEED_SW_CIPHER(_sh) _sh->hal_ops.need_sw_cipher(_sh)
+#define HAL_INIT_MAC(_sh) _sh->hal_ops.init_mac(_sh)
+#define HAL_RESET_SYSPLF(_sh) _sh->hal_ops.reset_sysplf(_sh)
+#define HAL_INI_HW_SEC_PHY_TABLE(_sc) _sc->sh->hal_ops.init_hw_sec_phy_table(_sc)
+#define HAL_INIT_IQK(_sh) _sh->hal_ops.init_iqk(_sh)
+#define HAL_WRITE_MAC_INI(_sh) _sh->hal_ops.write_mac_ini(_sh)
+#define HAL_USE_HW_ENCRYPT(_cipher,_sc,_sta_priv,_vif_priv) \
+ _sc->sh->hal_ops.use_hw_encrypt(_cipher, _sc, _sta_priv, _vif_priv)
+#define HAL_SET_RX_FLOW(_sh,_type,_rxflow) \
+ _sh->hal_ops.set_rx_flow(_sh, _type, _rxflow)
+#define HAL_SET_RX_CTRL_FLOW(_sh) _sh->hal_ops.set_rx_ctrl_flow(_sh)
+#define HAL_SET_MACADDR(_sh,_vif_idx) _sh->hal_ops.set_macaddr(_sh, _vif_idx)
+#define HAL_SET_BSSID(_sh,_bssid,_vif_idx) \
+ _sh->hal_ops.set_bssid(_sh, _bssid, _vif_idx)
+#define HAL_GET_IC_TIME_TAG(_sh) _sh->hal_ops.get_ic_time_tag(_sh)
+#define HAL_GET_CHIP_ID(_sh) _sh->hal_ops.get_chip_id(_sh)
+#define HAL_IF_CHK_MAC2(_sh) _sh->hal_ops.if_chk_mac2(_sh)
+#define HAL_SAVE_HW_STATUS(_sc) _sc->sh->hal_ops.save_hw_status( _sc)
+#define HAL_PLL_CHK(_sh) _sh->hal_ops.pll_chk(_sh)
+#define HAL_GET_WSID(_sc,_vif,_sta) _sc->sh->hal_ops.get_wsid( _sc, _vif, _sta)
+#define HAL_SET_HW_WSID(_sc,_vif,_sta,_wsid) \
+ _sc->sh->hal_ops.set_hw_wsid( _sc, _vif, _sta, _wsid)
+#define HAL_DEL_HW_WSID(_sc,_hw_wsid) _sc->sh->hal_ops.del_hw_wsid( _sc, _hw_wsid)
+#define HAL_ADD_FW_WSID(_sc,_vif_priv,_sta,_sta_info) \
+ _sc->sh->hal_ops.add_fw_wsid( _sc, _vif_priv, _sta, _sta_info)
+#define HAL_DEL_FW_WSID(_sc,_sta,_sta_info) \
+ _sc->sh->hal_ops.del_fw_wsid( _sc, _sta, _sta_info)
+#define HAL_SET_FW_HWWSID_SEC_TYPE(_sc,_sta,_sta_info,_vif_priv) \
+ _sc->sh->hal_ops.set_fw_hwwsid_sec_type( _sc, _sta, _sta_info, _vif_priv)
+#define HAL_ENABLE_FW_WSID(_sc,_sta,_sta_info,_key_type) \
+ _sc->sh->hal_ops.enable_fw_wsid( _sc, _sta, _sta_info, _key_type)
+#define HAL_DISABLE_FW_WSID(_sc,_key_idx,_sta_priv,_vif_priv) \
+ _sc->sh->hal_ops.disable_fw_wsid( _sc, _key_idx, _sta_priv, _vif_priv)
+#define HAL_WEP_USE_HW_CIPHER(_sc,_vif_priv) \
+ _sc->sh->hal_ops.wep_use_hw_cipher( _sc, _vif_priv)
+#define HAL_PAIRWISE_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher,_sta_priv) \
+ _sc->sh->hal_ops.pairwise_wpa_use_hw_cipher( _sc, _vif_priv, _cipher, _sta_priv)
+#define HAL_GROUP_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher) \
+ _sc->sh->hal_ops.group_wpa_use_hw_cipher( _sc, _vif_priv, _cipher)
+#define HAL_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(_sc,_vif_info,_sta_info,_param) \
+ _sc->sh->hal_ops.set_aes_tkip_hw_crypto_group_key(_sc, _vif_info, _sta_info, _param)
+#define HAL_WRITE_PAIRWISE_KEYIDX_TO_HW(_sh,_key_idx,_wsid) \
+ _sh->hal_ops.write_pairwise_keyidx_to_hw(_sh, _key_idx, _wsid)
+#define HAL_WRITE_GROUP_KEYIDX_TO_HW(_sh,_vif_priv,_key_idx) \
+ _sh->hal_ops.write_group_keyidx_to_hw(_sh, _vif_priv, _key_idx)
+#define HAL_WRITE_PAIRWISE_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+ _sc->sh->hal_ops.write_pairwise_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define HAL_WRITE_GROUP_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+ _sc->sh->hal_ops.write_group_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define HAL_WRITE_KEY_TO_HW(_sc,_vif_priv,_sram_ptr,_wsid,_key_idx,_key_type) \
+ _sc->sh->hal_ops.write_key_to_hw(_sc, _vif_priv, _sram_ptr, _wsid, _key_idx, _key_type)
+#define HAL_SET_GROUP_CIPHER_TYPE(_sh,_vif_priv,_cipher) \
+ _sh->hal_ops.set_group_cipher_type( _sh, _vif_priv, _cipher)
+#define HAL_SET_PAIRWISE_CIPHER_TYPE(_sh,_cipher,_wsid) \
+ _sh->hal_ops.set_pairwise_cipher_type( _sh, _cipher, _wsid)
+#define HAL_CHK_IF_SUPPORT_HW_BSSID(_sc,_vif_idx) \
+ _sc->sh->hal_ops.chk_if_support_hw_bssid( _sc, _vif_idx)
+#define HAL_CHK_DUAL_VIF_CHG_RX_FLOW(_sc,_vif_priv) \
+ _sc->sh->hal_ops.chk_dual_vif_chg_rx_flow( _sc, _vif_priv)
+#define HAL_RESTORE_RX_FLOW(_sc,_vif_priv,_sta) \
+ _sc->sh->hal_ops.restore_rx_flow( _sc, _vif_priv, _sta)
+#define HAL_HW_CRYPTO_KEY_WRITE_WEP(_sc,_keyconf,_alg,_vif_info) \
+ _sc->sh->hal_ops.hw_crypto_key_write_wep( _sc, _keyconf, _alg, _vif_info)
+#define HAL_SET_WEP_HW_CRYPTO_KEY(_sc,_sta_info,_vif_priv) \
+ _sc->sh->hal_ops.set_wep_hw_crypto_key( _sc, _sta_info, _vif_priv)
+#define HAL_STORE_WEP_KEY(_sc,_vif_priv,_sta_priv,_cipher,_key) \
+ _sc->sh->hal_ops.store_wep_key( _sc, _vif_priv, _sta_priv, _cipher, _key)
+#define HAL_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT(_sc,_skb) \
+ _sc->sh->hal_ops.put_mic_space_for_hw_ccmp_encrypt( _sc, _skb)
+#ifdef CONFIG_PM
+#define HAL_SAVE_CLEAR_TRAP_REASON(_sc) \
+ _sc->sh->hal_ops.save_clear_trap_reason(_sc)
+#define HAL_RESTORE_TRAP_REASON(_sc) \
+ _sc->sh->hal_ops.restore_trap_reason(_sc)
+#define HAL_PMU_AWAKE(_sc) \
+ _sc->sh->hal_ops.pmu_awake(_sc)
+#endif
+#define HAL_SET_REPLAY_IGNORE(_sh,_ignore) \
+ _sh->hal_ops.set_replay_ignore(_sh, _ignore)
+#define HAL_UPDATE_DECISION_TABLE_6(_sh,_val) \
+ _sh->hal_ops.update_decision_table_6(_sh, _val)
+#define HAL_UPDATE_DECISION_TABLE(_sc) _sc->sh->hal_ops.update_decision_table(_sc)
+#define HAL_GET_FW_VERSION(_sh,_regval) \
+ _sh->hal_ops.get_fw_version(_sh, _regval)
+#define HAL_SET_MRX_MODE(_sh,_regval) _sh->hal_ops.set_mrx_mode(_sh, _regval)
+#define HAL_GET_MRX_MODE(_sh,_regval) _sh->hal_ops.get_mrx_mode(_sh, _regval)
+#define HAL_SET_OP_MODE(_sh,_op_mode,_vif_idx) _sh->hal_ops.set_op_mode(_sh, _op_mode, _vif_idx)
+#define HAL_HALT_MNGQ_UNTIL_DTIM(_sh,_val) \
+ _sh->hal_ops.set_halt_mngq_util_dtim(_sh,_val)
+#define HAL_SET_DUR_BURST_SIFS_G(_sh,_val) \
+ _sh->hal_ops.set_dur_burst_sifs_g(_sh, _val)
+#define HAL_SET_DUR_SLOT(_sh,_val) _sh->hal_ops.set_dur_slot(_sh, _val)
+#define HAL_SET_SIFS(_sh,_band) _sh->hal_ops.set_sifs(_sh, _band)
+#define HAL_SET_QOS_ENABLE(_sh,_val) _sh->hal_ops.set_qos_enable(_sh, _val)
+#define HAL_SET_WMM_PARAM(_sc,_params,_queue) \
+ _sc->sh->hal_ops.set_wmm_param(_sc, _params, _queue)
+#define HAL_UPDATE_PAGE_ID(_sh) _sh->hal_ops.update_page_id(_sh)
+#define HAL_INIT_TX_CFG(_sh) _sh->hal_ops.init_tx_cfg(_sh)
+#define HAL_INIT_RX_CFG(_sh) _sh->hal_ops.init_rx_cfg(_sh)
+#define HAL_ALLOC_PBUF(_sc,_size,_type) \
+ _sc->sh->hal_ops.alloc_pbuf(_sc, _size, _type)
+#define HAL_FREE_PBUF(_sc,_addr) _sc->sh->hal_ops.free_pbuf(_sc, _addr)
+#define HAL_AMPDU_AUTO_CRC_EN(_sh) _sh->hal_ops.ampdu_auto_crc_en(_sh)
+#define HAL_SET_RX_BA(_sh,_on,_ta,_tid,_ssn,_buf_size) \
+ _sh->hal_ops.set_rx_ba(_sh, _on, _ta, _tid, _ssn, _buf_size)
+#define HAL_READ_EFUSE(_sh,_pbuf) _sh->hal_ops.read_efuse(_sh, _pbuf)
+#define HAL_WRITE_EFUSE(_sh,_data,_len) _sh->hal_ops.write_efuse(_sh, _data, _len)
+#define HAL_BEACON_GET_VALID_CFG(_sh) _sh->hal_ops.beacon_get_valid_cfg(_sh)
+#define HAL_SET_BEACON_REG_LOCK(_sh,_val) \
+ _sh->hal_ops.set_beacon_reg_lock(_sh, _val)
+#define HAL_SET_BCN_ID_DTIM(_sc,_bcntype,_dtim) \
+ _sc->sh->hal_ops.set_beacon_id_dtim(_sc, _bcntype, _dtim)
+#define HAL_FILL_BCN(_sc,_regaddr,_skb) \
+ _sc->sh->hal_ops.fill_beacon(_sc, _regaddr, _skb)
+#define HAL_BEACON_ENABLE(_sc,_val) _sc->sh->hal_ops.beacon_enable(_sc, _val)
+#define HAL_SET_BCN_IFNO(_sh,_interval,_cnt) \
+ _sh->hal_ops.set_beacon_info(_sh, _interval, _cnt)
+#define HAL_GET_BCN_ONGOING(_sh) _sh->hal_ops.get_bcn_ongoing(_sh)
+#define HAL_BEACON_LOSS_ENABLE(_sh) _sh->hal_ops.beacon_loss_enable(_sh)
+#define HAL_BEACON_LOSS_DISABLE(_sh) _sh->hal_ops.beacon_loss_disable(_sh)
+#define HAL_BEACON_LOSS_CONFIG(_sh,_beacon_int,_bssid) \
+ _sh->hal_ops.beacon_loss_config(_sh, _beacon_int, _bssid)
+#define HAL_UPDATE_TXQ_MASK(_sh,_txq_mask) \
+ _sh->hal_ops.update_txq_mask(_sh, _txq_mask)
+#define HAL_READRG_HCI_INQ_INFO(_sh,_hci_used_id,_tx_use_page) \
+ _sh->hal_ops.readrg_hci_inq_info(_sh, _hci_used_id, _tx_use_page)
+#define HAL_READRG_TXQ_INFO(_sh,_txq_info,_hci_used_id) \
+ _sh->hal_ops.readrg_txq_info(_sh, _txq_info, _hci_used_id)
+#define HAL_READRG_TXQ_INFO2(_sh,_txq_info2,_hci_used_id) \
+ _sh->hal_ops.readrg_txq_info2(_sh, _txq_info2, _hci_used_id)
+#define HAL_DUMP_WSID(_sh) \
+ _sh->hal_ops.dump_wsid(_sh)
+#define HAL_DUMP_DECISION(_sh) \
+ _sh->hal_ops.dump_decision(_sh)
+#define HAL_DUMP_PHY_REG(_sh) \
+ _sh->hal_ops.dump_phy_reg(_sh)
+#define HAL_DUMP_RF_REG(_sh) \
+ _sh->hal_ops.dump_rf_reg(_sh)
+#define HAL_GET_FFOUT_CNT(_sh,_value,_tag) \
+ _sh->hal_ops.get_ffout_cnt(_value, _tag)
+#define HAL_GET_IN_FFCNT(_sh,_value,_tag) \
+ _sh->hal_ops.get_in_ffcnt(_value, _tag)
+#define HAL_READ_FFOUT_CNT(_sh,_value,_value1,_value2) \
+ _sh->hal_ops.read_ffout_cnt(_sh, _value, _value1, _value2)
+#define HAL_READ_IN_FFCNT(_sh,_value,_value1) \
+ _sh->hal_ops.read_in_ffcnt(_sh, _value, _value1)
+#define HAL_READ_ID_LEN_THRESHOLD(_sh,_tx_len,_rx_len) \
+ _sh->hal_ops.read_id_len_threshold(_sh, _tx_len, _rx_len)
+#define HAL_READ_TAG_STATUS(_sh,_ava_status) \
+ _sh->hal_ops.read_tag_status(_sh, _ava_status)
+#define HAL_CMD_MIB(_sc,_argc,_argv) _sc->sh->hal_ops.cmd_mib(_sc, _argc, _argv)
+#define HAL_CMD_POWER_SAVING(_sc,_argc,_argv) _sc->sh->hal_ops.cmd_power_saving(_sc, _argc, _argv)
+#define HAL_SUPPORT_IQK_CMD(_sh) _sh->hal_ops.support_iqk_cmd(_sh)
+#define HAL_GET_RD_ID_ADR(_sh,_id_adr) \
+ _sh->hal_ops.get_rd_id_adr(_id_adr)
+#define HAL_CMD_CALI(_sh,_argc,_argv) \
+ _sh->hal_ops.cmd_cali(_sh, _argc, _argv)
+#define HAL_BURST_READ_REG(_sh,_reg,_val,_num) \
+ _sh->hal_ops.burst_read_reg(_sh, _reg, _val, _num)
+#define HAL_BURST_WRITE_REG(_sh,_reg,_val,_num) \
+ _sh->hal_ops.burst_write_reg(_sh, _reg, _val, _num)
+#define HAL_AUTO_GEN_NULLPKT(_sh,_hwq) \
+ _sh->hal_ops.auto_gen_nullpkt(_sh, _hwq)
+#define HAL_RC_ALGORITHM(_sc) _sc->sh->hal_ops.rc_algorithm(_sc)
+#define HAL_SET_80211HW_RATE_CONFIG(_sc) \
+ _sc->sh->hal_ops.set_80211_hw_rate_config(_sc)
+#define HAL_RC_LEGACY_BITRATE_TO_RATE_DESC(_sc,_bitrate,_drate) \
+ _sc->sh->hal_ops.rc_legacy_bitrate_to_rate_desc(_bitrate, _drate)
+#define HAL_RC_RX_DATA_HANDLER(_sc,_skb,rate_idx) \
+ _sc->sh->hal_ops.rc_rx_data_handler(_sc, _skb, rate_idx)
+#define HAL_RATE_REPORT_HANDLER(_sc,_skb,_no_ba_result) \
+ _sc->sh->hal_ops.rate_report_handler(_sc, _skb, _no_ba_result)
+#define HAL_RC_PROCESS_RATE_REPORT(_sc,_skb) \
+ _sc->sh->hal_ops.rc_process_rate_report(_sc, _skb)
+#define HAL_RC_UPDATE_BASIC_RATE(_sc,_basic_rates) \
+ _sc->sh->hal_ops.rc_update_basic_rate(_sc, _basic_rates)
+#define HAL_HT_RATE_UPDATE(_sc,_skb,_rates) \
+ _sc->sh->hal_ops.rc_ht_update_rate(_skb, _sc, _rates)
+#define HAL_RC_HT_STA_CURRENT_RATE_IS_CCK(_sc,_sta) \
+ _sc->sh->hal_ops.rc_ht_sta_current_rate_is_cck(_sta)
+#define HAL_LOAD_FW_ENABLE_MCU(_sh) _sh->hal_ops.load_fw_enable_mcu(_sh)
+#define HAL_LOAD_FW_DISABLE_MCU(_sh) _sh->hal_ops.load_fw_disable_mcu(_sh)
+#define HAL_LOAD_FW_SET_STATUS(_sh,_status) \
+ _sh->hal_ops.load_fw_set_status(_sh, _status)
+#define HAL_LOAD_FW_GET_STATUS(_sh,_status) \
+ _sh->hal_ops.load_fw_get_status(_sh, _status)
+#define HAL_LOAD_FW_PRE_CONFIG_DEVICE(_sh) \
+ _sh->hal_ops.load_fw_pre_config_device(_sh)
+#define HAL_LOAD_FW_POST_CONFIG_DEVICE(_sh) \
+ _sh->hal_ops.load_fw_post_config_device(_sh)
+#define HAL_RESET_CPU(_sh) _sh->hal_ops.reset_cpu(_sh)
+#define HAL_SET_SRAM_MODE(_sh,_mode) _sh->hal_ops.set_sram_mode(_sh, _mode)
+#define HAL_ENABLE_USB_ACC(_sc,_epnum) _sc->sh->hal_ops.enable_usb_acc(_sc, _epnum)
+#define HAL_DISABLE_USB_ACC(_sc,_epnum) _sc->sh->hal_ops.disable_usb_acc(_sc, _epnum)
+#define HAL_SET_USB_LPM(_sc,_enable) _sc->sh->hal_ops.set_usb_lpm(_sc, _enable)
+#define HAL_JUMP_TO_ROM(_sc) _sc->sh->hal_ops.jump_to_rom(_sc)
+#define HAL_GET_FW_NAME(_sh,_name) _sh->hal_ops.get_fw_name(_name)
+#define HAL_SEND_TX_POLL_CMD(_sh,_type) _sh->hal_ops.send_tx_poll_cmd(_sh, _type)
+#define HAL_FLASH_READ_ALL_MAP(_sh) _sh->hal_ops.flash_read_all_map(_sh)
+#define HAL_WAIT_USB_ROM_READY(_sh) _sh->hal_ops.wait_usb_rom_ready(_sh)
+#define HAL_DETACH_USB_HCI(_sh) _sh->hal_ops.detach_usb_hci(_sh)
+#define HAL_ADD_TXINFO(_sc,_skb) _sc->sh->hal_ops.add_txinfo( _sc, _skb)
+#define HAL_UPDATE_TXINFO(_sc,_skb) _sc->sh->hal_ops.update_txinfo( _sc, _skb)
+#define HAL_UPDATE_AMPDU_TXINFO(_sc,_skb) \
+ _sc->sh->hal_ops.update_ampdu_txinfo( _sc, _skb)
+#define HAL_ADD_AMPDU_TXINFO(_sc,_skb) \
+ _sc->sh->hal_ops.add_ampdu_txinfo( _sc, _skb)
+#define HAL_UPDATE_NULL_FUNC_TXINFO(_sc,_sta,_skb) \
+ _sc->sh->hal_ops.update_null_func_txinfo( _sc, _sta, _skb)
+#define HAL_GET_TX_DESC_SIZE(_sh) _sh->hal_ops.get_tx_desc_size(_sh)
+#define HAL_GET_TX_DESC_CTYPE(_sh,_skb) \
+ _sh->hal_ops.get_tx_desc_ctype(_skb)
+#define HAL_GET_TX_DESC_REASON(_sh,_skb) \
+ _sh->hal_ops.get_tx_desc_reason(_skb)
+#define HAL_GET_TX_DESC_TXQ_IDX(_sh,_skb) \
+ _sh->hal_ops.get_tx_desc_txq_idx(_skb)
+#define HAL_TX_RATE_UPDATE(_sc,_skb) _sc->sh->hal_ops.tx_rate_update( _sc, _skb)
+#define HAL_TXTPUT_SET_DESC(_sh,_skb) _sh->hal_ops.txtput_set_desc( _sh, _skb)
+#define HAL_FILL_BEACON_TX_DESC(_sc,_skb) \
+ _sc->sh->hal_ops.fill_beacon_tx_desc(_sc, _skb)
+#define HAL_FILL_LPBK_TX_DESC(_sc,_skb,_sec,_rate) \
+ _sc->sh->hal_ops.fill_lpbk_tx_desc(_skb, _sec, _rate)
+#define HAL_CHK_LPBK_RX_RATE_DESC(_sh,_skb) \
+ _sh->hal_ops.chk_lpbk_rx_rate_desc(_sh, _skb)
+#define HAL_GET_SEC_DECODE_ERR(_sh,_skb,_mic_err,_decode_err) \
+ _sh->hal_ops.get_sec_decode_err(_skb, _mic_err, _decode_err)
+#define HAL_GET_RX_DESC_SIZE(_sh) _sh->hal_ops.get_rx_desc_size(_sh)
+#define HAL_GET_RX_DESC_LENGTH(_sh) _sh->hal_ops.get_rx_desc_length(_sh)
+#define HAL_GET_RX_DESC_WSID(_sh,_skb) \
+ _sh->hal_ops.get_rx_desc_wsid( _skb)
+#define HAL_GET_RX_DESC_RATE_IDX(_sh,_skb) \
+ _sh->hal_ops.get_rx_desc_rate_idx( _skb)
+#define HAL_GET_RX_DESC_MNG_USED(_sh,_skb) \
+ _sh->hal_ops.get_rx_desc_mng_used( _skb)
+#define HAL_IS_RX_AGGR(_sh,_skb) _sh->hal_ops.is_rx_aggr( _skb)
+#define HAL_GET_RX_DESC_CTYPE(_sh,_skb) \
+ _sh->hal_ops.get_rx_desc_ctype( _skb)
+#define HAL_GET_RX_DESC_HDR_OFFSET(_sh,_skb) \
+ _sh->hal_ops.get_rx_desc_hdr_offset( _skb)
+#define HAL_GET_RX_DESC_INFO(_sh,_skb,_packet_len,_c_type,_tx_pkt_run_no) \
+ _sh->hal_ops.get_rx_desc_info( _skb, _packet_len, _c_type, _tx_pkt_run_no)
+#define HAL_NULLFUN_FRAME_FILTER(_sh,_skb) \
+ _sh->hal_ops.nullfun_frame_filter(_skb)
+#define HAL_SET_PHY_MODE(_sh,_val) _sh->hal_ops.set_phy_mode(_sh, _val)
+#define HAL_PHY_ENABLE(_sh,_val) _sh->hal_ops.phy_enable(_sh, _val)
+#define HAL_EDCA_ENABLE(_sh,_val) _sh->hal_ops.edca_enable(_sh, _val)
+#define HAL_EDCA_STAT(_sh) _sh->hal_ops.edca_stat(_sh)
+#define HAL_RESET_MIB_PHY(_sh) _sh->hal_ops.reset_mib_phy(_sh)
+#define HAL_DUMP_MIB_RX_PHY(_sh) \
+ _sh->hal_ops.dump_mib_rx_phy(_sh)
+#define HAL_RC_MAC80211_RATE_IDX(_sc,_rate_idx,_rxs) \
+ _sc->sh->hal_ops.rc_mac80211_rate_idx(_sc, _rate_idx, _rxs)
+#define HAL_UPDATE_RXSTATUS(_sc,_skb,_rxs) \
+ _sc->sh->hal_ops.update_rxstatus(_sc, _skb, _rxs)
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+#define HAL_UPDATE_SCAN_CCI_SETTING(_sc) _sc->sh->hal_ops.update_scan_cci_setting(_sc)
+#define HAL_RECOVERY_SCAN_CCI_SETTING(_sc) _sc->sh->hal_ops.recover_scan_cci_setting(_sc)
+#endif
+#define HAL_CMD_RC(_sh,_argc,_argv) _sh->hal_ops.cmd_rc(_sh, _argc, _argv)
+#define HAL_CMD_EFUSE(_sh,_argc,_argv) _sh->hal_ops.cmd_efuse(_sh, _argc, _argv)
+#define HAL_CMD_SPECTRUM(_sh) _sh->hal_ops.cmd_spectrum(_sh)
+#define HAL_CMD_LOOPBACK(_sh,_argc,_argv) _sh->hal_ops.cmd_loopback(_sh, _argc, _argv)
+#define HAL_CMD_LOOPBACK_START(_sh) _sh->hal_ops.cmd_loopback_start(_sh)
+#define HAL_CMD_LOOPBACK_SETUP_ENV(_sh) _sh->hal_ops.cmd_loopback_setup_env(_sh)
+#define HAL_CMD_HWINFO(_sh,_argc,_argv) _sh->hal_ops.cmd_hwinfo(_sh, _argc, _argv)
+#define HAL_CMD_CCI(_sh,_argc,_argv) _sh->hal_ops.cmd_cci(_sh, _argc, _argv)
+#define HAL_CMD_TXGEN(_sh) _sh->hal_ops.cmd_txgen(_sh)
+#define HAL_CMD_RF(_sh,_argc,_argv) _sh->hal_ops.cmd_rf(_sh, _argc, _argv)
+#define HAL_UPDATE_RF_PWR(_sc) _sc->sh->hal_ops.update_rf_pwr(_sc)
+#define HAL_CMD_HWQ_LIMIT(_sh,_argc,_argv) _sh->hal_ops.cmd_hwq_limit(_sh, _argc, _argv)
+#define HAL_AMPDU_RX_START(_sc,_hw,_vif,_sta,_tid,_ssn,_buf_size) \
+ _sc->sh->hal_ops.ampdu_rx_start(_hw, _vif, _sta, _tid, _ssn, _buf_size)
+#define HAL_AMPDU_BA_HANDLER(_sc,_hw,_skb,_tx_pkt_run_no) \
+ _sc->sh->hal_ops.ampdu_ba_handler( _hw, _skb, _tx_pkt_run_no)
+#define HAL_IS_LEGACY_RATE(_sc,_skb) _sc->sh->hal_ops.is_legacy_rate(_sc, _skb)
+#define HAL_AMPDU_MAX_TRANSMIT_LENGTH(_sc,_skb,_rate_idx) \
+ _sc->sh->hal_ops.ampdu_max_transmit_length(_sc, _skb, _rate_idx)
+#define HAL_LOAD_PHY_TABLE(_sh,_tbl) _sh->hal_ops.load_phy_table(_tbl)
+#define HAL_GET_PHY_TABLE_SIZE(_sh) _sh->hal_ops.get_phy_table_size(_sh)
+#define HAL_LOAD_RF_TABLE(_sh,_tbl) _sh->hal_ops.load_rf_table(_tbl)
+#define HAL_GET_RF_TABLE_SIZE(_sh) _sh->hal_ops.get_rf_table_size(_sh)
+#define HAL_INIT_PLL(_sh) _sh->hal_ops.init_pll(_sh)
+#define HAL_UPDATE_CFG_HW_PATCH(_sh,_rftbl,_phytbl) \
+ _sh->hal_ops.update_cfg_hw_patch(_sh, _rftbl, _phytbl)
+#define HAL_UPDATE_HW_CONFIG(_sh,_rftbl,_phytbl) \
+ _sh->hal_ops.update_hw_config(_sh, _rftbl, _phytbl)
+#define HAL_CHG_PAD_SETTING(_sh) _sh->hal_ops.chg_pad_setting(_sh)
+#define HAL_CHG_CLK_SRC(_sh) _sh->hal_ops.chg_clk_src(_sh)
+#define HAL_UPDATE_EFUSE_SETTING(_sh) _sh->hal_ops.update_efuse_setting(_sh)
+#define HAL_DO_TEMPERATURE_COMPENSATION(_sh) \
+ _sh->hal_ops.do_temperature_compensation(_sh)
+#define HAL_UPDATE_PRODUCT_HW_SETTING(_sh) _sh->hal_ops.update_product_hw_setting(_sh)
+#define HAL_SET_CHANNEL(_sc,_ch,_type) _sc->sh->hal_ops.set_channel(_sc, _ch, _type)
+#define HAL_DO_IQ_CAL(_sh,_pcfg) _sh->hal_ops.do_iq_cal(_sh,_pcfg)
+#define HAL_SET_PLL_PHY_RF(_sh,_rf_tbl,_phy_tbl) \
+ _sh->hal_ops.set_pll_phy_rf(_sh, _rf_tbl, _phy_tbl)
+#define HAL_DPD_ENABLE(_sh,_val) _sh->hal_ops.dpd_enable(_sh, _val)
+#define HAL_INIT_CH_CFG(_sh) _sh->hal_ops.init_ch_cfg(_sh)
+#define HAL_SAVE_DEFAULT_IPD_CHCFG(_sh) \
+ _sh->hal_ops.save_default_ipd_chcfg(_sh)
+#define HAL_CHG_IPD_PHYINFO(_sh) _sh->hal_ops.chg_ipd_phyinfo(_sh)
+#define HAL_SET_RF_ENABLE(_sh,_val) _sh->hal_ops.set_rf_enable(_sh, _val)
+#define HAL_SET_ON3_ENABLE(_sh,_val) _sh->hal_ops.set_on3_enable(_sh, _val)
+#define HAL_INIT_GPIO_CFG(_sh) _sh->hal_ops.init_gpio_cfg(_sh)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/linux_80211.h b/drivers/net/wireless/ssv6x5x/include/linux_80211.h
new file mode 100644
index 000000000..2207d6fc6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/linux_80211.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _LINUX_80211_H_
+#define _LINUX_80211_H_
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
+#define INDEX_80211_BAND_5GHZ NL80211_BAND_5GHZ
+#define INDEX_80211_BAND_60GHZ NL80211_BAND_60GHZ
+#else
+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#define INDEX_80211_BAND_5GHZ IEEE80211_BAND_5GHZ
+#define INDEX_80211_BAND_60GHZ IEEE80211_BAND_60GHZ
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200.h b/drivers/net/wireless/ssv6x5x/include/ssv6200.h
new file mode 100644
index 000000000..613bee90a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV6200_H_
+#define _SSV6200_H_
+#include
+#include
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include
+#endif
+#ifdef ECLIPSE
+#include
+#endif
+#ifndef SSV_SUPPORT_HAL
+#include
+#include
+#endif
+#include
+#include
+#include "ssv6200_common.h"
+#ifdef SSV6200_ECO
+#define SSV6200_TOTAL_PAGE (256)
+#define SSV6200_TOTAL_ID (128)
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_RESERVED_PAGE (26)
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD (SSV6200_TOTAL_PAGE - SSV6200_PAGE_TX_THRESHOLD - SSV6200_RESERVED_PAGE)
+#define SSV6200_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6200_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 63
+#define SSV6200_ID_RX_THRESHOLD 63
+#ifdef PREFER_RX
+#define SSV6200_PAGE_TX_THRESHOLD (126-24)
+#define SSV6200_PAGE_RX_THRESHOLD (126+24)
+#else
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#define SSV6200_PAGE_TX_THRESHOLD 126
+#define SSV6200_PAGE_RX_THRESHOLD 126
+#endif
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD/2)
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (SSV6200_TOTAL_ID)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+ u32 txUsePage:8;
+ u32 txUseID:6;
+ u32 edca0:4;
+ u32 edca1:4;
+ u32 edca2:5;
+ u32 edca3:5;
+};
+#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
+#include "ssv_cfg.h"
+static inline void txrxboost_init(void)
+{
+ struct sched_param param = { .sched_priority = 0 };
+ sched_setscheduler(current, SCHED_NORMAL, ¶m);
+}
+static inline void txrxboost_change(u32 tx_frame_qlen, u32 low_threshold, u32 high_threshold, u32 prio)
+{
+ struct sched_param param;
+ if (tx_frame_qlen > high_threshold) {
+ param.sched_priority = (int)prio;
+ sched_setscheduler(current, (prio != 0)?SCHED_RR:SCHED_NORMAL, ¶m);
+ } else if (tx_frame_qlen < low_threshold) {
+ param.sched_priority = 0;
+ sched_setscheduler(current, SCHED_NORMAL, ¶m);
+ }
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h
new file mode 100644
index 000000000..30ed7e97c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h
@@ -0,0 +1,18220 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define MCU_SW_RST_MSK 0x00000004
+#define MCU_SW_RST_I_MSK 0xfffffffb
+#define MCU_SW_RST_SFT 2
+#define MCU_SW_RST_HI 2
+#define MCU_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define GPIO_SW_RST_MSK 0x00000800
+#define GPIO_SW_RST_I_MSK 0xfffff7ff
+#define GPIO_SW_RST_SFT 11
+#define GPIO_SW_RST_HI 11
+#define GPIO_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define RF_BB_SW_RST_MSK 0x00100000
+#define RF_BB_SW_RST_I_MSK 0xffefffff
+#define RF_BB_SW_RST_SFT 20
+#define RF_BB_SW_RST_HI 20
+#define RF_BB_SW_RST_SZ 1
+#define SYS_ALL_RST_MSK 0x00200000
+#define SYS_ALL_RST_I_MSK 0xffdfffff
+#define SYS_ALL_RST_SFT 21
+#define SYS_ALL_RST_HI 21
+#define SYS_ALL_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CK_SEL_1_0_MSK 0x00000003
+#define CK_SEL_1_0_I_MSK 0xfffffffc
+#define CK_SEL_1_0_SFT 0
+#define CK_SEL_1_0_HI 1
+#define CK_SEL_1_0_SZ 2
+#define CK_SEL_2_MSK 0x00000004
+#define CK_SEL_2_I_MSK 0xfffffffb
+#define CK_SEL_2_SFT 2
+#define CK_SEL_2_HI 2
+#define CK_SEL_2_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define MCU_CLK_EN_MSK 0x00000004
+#define MCU_CLK_EN_I_MSK 0xfffffffb
+#define MCU_CLK_EN_SFT 2
+#define MCU_CLK_EN_HI 2
+#define MCU_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define GPIO_CLK_EN_MSK 0x00000800
+#define GPIO_CLK_EN_I_MSK 0xfffff7ff
+#define GPIO_CLK_EN_SFT 11
+#define GPIO_CLK_EN_HI 11
+#define GPIO_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define BIST_CLK_EN_MSK 0x00100000
+#define BIST_CLK_EN_I_MSK 0xffefffff
+#define BIST_CLK_EN_SFT 20
+#define BIST_CLK_EN_HI 20
+#define BIST_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define MCU_DBG_SEL_MSK 0x0000003f
+#define MCU_DBG_SEL_I_MSK 0xffffffc0
+#define MCU_DBG_SEL_SFT 0
+#define MCU_DBG_SEL_HI 5
+#define MCU_DBG_SEL_SZ 6
+#define MCU_STOP_NOGRANT_MSK 0x00000100
+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
+#define MCU_STOP_NOGRANT_SFT 8
+#define MCU_STOP_NOGRANT_HI 8
+#define MCU_STOP_NOGRANT_SZ 1
+#define MCU_STOP_ANYTIME_MSK 0x00000200
+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
+#define MCU_STOP_ANYTIME_SFT 9
+#define MCU_STOP_ANYTIME_HI 9
+#define MCU_STOP_ANYTIME_SZ 1
+#define MCU_DBG_DATA_MSK 0xffffffff
+#define MCU_DBG_DATA_I_MSK 0x00000000
+#define MCU_DBG_DATA_SFT 0
+#define MCU_DBG_DATA_HI 31
+#define MCU_DBG_DATA_SZ 32
+#define AHB_SW_RST_MSK 0x00000001
+#define AHB_SW_RST_I_MSK 0xfffffffe
+#define AHB_SW_RST_SFT 0
+#define AHB_SW_RST_HI 0
+#define AHB_SW_RST_SZ 1
+#define AHB_ERR_RST_MSK 0x00000002
+#define AHB_ERR_RST_I_MSK 0xfffffffd
+#define AHB_ERR_RST_SFT 1
+#define AHB_ERR_RST_HI 1
+#define AHB_ERR_RST_SZ 1
+#define REG_AHB_DEBUG_MX_MSK 0x00000030
+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
+#define REG_AHB_DEBUG_MX_SFT 4
+#define REG_AHB_DEBUG_MX_HI 5
+#define REG_AHB_DEBUG_MX_SZ 2
+#define REG_PKT_W_NBRT_MSK 0x00000100
+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
+#define REG_PKT_W_NBRT_SFT 8
+#define REG_PKT_W_NBRT_HI 8
+#define REG_PKT_W_NBRT_SZ 1
+#define REG_PKT_R_NBRT_MSK 0x00000200
+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
+#define REG_PKT_R_NBRT_SFT 9
+#define REG_PKT_R_NBRT_HI 9
+#define REG_PKT_R_NBRT_SZ 1
+#define IQ_SRAM_SEL_0_MSK 0x00001000
+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
+#define IQ_SRAM_SEL_0_SFT 12
+#define IQ_SRAM_SEL_0_HI 12
+#define IQ_SRAM_SEL_0_SZ 1
+#define IQ_SRAM_SEL_1_MSK 0x00002000
+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
+#define IQ_SRAM_SEL_1_SFT 13
+#define IQ_SRAM_SEL_1_HI 13
+#define IQ_SRAM_SEL_1_SZ 1
+#define IQ_SRAM_SEL_2_MSK 0x00004000
+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
+#define IQ_SRAM_SEL_2_SFT 14
+#define IQ_SRAM_SEL_2_HI 14
+#define IQ_SRAM_SEL_2_SZ 1
+#define AHB_STATUS_MSK 0xffff0000
+#define AHB_STATUS_I_MSK 0x0000ffff
+#define AHB_STATUS_SFT 16
+#define AHB_STATUS_HI 31
+#define AHB_STATUS_SZ 16
+#define PARALLEL_DR_MSK 0x00000001
+#define PARALLEL_DR_I_MSK 0xfffffffe
+#define PARALLEL_DR_SFT 0
+#define PARALLEL_DR_HI 0
+#define PARALLEL_DR_SZ 1
+#define MBRUN_MSK 0x00000010
+#define MBRUN_I_MSK 0xffffffef
+#define MBRUN_SFT 4
+#define MBRUN_HI 4
+#define MBRUN_SZ 1
+#define SHIFT_DR_MSK 0x00000100
+#define SHIFT_DR_I_MSK 0xfffffeff
+#define SHIFT_DR_SFT 8
+#define SHIFT_DR_HI 8
+#define SHIFT_DR_SZ 1
+#define MODE_REG_SI_MSK 0x00000200
+#define MODE_REG_SI_I_MSK 0xfffffdff
+#define MODE_REG_SI_SFT 9
+#define MODE_REG_SI_HI 9
+#define MODE_REG_SI_SZ 1
+#define SIMULATION_MODE_MSK 0x00000400
+#define SIMULATION_MODE_I_MSK 0xfffffbff
+#define SIMULATION_MODE_SFT 10
+#define SIMULATION_MODE_HI 10
+#define SIMULATION_MODE_SZ 1
+#define DBIST_MODE_MSK 0x00000800
+#define DBIST_MODE_I_MSK 0xfffff7ff
+#define DBIST_MODE_SFT 11
+#define DBIST_MODE_HI 11
+#define DBIST_MODE_SZ 1
+#define MODE_REG_IN_MSK 0x001fffff
+#define MODE_REG_IN_I_MSK 0xffe00000
+#define MODE_REG_IN_SFT 0
+#define MODE_REG_IN_HI 20
+#define MODE_REG_IN_SZ 21
+#define MODE_REG_OUT_MCU_MSK 0x001fffff
+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
+#define MODE_REG_OUT_MCU_SFT 0
+#define MODE_REG_OUT_MCU_HI 20
+#define MODE_REG_OUT_MCU_SZ 21
+#define MODE_REG_SO_MCU_MSK 0x80000000
+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MCU_SFT 31
+#define MODE_REG_SO_MCU_HI 31
+#define MODE_REG_SO_MCU_SZ 1
+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
+#define MONITOR_BUS_MCU_31_0_SFT 0
+#define MONITOR_BUS_MCU_31_0_HI 31
+#define MONITOR_BUS_MCU_31_0_SZ 32
+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
+#define MONITOR_BUS_MCU_33_32_SFT 0
+#define MONITOR_BUS_MCU_33_32_HI 1
+#define MONITOR_BUS_MCU_33_32_SZ 2
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define DATA_UART_W2B_EN_MSK 0x00000010
+#define DATA_UART_W2B_EN_I_MSK 0xffffffef
+#define DATA_UART_W2B_EN_SFT 4
+#define DATA_UART_W2B_EN_HI 4
+#define DATA_UART_W2B_EN_SZ 1
+#define AHB_ILL_ADDR_MSK 0xffffffff
+#define AHB_ILL_ADDR_I_MSK 0x00000000
+#define AHB_ILL_ADDR_SFT 0
+#define AHB_ILL_ADDR_HI 31
+#define AHB_ILL_ADDR_SZ 32
+#define AHB_FEN_ADDR_MSK 0xffffffff
+#define AHB_FEN_ADDR_I_MSK 0x00000000
+#define AHB_FEN_ADDR_SFT 0
+#define AHB_FEN_ADDR_HI 31
+#define AHB_FEN_ADDR_SZ 32
+#define ILL_ADDR_CLR_MSK 0x00000001
+#define ILL_ADDR_CLR_I_MSK 0xfffffffe
+#define ILL_ADDR_CLR_SFT 0
+#define ILL_ADDR_CLR_HI 0
+#define ILL_ADDR_CLR_SZ 1
+#define FENCE_HIT_CLR_MSK 0x00000002
+#define FENCE_HIT_CLR_I_MSK 0xfffffffd
+#define FENCE_HIT_CLR_SFT 1
+#define FENCE_HIT_CLR_HI 1
+#define FENCE_HIT_CLR_SZ 1
+#define ILL_ADDR_INT_MSK 0x00000010
+#define ILL_ADDR_INT_I_MSK 0xffffffef
+#define ILL_ADDR_INT_SFT 4
+#define ILL_ADDR_INT_HI 4
+#define ILL_ADDR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000020
+#define FENCE_HIT_INT_I_MSK 0xffffffdf
+#define FENCE_HIT_INT_SFT 5
+#define FENCE_HIT_INT_HI 5
+#define FENCE_HIT_INT_SZ 1
+#define PWM_INI_VALUE_P_A_MSK 0x000000ff
+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_A_SFT 0
+#define PWM_INI_VALUE_P_A_HI 7
+#define PWM_INI_VALUE_P_A_SZ 8
+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_A_SFT 8
+#define PWM_INI_VALUE_N_A_HI 15
+#define PWM_INI_VALUE_N_A_SZ 8
+#define PWM_POST_SCALER_A_MSK 0x000f0000
+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_A_SFT 16
+#define PWM_POST_SCALER_A_HI 19
+#define PWM_POST_SCALER_A_SZ 4
+#define PWM_ALWAYSON_A_MSK 0x20000000
+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_A_SFT 29
+#define PWM_ALWAYSON_A_HI 29
+#define PWM_ALWAYSON_A_SZ 1
+#define PWM_INVERT_A_MSK 0x40000000
+#define PWM_INVERT_A_I_MSK 0xbfffffff
+#define PWM_INVERT_A_SFT 30
+#define PWM_INVERT_A_HI 30
+#define PWM_INVERT_A_SZ 1
+#define PWM_ENABLE_A_MSK 0x80000000
+#define PWM_ENABLE_A_I_MSK 0x7fffffff
+#define PWM_ENABLE_A_SFT 31
+#define PWM_ENABLE_A_HI 31
+#define PWM_ENABLE_A_SZ 1
+#define PWM_INI_VALUE_P_B_MSK 0x000000ff
+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_B_SFT 0
+#define PWM_INI_VALUE_P_B_HI 7
+#define PWM_INI_VALUE_P_B_SZ 8
+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_B_SFT 8
+#define PWM_INI_VALUE_N_B_HI 15
+#define PWM_INI_VALUE_N_B_SZ 8
+#define PWM_POST_SCALER_B_MSK 0x000f0000
+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_B_SFT 16
+#define PWM_POST_SCALER_B_HI 19
+#define PWM_POST_SCALER_B_SZ 4
+#define PWM_ALWAYSON_B_MSK 0x20000000
+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_B_SFT 29
+#define PWM_ALWAYSON_B_HI 29
+#define PWM_ALWAYSON_B_SZ 1
+#define PWM_INVERT_B_MSK 0x40000000
+#define PWM_INVERT_B_I_MSK 0xbfffffff
+#define PWM_INVERT_B_SFT 30
+#define PWM_INVERT_B_HI 30
+#define PWM_INVERT_B_SZ 1
+#define PWM_ENABLE_B_MSK 0x80000000
+#define PWM_ENABLE_B_I_MSK 0x7fffffff
+#define PWM_ENABLE_B_SFT 31
+#define PWM_ENABLE_B_HI 31
+#define PWM_ENABLE_B_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define PRESCALER_USTIMER_MSK 0x000001ff
+#define PRESCALER_USTIMER_I_MSK 0xfffffe00
+#define PRESCALER_USTIMER_SFT 0
+#define PRESCALER_USTIMER_HI 8
+#define PRESCALER_USTIMER_SZ 9
+#define MODE_REG_IN_MMU_MSK 0x0000ffff
+#define MODE_REG_IN_MMU_I_MSK 0xffff0000
+#define MODE_REG_IN_MMU_SFT 0
+#define MODE_REG_IN_MMU_HI 15
+#define MODE_REG_IN_MMU_SZ 16
+#define MODE_REG_OUT_MMU_MSK 0x0000ffff
+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
+#define MODE_REG_OUT_MMU_SFT 0
+#define MODE_REG_OUT_MMU_HI 15
+#define MODE_REG_OUT_MMU_SZ 16
+#define MODE_REG_SO_MMU_MSK 0x80000000
+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MMU_SFT 31
+#define MODE_REG_SO_MMU_HI 31
+#define MODE_REG_SO_MMU_SZ 1
+#define MONITOR_BUS_MMU_MSK 0x0007ffff
+#define MONITOR_BUS_MMU_I_MSK 0xfff80000
+#define MONITOR_BUS_MMU_SFT 0
+#define MONITOR_BUS_MMU_HI 18
+#define MONITOR_BUS_MMU_SZ 19
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define WDT_INIT_MSK 0x00000001
+#define WDT_INIT_I_MSK 0xfffffffe
+#define WDT_INIT_SFT 0
+#define WDT_INIT_HI 0
+#define WDT_INIT_SZ 1
+#define SD_HOST_INIT_MSK 0x00000002
+#define SD_HOST_INIT_I_MSK 0xfffffffd
+#define SD_HOST_INIT_SFT 1
+#define SD_HOST_INIT_HI 1
+#define SD_HOST_INIT_SZ 1
+#define ALLOW_SD_RESET_MSK 0x00000001
+#define ALLOW_SD_RESET_I_MSK 0xfffffffe
+#define ALLOW_SD_RESET_SFT 0
+#define ALLOW_SD_RESET_HI 0
+#define ALLOW_SD_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_STATUS_MSK 0x00020000
+#define MCU_WDT_STATUS_I_MSK 0xfffdffff
+#define MCU_WDT_STATUS_SFT 17
+#define MCU_WDT_STATUS_HI 17
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_STATUS_MSK 0x00020000
+#define SYS_WDT_STATUS_I_MSK 0xfffdffff
+#define SYS_WDT_STATUS_SFT 17
+#define SYS_WDT_STATUS_HI 17
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define XLNA_EN_O_OE_MSK 0x00000001
+#define XLNA_EN_O_OE_I_MSK 0xfffffffe
+#define XLNA_EN_O_OE_SFT 0
+#define XLNA_EN_O_OE_HI 0
+#define XLNA_EN_O_OE_SZ 1
+#define XLNA_EN_O_PE_MSK 0x00000002
+#define XLNA_EN_O_PE_I_MSK 0xfffffffd
+#define XLNA_EN_O_PE_SFT 1
+#define XLNA_EN_O_PE_HI 1
+#define XLNA_EN_O_PE_SZ 1
+#define PAD6_IE_MSK 0x00000008
+#define PAD6_IE_I_MSK 0xfffffff7
+#define PAD6_IE_SFT 3
+#define PAD6_IE_HI 3
+#define PAD6_IE_SZ 1
+#define PAD6_SEL_I_MSK 0x00000030
+#define PAD6_SEL_I_I_MSK 0xffffffcf
+#define PAD6_SEL_I_SFT 4
+#define PAD6_SEL_I_HI 5
+#define PAD6_SEL_I_SZ 2
+#define PAD6_OD_MSK 0x00000100
+#define PAD6_OD_I_MSK 0xfffffeff
+#define PAD6_OD_SFT 8
+#define PAD6_OD_HI 8
+#define PAD6_OD_SZ 1
+#define PAD6_SEL_O_MSK 0x00001000
+#define PAD6_SEL_O_I_MSK 0xffffefff
+#define PAD6_SEL_O_SFT 12
+#define PAD6_SEL_O_HI 12
+#define PAD6_SEL_O_SZ 1
+#define XLNA_EN_O_C_MSK 0x10000000
+#define XLNA_EN_O_C_I_MSK 0xefffffff
+#define XLNA_EN_O_C_SFT 28
+#define XLNA_EN_O_C_HI 28
+#define XLNA_EN_O_C_SZ 1
+#define WIFI_TX_SW_O_OE_MSK 0x00000001
+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_TX_SW_O_OE_SFT 0
+#define WIFI_TX_SW_O_OE_HI 0
+#define WIFI_TX_SW_O_OE_SZ 1
+#define WIFI_TX_SW_O_PE_MSK 0x00000002
+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_TX_SW_O_PE_SFT 1
+#define WIFI_TX_SW_O_PE_HI 1
+#define WIFI_TX_SW_O_PE_SZ 1
+#define PAD7_IE_MSK 0x00000008
+#define PAD7_IE_I_MSK 0xfffffff7
+#define PAD7_IE_SFT 3
+#define PAD7_IE_HI 3
+#define PAD7_IE_SZ 1
+#define PAD7_SEL_I_MSK 0x00000030
+#define PAD7_SEL_I_I_MSK 0xffffffcf
+#define PAD7_SEL_I_SFT 4
+#define PAD7_SEL_I_HI 5
+#define PAD7_SEL_I_SZ 2
+#define PAD7_OD_MSK 0x00000100
+#define PAD7_OD_I_MSK 0xfffffeff
+#define PAD7_OD_SFT 8
+#define PAD7_OD_HI 8
+#define PAD7_OD_SZ 1
+#define PAD7_SEL_O_MSK 0x00001000
+#define PAD7_SEL_O_I_MSK 0xffffefff
+#define PAD7_SEL_O_SFT 12
+#define PAD7_SEL_O_HI 12
+#define PAD7_SEL_O_SZ 1
+#define WIFI_TX_SW_O_C_MSK 0x10000000
+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_TX_SW_O_C_SFT 28
+#define WIFI_TX_SW_O_C_HI 28
+#define WIFI_TX_SW_O_C_SZ 1
+#define WIFI_RX_SW_O_OE_MSK 0x00000001
+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_RX_SW_O_OE_SFT 0
+#define WIFI_RX_SW_O_OE_HI 0
+#define WIFI_RX_SW_O_OE_SZ 1
+#define WIFI_RX_SW_O_PE_MSK 0x00000002
+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_RX_SW_O_PE_SFT 1
+#define WIFI_RX_SW_O_PE_HI 1
+#define WIFI_RX_SW_O_PE_SZ 1
+#define PAD8_IE_MSK 0x00000008
+#define PAD8_IE_I_MSK 0xfffffff7
+#define PAD8_IE_SFT 3
+#define PAD8_IE_HI 3
+#define PAD8_IE_SZ 1
+#define PAD8_SEL_I_MSK 0x00000030
+#define PAD8_SEL_I_I_MSK 0xffffffcf
+#define PAD8_SEL_I_SFT 4
+#define PAD8_SEL_I_HI 5
+#define PAD8_SEL_I_SZ 2
+#define PAD8_OD_MSK 0x00000100
+#define PAD8_OD_I_MSK 0xfffffeff
+#define PAD8_OD_SFT 8
+#define PAD8_OD_HI 8
+#define PAD8_OD_SZ 1
+#define WIFI_RX_SW_O_C_MSK 0x10000000
+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_RX_SW_O_C_SFT 28
+#define WIFI_RX_SW_O_C_HI 28
+#define WIFI_RX_SW_O_C_SZ 1
+#define BT_SW_O_OE_MSK 0x00000001
+#define BT_SW_O_OE_I_MSK 0xfffffffe
+#define BT_SW_O_OE_SFT 0
+#define BT_SW_O_OE_HI 0
+#define BT_SW_O_OE_SZ 1
+#define BT_SW_O_PE_MSK 0x00000002
+#define BT_SW_O_PE_I_MSK 0xfffffffd
+#define BT_SW_O_PE_SFT 1
+#define BT_SW_O_PE_HI 1
+#define BT_SW_O_PE_SZ 1
+#define PAD9_IE_MSK 0x00000008
+#define PAD9_IE_I_MSK 0xfffffff7
+#define PAD9_IE_SFT 3
+#define PAD9_IE_HI 3
+#define PAD9_IE_SZ 1
+#define PAD9_SEL_I_MSK 0x00000030
+#define PAD9_SEL_I_I_MSK 0xffffffcf
+#define PAD9_SEL_I_SFT 4
+#define PAD9_SEL_I_HI 5
+#define PAD9_SEL_I_SZ 2
+#define PAD9_OD_MSK 0x00000100
+#define PAD9_OD_I_MSK 0xfffffeff
+#define PAD9_OD_SFT 8
+#define PAD9_OD_HI 8
+#define PAD9_OD_SZ 1
+#define PAD9_SEL_O_MSK 0x00001000
+#define PAD9_SEL_O_I_MSK 0xffffefff
+#define PAD9_SEL_O_SFT 12
+#define PAD9_SEL_O_HI 12
+#define PAD9_SEL_O_SZ 1
+#define BT_SW_O_C_MSK 0x10000000
+#define BT_SW_O_C_I_MSK 0xefffffff
+#define BT_SW_O_C_SFT 28
+#define BT_SW_O_C_HI 28
+#define BT_SW_O_C_SZ 1
+#define XPA_EN_O_OE_MSK 0x00000001
+#define XPA_EN_O_OE_I_MSK 0xfffffffe
+#define XPA_EN_O_OE_SFT 0
+#define XPA_EN_O_OE_HI 0
+#define XPA_EN_O_OE_SZ 1
+#define XPA_EN_O_PE_MSK 0x00000002
+#define XPA_EN_O_PE_I_MSK 0xfffffffd
+#define XPA_EN_O_PE_SFT 1
+#define XPA_EN_O_PE_HI 1
+#define XPA_EN_O_PE_SZ 1
+#define PAD11_IE_MSK 0x00000008
+#define PAD11_IE_I_MSK 0xfffffff7
+#define PAD11_IE_SFT 3
+#define PAD11_IE_HI 3
+#define PAD11_IE_SZ 1
+#define PAD11_SEL_I_MSK 0x00000030
+#define PAD11_SEL_I_I_MSK 0xffffffcf
+#define PAD11_SEL_I_SFT 4
+#define PAD11_SEL_I_HI 5
+#define PAD11_SEL_I_SZ 2
+#define PAD11_OD_MSK 0x00000100
+#define PAD11_OD_I_MSK 0xfffffeff
+#define PAD11_OD_SFT 8
+#define PAD11_OD_HI 8
+#define PAD11_OD_SZ 1
+#define PAD11_SEL_O_MSK 0x00001000
+#define PAD11_SEL_O_I_MSK 0xffffefff
+#define PAD11_SEL_O_SFT 12
+#define PAD11_SEL_O_HI 12
+#define PAD11_SEL_O_SZ 1
+#define XPA_EN_O_C_MSK 0x10000000
+#define XPA_EN_O_C_I_MSK 0xefffffff
+#define XPA_EN_O_C_SFT 28
+#define XPA_EN_O_C_HI 28
+#define XPA_EN_O_C_SZ 1
+#define PAD15_OE_MSK 0x00000001
+#define PAD15_OE_I_MSK 0xfffffffe
+#define PAD15_OE_SFT 0
+#define PAD15_OE_HI 0
+#define PAD15_OE_SZ 1
+#define PAD15_PE_MSK 0x00000002
+#define PAD15_PE_I_MSK 0xfffffffd
+#define PAD15_PE_SFT 1
+#define PAD15_PE_HI 1
+#define PAD15_PE_SZ 1
+#define PAD15_DS_MSK 0x00000004
+#define PAD15_DS_I_MSK 0xfffffffb
+#define PAD15_DS_SFT 2
+#define PAD15_DS_HI 2
+#define PAD15_DS_SZ 1
+#define PAD15_IE_MSK 0x00000008
+#define PAD15_IE_I_MSK 0xfffffff7
+#define PAD15_IE_SFT 3
+#define PAD15_IE_HI 3
+#define PAD15_IE_SZ 1
+#define PAD15_SEL_I_MSK 0x00000030
+#define PAD15_SEL_I_I_MSK 0xffffffcf
+#define PAD15_SEL_I_SFT 4
+#define PAD15_SEL_I_HI 5
+#define PAD15_SEL_I_SZ 2
+#define PAD15_OD_MSK 0x00000100
+#define PAD15_OD_I_MSK 0xfffffeff
+#define PAD15_OD_SFT 8
+#define PAD15_OD_HI 8
+#define PAD15_OD_SZ 1
+#define PAD15_SEL_O_MSK 0x00001000
+#define PAD15_SEL_O_I_MSK 0xffffefff
+#define PAD15_SEL_O_SFT 12
+#define PAD15_SEL_O_HI 12
+#define PAD15_SEL_O_SZ 1
+#define TEST_1_ID_MSK 0x10000000
+#define TEST_1_ID_I_MSK 0xefffffff
+#define TEST_1_ID_SFT 28
+#define TEST_1_ID_HI 28
+#define TEST_1_ID_SZ 1
+#define PAD16_OE_MSK 0x00000001
+#define PAD16_OE_I_MSK 0xfffffffe
+#define PAD16_OE_SFT 0
+#define PAD16_OE_HI 0
+#define PAD16_OE_SZ 1
+#define PAD16_PE_MSK 0x00000002
+#define PAD16_PE_I_MSK 0xfffffffd
+#define PAD16_PE_SFT 1
+#define PAD16_PE_HI 1
+#define PAD16_PE_SZ 1
+#define PAD16_DS_MSK 0x00000004
+#define PAD16_DS_I_MSK 0xfffffffb
+#define PAD16_DS_SFT 2
+#define PAD16_DS_HI 2
+#define PAD16_DS_SZ 1
+#define PAD16_IE_MSK 0x00000008
+#define PAD16_IE_I_MSK 0xfffffff7
+#define PAD16_IE_SFT 3
+#define PAD16_IE_HI 3
+#define PAD16_IE_SZ 1
+#define PAD16_SEL_I_MSK 0x00000030
+#define PAD16_SEL_I_I_MSK 0xffffffcf
+#define PAD16_SEL_I_SFT 4
+#define PAD16_SEL_I_HI 5
+#define PAD16_SEL_I_SZ 2
+#define PAD16_OD_MSK 0x00000100
+#define PAD16_OD_I_MSK 0xfffffeff
+#define PAD16_OD_SFT 8
+#define PAD16_OD_HI 8
+#define PAD16_OD_SZ 1
+#define PAD16_SEL_O_MSK 0x00001000
+#define PAD16_SEL_O_I_MSK 0xffffefff
+#define PAD16_SEL_O_SFT 12
+#define PAD16_SEL_O_HI 12
+#define PAD16_SEL_O_SZ 1
+#define TEST_2_ID_MSK 0x10000000
+#define TEST_2_ID_I_MSK 0xefffffff
+#define TEST_2_ID_SFT 28
+#define TEST_2_ID_HI 28
+#define TEST_2_ID_SZ 1
+#define PAD17_OE_MSK 0x00000001
+#define PAD17_OE_I_MSK 0xfffffffe
+#define PAD17_OE_SFT 0
+#define PAD17_OE_HI 0
+#define PAD17_OE_SZ 1
+#define PAD17_PE_MSK 0x00000002
+#define PAD17_PE_I_MSK 0xfffffffd
+#define PAD17_PE_SFT 1
+#define PAD17_PE_HI 1
+#define PAD17_PE_SZ 1
+#define PAD17_DS_MSK 0x00000004
+#define PAD17_DS_I_MSK 0xfffffffb
+#define PAD17_DS_SFT 2
+#define PAD17_DS_HI 2
+#define PAD17_DS_SZ 1
+#define PAD17_IE_MSK 0x00000008
+#define PAD17_IE_I_MSK 0xfffffff7
+#define PAD17_IE_SFT 3
+#define PAD17_IE_HI 3
+#define PAD17_IE_SZ 1
+#define PAD17_SEL_I_MSK 0x00000030
+#define PAD17_SEL_I_I_MSK 0xffffffcf
+#define PAD17_SEL_I_SFT 4
+#define PAD17_SEL_I_HI 5
+#define PAD17_SEL_I_SZ 2
+#define PAD17_OD_MSK 0x00000100
+#define PAD17_OD_I_MSK 0xfffffeff
+#define PAD17_OD_SFT 8
+#define PAD17_OD_HI 8
+#define PAD17_OD_SZ 1
+#define PAD17_SEL_O_MSK 0x00001000
+#define PAD17_SEL_O_I_MSK 0xffffefff
+#define PAD17_SEL_O_SFT 12
+#define PAD17_SEL_O_HI 12
+#define PAD17_SEL_O_SZ 1
+#define TEST_3_ID_MSK 0x10000000
+#define TEST_3_ID_I_MSK 0xefffffff
+#define TEST_3_ID_SFT 28
+#define TEST_3_ID_HI 28
+#define TEST_3_ID_SZ 1
+#define PAD18_OE_MSK 0x00000001
+#define PAD18_OE_I_MSK 0xfffffffe
+#define PAD18_OE_SFT 0
+#define PAD18_OE_HI 0
+#define PAD18_OE_SZ 1
+#define PAD18_PE_MSK 0x00000002
+#define PAD18_PE_I_MSK 0xfffffffd
+#define PAD18_PE_SFT 1
+#define PAD18_PE_HI 1
+#define PAD18_PE_SZ 1
+#define PAD18_DS_MSK 0x00000004
+#define PAD18_DS_I_MSK 0xfffffffb
+#define PAD18_DS_SFT 2
+#define PAD18_DS_HI 2
+#define PAD18_DS_SZ 1
+#define PAD18_IE_MSK 0x00000008
+#define PAD18_IE_I_MSK 0xfffffff7
+#define PAD18_IE_SFT 3
+#define PAD18_IE_HI 3
+#define PAD18_IE_SZ 1
+#define PAD18_SEL_I_MSK 0x00000030
+#define PAD18_SEL_I_I_MSK 0xffffffcf
+#define PAD18_SEL_I_SFT 4
+#define PAD18_SEL_I_HI 5
+#define PAD18_SEL_I_SZ 2
+#define PAD18_OD_MSK 0x00000100
+#define PAD18_OD_I_MSK 0xfffffeff
+#define PAD18_OD_SFT 8
+#define PAD18_OD_HI 8
+#define PAD18_OD_SZ 1
+#define PAD18_SEL_O_MSK 0x00003000
+#define PAD18_SEL_O_I_MSK 0xffffcfff
+#define PAD18_SEL_O_SFT 12
+#define PAD18_SEL_O_HI 13
+#define PAD18_SEL_O_SZ 2
+#define TEST_4_ID_MSK 0x10000000
+#define TEST_4_ID_I_MSK 0xefffffff
+#define TEST_4_ID_SFT 28
+#define TEST_4_ID_HI 28
+#define TEST_4_ID_SZ 1
+#define PAD19_OE_MSK 0x00000001
+#define PAD19_OE_I_MSK 0xfffffffe
+#define PAD19_OE_SFT 0
+#define PAD19_OE_HI 0
+#define PAD19_OE_SZ 1
+#define PAD19_PE_MSK 0x00000002
+#define PAD19_PE_I_MSK 0xfffffffd
+#define PAD19_PE_SFT 1
+#define PAD19_PE_HI 1
+#define PAD19_PE_SZ 1
+#define PAD19_DS_MSK 0x00000004
+#define PAD19_DS_I_MSK 0xfffffffb
+#define PAD19_DS_SFT 2
+#define PAD19_DS_HI 2
+#define PAD19_DS_SZ 1
+#define PAD19_IE_MSK 0x00000008
+#define PAD19_IE_I_MSK 0xfffffff7
+#define PAD19_IE_SFT 3
+#define PAD19_IE_HI 3
+#define PAD19_IE_SZ 1
+#define PAD19_SEL_I_MSK 0x00000030
+#define PAD19_SEL_I_I_MSK 0xffffffcf
+#define PAD19_SEL_I_SFT 4
+#define PAD19_SEL_I_HI 5
+#define PAD19_SEL_I_SZ 2
+#define PAD19_OD_MSK 0x00000100
+#define PAD19_OD_I_MSK 0xfffffeff
+#define PAD19_OD_SFT 8
+#define PAD19_OD_HI 8
+#define PAD19_OD_SZ 1
+#define PAD19_SEL_O_MSK 0x00007000
+#define PAD19_SEL_O_I_MSK 0xffff8fff
+#define PAD19_SEL_O_SFT 12
+#define PAD19_SEL_O_HI 14
+#define PAD19_SEL_O_SZ 3
+#define SHORT_TO_20_ID_MSK 0x10000000
+#define SHORT_TO_20_ID_I_MSK 0xefffffff
+#define SHORT_TO_20_ID_SFT 28
+#define SHORT_TO_20_ID_HI 28
+#define SHORT_TO_20_ID_SZ 1
+#define PAD20_OE_MSK 0x00000001
+#define PAD20_OE_I_MSK 0xfffffffe
+#define PAD20_OE_SFT 0
+#define PAD20_OE_HI 0
+#define PAD20_OE_SZ 1
+#define PAD20_PE_MSK 0x00000002
+#define PAD20_PE_I_MSK 0xfffffffd
+#define PAD20_PE_SFT 1
+#define PAD20_PE_HI 1
+#define PAD20_PE_SZ 1
+#define PAD20_DS_MSK 0x00000004
+#define PAD20_DS_I_MSK 0xfffffffb
+#define PAD20_DS_SFT 2
+#define PAD20_DS_HI 2
+#define PAD20_DS_SZ 1
+#define PAD20_IE_MSK 0x00000008
+#define PAD20_IE_I_MSK 0xfffffff7
+#define PAD20_IE_SFT 3
+#define PAD20_IE_HI 3
+#define PAD20_IE_SZ 1
+#define PAD20_SEL_I_MSK 0x000000f0
+#define PAD20_SEL_I_I_MSK 0xffffff0f
+#define PAD20_SEL_I_SFT 4
+#define PAD20_SEL_I_HI 7
+#define PAD20_SEL_I_SZ 4
+#define PAD20_OD_MSK 0x00000100
+#define PAD20_OD_I_MSK 0xfffffeff
+#define PAD20_OD_SFT 8
+#define PAD20_OD_HI 8
+#define PAD20_OD_SZ 1
+#define PAD20_SEL_O_MSK 0x00003000
+#define PAD20_SEL_O_I_MSK 0xffffcfff
+#define PAD20_SEL_O_SFT 12
+#define PAD20_SEL_O_HI 13
+#define PAD20_SEL_O_SZ 2
+#define STRAP0_MSK 0x08000000
+#define STRAP0_I_MSK 0xf7ffffff
+#define STRAP0_SFT 27
+#define STRAP0_HI 27
+#define STRAP0_SZ 1
+#define GPIO_TEST_1_ID_MSK 0x10000000
+#define GPIO_TEST_1_ID_I_MSK 0xefffffff
+#define GPIO_TEST_1_ID_SFT 28
+#define GPIO_TEST_1_ID_HI 28
+#define GPIO_TEST_1_ID_SZ 1
+#define PAD21_OE_MSK 0x00000001
+#define PAD21_OE_I_MSK 0xfffffffe
+#define PAD21_OE_SFT 0
+#define PAD21_OE_HI 0
+#define PAD21_OE_SZ 1
+#define PAD21_PE_MSK 0x00000002
+#define PAD21_PE_I_MSK 0xfffffffd
+#define PAD21_PE_SFT 1
+#define PAD21_PE_HI 1
+#define PAD21_PE_SZ 1
+#define PAD21_DS_MSK 0x00000004
+#define PAD21_DS_I_MSK 0xfffffffb
+#define PAD21_DS_SFT 2
+#define PAD21_DS_HI 2
+#define PAD21_DS_SZ 1
+#define PAD21_IE_MSK 0x00000008
+#define PAD21_IE_I_MSK 0xfffffff7
+#define PAD21_IE_SFT 3
+#define PAD21_IE_HI 3
+#define PAD21_IE_SZ 1
+#define PAD21_SEL_I_MSK 0x00000070
+#define PAD21_SEL_I_I_MSK 0xffffff8f
+#define PAD21_SEL_I_SFT 4
+#define PAD21_SEL_I_HI 6
+#define PAD21_SEL_I_SZ 3
+#define PAD21_OD_MSK 0x00000100
+#define PAD21_OD_I_MSK 0xfffffeff
+#define PAD21_OD_SFT 8
+#define PAD21_OD_HI 8
+#define PAD21_OD_SZ 1
+#define PAD21_SEL_O_MSK 0x00003000
+#define PAD21_SEL_O_I_MSK 0xffffcfff
+#define PAD21_SEL_O_SFT 12
+#define PAD21_SEL_O_HI 13
+#define PAD21_SEL_O_SZ 2
+#define STRAP3_MSK 0x08000000
+#define STRAP3_I_MSK 0xf7ffffff
+#define STRAP3_SFT 27
+#define STRAP3_HI 27
+#define STRAP3_SZ 1
+#define GPIO_TEST_2_ID_MSK 0x10000000
+#define GPIO_TEST_2_ID_I_MSK 0xefffffff
+#define GPIO_TEST_2_ID_SFT 28
+#define GPIO_TEST_2_ID_HI 28
+#define GPIO_TEST_2_ID_SZ 1
+#define PAD22_OE_MSK 0x00000001
+#define PAD22_OE_I_MSK 0xfffffffe
+#define PAD22_OE_SFT 0
+#define PAD22_OE_HI 0
+#define PAD22_OE_SZ 1
+#define PAD22_PE_MSK 0x00000002
+#define PAD22_PE_I_MSK 0xfffffffd
+#define PAD22_PE_SFT 1
+#define PAD22_PE_HI 1
+#define PAD22_PE_SZ 1
+#define PAD22_DS_MSK 0x00000004
+#define PAD22_DS_I_MSK 0xfffffffb
+#define PAD22_DS_SFT 2
+#define PAD22_DS_HI 2
+#define PAD22_DS_SZ 1
+#define PAD22_IE_MSK 0x00000008
+#define PAD22_IE_I_MSK 0xfffffff7
+#define PAD22_IE_SFT 3
+#define PAD22_IE_HI 3
+#define PAD22_IE_SZ 1
+#define PAD22_SEL_I_MSK 0x00000070
+#define PAD22_SEL_I_I_MSK 0xffffff8f
+#define PAD22_SEL_I_SFT 4
+#define PAD22_SEL_I_HI 6
+#define PAD22_SEL_I_SZ 3
+#define PAD22_OD_MSK 0x00000100
+#define PAD22_OD_I_MSK 0xfffffeff
+#define PAD22_OD_SFT 8
+#define PAD22_OD_HI 8
+#define PAD22_OD_SZ 1
+#define PAD22_SEL_O_MSK 0x00007000
+#define PAD22_SEL_O_I_MSK 0xffff8fff
+#define PAD22_SEL_O_SFT 12
+#define PAD22_SEL_O_HI 14
+#define PAD22_SEL_O_SZ 3
+#define PAD22_SEL_OE_MSK 0x00100000
+#define PAD22_SEL_OE_I_MSK 0xffefffff
+#define PAD22_SEL_OE_SFT 20
+#define PAD22_SEL_OE_HI 20
+#define PAD22_SEL_OE_SZ 1
+#define GPIO_TEST_3_ID_MSK 0x10000000
+#define GPIO_TEST_3_ID_I_MSK 0xefffffff
+#define GPIO_TEST_3_ID_SFT 28
+#define GPIO_TEST_3_ID_HI 28
+#define GPIO_TEST_3_ID_SZ 1
+#define PAD24_OE_MSK 0x00000001
+#define PAD24_OE_I_MSK 0xfffffffe
+#define PAD24_OE_SFT 0
+#define PAD24_OE_HI 0
+#define PAD24_OE_SZ 1
+#define PAD24_PE_MSK 0x00000002
+#define PAD24_PE_I_MSK 0xfffffffd
+#define PAD24_PE_SFT 1
+#define PAD24_PE_HI 1
+#define PAD24_PE_SZ 1
+#define PAD24_DS_MSK 0x00000004
+#define PAD24_DS_I_MSK 0xfffffffb
+#define PAD24_DS_SFT 2
+#define PAD24_DS_HI 2
+#define PAD24_DS_SZ 1
+#define PAD24_IE_MSK 0x00000008
+#define PAD24_IE_I_MSK 0xfffffff7
+#define PAD24_IE_SFT 3
+#define PAD24_IE_HI 3
+#define PAD24_IE_SZ 1
+#define PAD24_SEL_I_MSK 0x00000030
+#define PAD24_SEL_I_I_MSK 0xffffffcf
+#define PAD24_SEL_I_SFT 4
+#define PAD24_SEL_I_HI 5
+#define PAD24_SEL_I_SZ 2
+#define PAD24_OD_MSK 0x00000100
+#define PAD24_OD_I_MSK 0xfffffeff
+#define PAD24_OD_SFT 8
+#define PAD24_OD_HI 8
+#define PAD24_OD_SZ 1
+#define PAD24_SEL_O_MSK 0x00007000
+#define PAD24_SEL_O_I_MSK 0xffff8fff
+#define PAD24_SEL_O_SFT 12
+#define PAD24_SEL_O_HI 14
+#define PAD24_SEL_O_SZ 3
+#define GPIO_TEST_4_ID_MSK 0x10000000
+#define GPIO_TEST_4_ID_I_MSK 0xefffffff
+#define GPIO_TEST_4_ID_SFT 28
+#define GPIO_TEST_4_ID_HI 28
+#define GPIO_TEST_4_ID_SZ 1
+#define PAD25_OE_MSK 0x00000001
+#define PAD25_OE_I_MSK 0xfffffffe
+#define PAD25_OE_SFT 0
+#define PAD25_OE_HI 0
+#define PAD25_OE_SZ 1
+#define PAD25_PE_MSK 0x00000002
+#define PAD25_PE_I_MSK 0xfffffffd
+#define PAD25_PE_SFT 1
+#define PAD25_PE_HI 1
+#define PAD25_PE_SZ 1
+#define PAD25_DS_MSK 0x00000004
+#define PAD25_DS_I_MSK 0xfffffffb
+#define PAD25_DS_SFT 2
+#define PAD25_DS_HI 2
+#define PAD25_DS_SZ 1
+#define PAD25_IE_MSK 0x00000008
+#define PAD25_IE_I_MSK 0xfffffff7
+#define PAD25_IE_SFT 3
+#define PAD25_IE_HI 3
+#define PAD25_IE_SZ 1
+#define PAD25_SEL_I_MSK 0x00000070
+#define PAD25_SEL_I_I_MSK 0xffffff8f
+#define PAD25_SEL_I_SFT 4
+#define PAD25_SEL_I_HI 6
+#define PAD25_SEL_I_SZ 3
+#define PAD25_OD_MSK 0x00000100
+#define PAD25_OD_I_MSK 0xfffffeff
+#define PAD25_OD_SFT 8
+#define PAD25_OD_HI 8
+#define PAD25_OD_SZ 1
+#define PAD25_SEL_O_MSK 0x00007000
+#define PAD25_SEL_O_I_MSK 0xffff8fff
+#define PAD25_SEL_O_SFT 12
+#define PAD25_SEL_O_HI 14
+#define PAD25_SEL_O_SZ 3
+#define PAD25_SEL_OE_MSK 0x00100000
+#define PAD25_SEL_OE_I_MSK 0xffefffff
+#define PAD25_SEL_OE_SFT 20
+#define PAD25_SEL_OE_HI 20
+#define PAD25_SEL_OE_SZ 1
+#define STRAP1_MSK 0x08000000
+#define STRAP1_I_MSK 0xf7ffffff
+#define STRAP1_SFT 27
+#define STRAP1_HI 27
+#define STRAP1_SZ 1
+#define GPIO_1_ID_MSK 0x10000000
+#define GPIO_1_ID_I_MSK 0xefffffff
+#define GPIO_1_ID_SFT 28
+#define GPIO_1_ID_HI 28
+#define GPIO_1_ID_SZ 1
+#define PAD27_OE_MSK 0x00000001
+#define PAD27_OE_I_MSK 0xfffffffe
+#define PAD27_OE_SFT 0
+#define PAD27_OE_HI 0
+#define PAD27_OE_SZ 1
+#define PAD27_PE_MSK 0x00000002
+#define PAD27_PE_I_MSK 0xfffffffd
+#define PAD27_PE_SFT 1
+#define PAD27_PE_HI 1
+#define PAD27_PE_SZ 1
+#define PAD27_DS_MSK 0x00000004
+#define PAD27_DS_I_MSK 0xfffffffb
+#define PAD27_DS_SFT 2
+#define PAD27_DS_HI 2
+#define PAD27_DS_SZ 1
+#define PAD27_IE_MSK 0x00000008
+#define PAD27_IE_I_MSK 0xfffffff7
+#define PAD27_IE_SFT 3
+#define PAD27_IE_HI 3
+#define PAD27_IE_SZ 1
+#define PAD27_SEL_I_MSK 0x00000070
+#define PAD27_SEL_I_I_MSK 0xffffff8f
+#define PAD27_SEL_I_SFT 4
+#define PAD27_SEL_I_HI 6
+#define PAD27_SEL_I_SZ 3
+#define PAD27_OD_MSK 0x00000100
+#define PAD27_OD_I_MSK 0xfffffeff
+#define PAD27_OD_SFT 8
+#define PAD27_OD_HI 8
+#define PAD27_OD_SZ 1
+#define PAD27_SEL_O_MSK 0x00007000
+#define PAD27_SEL_O_I_MSK 0xffff8fff
+#define PAD27_SEL_O_SFT 12
+#define PAD27_SEL_O_HI 14
+#define PAD27_SEL_O_SZ 3
+#define GPIO_2_ID_MSK 0x10000000
+#define GPIO_2_ID_I_MSK 0xefffffff
+#define GPIO_2_ID_SFT 28
+#define GPIO_2_ID_HI 28
+#define GPIO_2_ID_SZ 1
+#define PAD28_OE_MSK 0x00000001
+#define PAD28_OE_I_MSK 0xfffffffe
+#define PAD28_OE_SFT 0
+#define PAD28_OE_HI 0
+#define PAD28_OE_SZ 1
+#define PAD28_PE_MSK 0x00000002
+#define PAD28_PE_I_MSK 0xfffffffd
+#define PAD28_PE_SFT 1
+#define PAD28_PE_HI 1
+#define PAD28_PE_SZ 1
+#define PAD28_DS_MSK 0x00000004
+#define PAD28_DS_I_MSK 0xfffffffb
+#define PAD28_DS_SFT 2
+#define PAD28_DS_HI 2
+#define PAD28_DS_SZ 1
+#define PAD28_IE_MSK 0x00000008
+#define PAD28_IE_I_MSK 0xfffffff7
+#define PAD28_IE_SFT 3
+#define PAD28_IE_HI 3
+#define PAD28_IE_SZ 1
+#define PAD28_SEL_I_MSK 0x00000070
+#define PAD28_SEL_I_I_MSK 0xffffff8f
+#define PAD28_SEL_I_SFT 4
+#define PAD28_SEL_I_HI 6
+#define PAD28_SEL_I_SZ 3
+#define PAD28_OD_MSK 0x00000100
+#define PAD28_OD_I_MSK 0xfffffeff
+#define PAD28_OD_SFT 8
+#define PAD28_OD_HI 8
+#define PAD28_OD_SZ 1
+#define PAD28_SEL_O_MSK 0x0000f000
+#define PAD28_SEL_O_I_MSK 0xffff0fff
+#define PAD28_SEL_O_SFT 12
+#define PAD28_SEL_O_HI 15
+#define PAD28_SEL_O_SZ 4
+#define PAD28_SEL_OE_MSK 0x00100000
+#define PAD28_SEL_OE_I_MSK 0xffefffff
+#define PAD28_SEL_OE_SFT 20
+#define PAD28_SEL_OE_HI 20
+#define PAD28_SEL_OE_SZ 1
+#define GPIO_3_ID_MSK 0x10000000
+#define GPIO_3_ID_I_MSK 0xefffffff
+#define GPIO_3_ID_SFT 28
+#define GPIO_3_ID_HI 28
+#define GPIO_3_ID_SZ 1
+#define PAD29_OE_MSK 0x00000001
+#define PAD29_OE_I_MSK 0xfffffffe
+#define PAD29_OE_SFT 0
+#define PAD29_OE_HI 0
+#define PAD29_OE_SZ 1
+#define PAD29_PE_MSK 0x00000002
+#define PAD29_PE_I_MSK 0xfffffffd
+#define PAD29_PE_SFT 1
+#define PAD29_PE_HI 1
+#define PAD29_PE_SZ 1
+#define PAD29_DS_MSK 0x00000004
+#define PAD29_DS_I_MSK 0xfffffffb
+#define PAD29_DS_SFT 2
+#define PAD29_DS_HI 2
+#define PAD29_DS_SZ 1
+#define PAD29_IE_MSK 0x00000008
+#define PAD29_IE_I_MSK 0xfffffff7
+#define PAD29_IE_SFT 3
+#define PAD29_IE_HI 3
+#define PAD29_IE_SZ 1
+#define PAD29_SEL_I_MSK 0x00000070
+#define PAD29_SEL_I_I_MSK 0xffffff8f
+#define PAD29_SEL_I_SFT 4
+#define PAD29_SEL_I_HI 6
+#define PAD29_SEL_I_SZ 3
+#define PAD29_OD_MSK 0x00000100
+#define PAD29_OD_I_MSK 0xfffffeff
+#define PAD29_OD_SFT 8
+#define PAD29_OD_HI 8
+#define PAD29_OD_SZ 1
+#define PAD29_SEL_O_MSK 0x00007000
+#define PAD29_SEL_O_I_MSK 0xffff8fff
+#define PAD29_SEL_O_SFT 12
+#define PAD29_SEL_O_HI 14
+#define PAD29_SEL_O_SZ 3
+#define GPIO_TEST_5_ID_MSK 0x10000000
+#define GPIO_TEST_5_ID_I_MSK 0xefffffff
+#define GPIO_TEST_5_ID_SFT 28
+#define GPIO_TEST_5_ID_HI 28
+#define GPIO_TEST_5_ID_SZ 1
+#define PAD30_OE_MSK 0x00000001
+#define PAD30_OE_I_MSK 0xfffffffe
+#define PAD30_OE_SFT 0
+#define PAD30_OE_HI 0
+#define PAD30_OE_SZ 1
+#define PAD30_PE_MSK 0x00000002
+#define PAD30_PE_I_MSK 0xfffffffd
+#define PAD30_PE_SFT 1
+#define PAD30_PE_HI 1
+#define PAD30_PE_SZ 1
+#define PAD30_DS_MSK 0x00000004
+#define PAD30_DS_I_MSK 0xfffffffb
+#define PAD30_DS_SFT 2
+#define PAD30_DS_HI 2
+#define PAD30_DS_SZ 1
+#define PAD30_IE_MSK 0x00000008
+#define PAD30_IE_I_MSK 0xfffffff7
+#define PAD30_IE_SFT 3
+#define PAD30_IE_HI 3
+#define PAD30_IE_SZ 1
+#define PAD30_SEL_I_MSK 0x00000030
+#define PAD30_SEL_I_I_MSK 0xffffffcf
+#define PAD30_SEL_I_SFT 4
+#define PAD30_SEL_I_HI 5
+#define PAD30_SEL_I_SZ 2
+#define PAD30_OD_MSK 0x00000100
+#define PAD30_OD_I_MSK 0xfffffeff
+#define PAD30_OD_SFT 8
+#define PAD30_OD_HI 8
+#define PAD30_OD_SZ 1
+#define PAD30_SEL_O_MSK 0x00003000
+#define PAD30_SEL_O_I_MSK 0xffffcfff
+#define PAD30_SEL_O_SFT 12
+#define PAD30_SEL_O_HI 13
+#define PAD30_SEL_O_SZ 2
+#define TEST_6_ID_MSK 0x10000000
+#define TEST_6_ID_I_MSK 0xefffffff
+#define TEST_6_ID_SFT 28
+#define TEST_6_ID_HI 28
+#define TEST_6_ID_SZ 1
+#define PAD31_OE_MSK 0x00000001
+#define PAD31_OE_I_MSK 0xfffffffe
+#define PAD31_OE_SFT 0
+#define PAD31_OE_HI 0
+#define PAD31_OE_SZ 1
+#define PAD31_PE_MSK 0x00000002
+#define PAD31_PE_I_MSK 0xfffffffd
+#define PAD31_PE_SFT 1
+#define PAD31_PE_HI 1
+#define PAD31_PE_SZ 1
+#define PAD31_DS_MSK 0x00000004
+#define PAD31_DS_I_MSK 0xfffffffb
+#define PAD31_DS_SFT 2
+#define PAD31_DS_HI 2
+#define PAD31_DS_SZ 1
+#define PAD31_IE_MSK 0x00000008
+#define PAD31_IE_I_MSK 0xfffffff7
+#define PAD31_IE_SFT 3
+#define PAD31_IE_HI 3
+#define PAD31_IE_SZ 1
+#define PAD31_SEL_I_MSK 0x00000030
+#define PAD31_SEL_I_I_MSK 0xffffffcf
+#define PAD31_SEL_I_SFT 4
+#define PAD31_SEL_I_HI 5
+#define PAD31_SEL_I_SZ 2
+#define PAD31_OD_MSK 0x00000100
+#define PAD31_OD_I_MSK 0xfffffeff
+#define PAD31_OD_SFT 8
+#define PAD31_OD_HI 8
+#define PAD31_OD_SZ 1
+#define PAD31_SEL_O_MSK 0x00003000
+#define PAD31_SEL_O_I_MSK 0xffffcfff
+#define PAD31_SEL_O_SFT 12
+#define PAD31_SEL_O_HI 13
+#define PAD31_SEL_O_SZ 2
+#define TEST_7_ID_MSK 0x10000000
+#define TEST_7_ID_I_MSK 0xefffffff
+#define TEST_7_ID_SFT 28
+#define TEST_7_ID_HI 28
+#define TEST_7_ID_SZ 1
+#define PAD32_OE_MSK 0x00000001
+#define PAD32_OE_I_MSK 0xfffffffe
+#define PAD32_OE_SFT 0
+#define PAD32_OE_HI 0
+#define PAD32_OE_SZ 1
+#define PAD32_PE_MSK 0x00000002
+#define PAD32_PE_I_MSK 0xfffffffd
+#define PAD32_PE_SFT 1
+#define PAD32_PE_HI 1
+#define PAD32_PE_SZ 1
+#define PAD32_DS_MSK 0x00000004
+#define PAD32_DS_I_MSK 0xfffffffb
+#define PAD32_DS_SFT 2
+#define PAD32_DS_HI 2
+#define PAD32_DS_SZ 1
+#define PAD32_IE_MSK 0x00000008
+#define PAD32_IE_I_MSK 0xfffffff7
+#define PAD32_IE_SFT 3
+#define PAD32_IE_HI 3
+#define PAD32_IE_SZ 1
+#define PAD32_SEL_I_MSK 0x00000030
+#define PAD32_SEL_I_I_MSK 0xffffffcf
+#define PAD32_SEL_I_SFT 4
+#define PAD32_SEL_I_HI 5
+#define PAD32_SEL_I_SZ 2
+#define PAD32_OD_MSK 0x00000100
+#define PAD32_OD_I_MSK 0xfffffeff
+#define PAD32_OD_SFT 8
+#define PAD32_OD_HI 8
+#define PAD32_OD_SZ 1
+#define PAD32_SEL_O_MSK 0x00003000
+#define PAD32_SEL_O_I_MSK 0xffffcfff
+#define PAD32_SEL_O_SFT 12
+#define PAD32_SEL_O_HI 13
+#define PAD32_SEL_O_SZ 2
+#define TEST_8_ID_MSK 0x10000000
+#define TEST_8_ID_I_MSK 0xefffffff
+#define TEST_8_ID_SFT 28
+#define TEST_8_ID_HI 28
+#define TEST_8_ID_SZ 1
+#define PAD33_OE_MSK 0x00000001
+#define PAD33_OE_I_MSK 0xfffffffe
+#define PAD33_OE_SFT 0
+#define PAD33_OE_HI 0
+#define PAD33_OE_SZ 1
+#define PAD33_PE_MSK 0x00000002
+#define PAD33_PE_I_MSK 0xfffffffd
+#define PAD33_PE_SFT 1
+#define PAD33_PE_HI 1
+#define PAD33_PE_SZ 1
+#define PAD33_DS_MSK 0x00000004
+#define PAD33_DS_I_MSK 0xfffffffb
+#define PAD33_DS_SFT 2
+#define PAD33_DS_HI 2
+#define PAD33_DS_SZ 1
+#define PAD33_IE_MSK 0x00000008
+#define PAD33_IE_I_MSK 0xfffffff7
+#define PAD33_IE_SFT 3
+#define PAD33_IE_HI 3
+#define PAD33_IE_SZ 1
+#define PAD33_SEL_I_MSK 0x00000030
+#define PAD33_SEL_I_I_MSK 0xffffffcf
+#define PAD33_SEL_I_SFT 4
+#define PAD33_SEL_I_HI 5
+#define PAD33_SEL_I_SZ 2
+#define PAD33_OD_MSK 0x00000100
+#define PAD33_OD_I_MSK 0xfffffeff
+#define PAD33_OD_SFT 8
+#define PAD33_OD_HI 8
+#define PAD33_OD_SZ 1
+#define PAD33_SEL_O_MSK 0x00003000
+#define PAD33_SEL_O_I_MSK 0xffffcfff
+#define PAD33_SEL_O_SFT 12
+#define PAD33_SEL_O_HI 13
+#define PAD33_SEL_O_SZ 2
+#define TEST_9_ID_MSK 0x10000000
+#define TEST_9_ID_I_MSK 0xefffffff
+#define TEST_9_ID_SFT 28
+#define TEST_9_ID_HI 28
+#define TEST_9_ID_SZ 1
+#define PAD34_OE_MSK 0x00000001
+#define PAD34_OE_I_MSK 0xfffffffe
+#define PAD34_OE_SFT 0
+#define PAD34_OE_HI 0
+#define PAD34_OE_SZ 1
+#define PAD34_PE_MSK 0x00000002
+#define PAD34_PE_I_MSK 0xfffffffd
+#define PAD34_PE_SFT 1
+#define PAD34_PE_HI 1
+#define PAD34_PE_SZ 1
+#define PAD34_DS_MSK 0x00000004
+#define PAD34_DS_I_MSK 0xfffffffb
+#define PAD34_DS_SFT 2
+#define PAD34_DS_HI 2
+#define PAD34_DS_SZ 1
+#define PAD34_IE_MSK 0x00000008
+#define PAD34_IE_I_MSK 0xfffffff7
+#define PAD34_IE_SFT 3
+#define PAD34_IE_HI 3
+#define PAD34_IE_SZ 1
+#define PAD34_SEL_I_MSK 0x00000030
+#define PAD34_SEL_I_I_MSK 0xffffffcf
+#define PAD34_SEL_I_SFT 4
+#define PAD34_SEL_I_HI 5
+#define PAD34_SEL_I_SZ 2
+#define PAD34_OD_MSK 0x00000100
+#define PAD34_OD_I_MSK 0xfffffeff
+#define PAD34_OD_SFT 8
+#define PAD34_OD_HI 8
+#define PAD34_OD_SZ 1
+#define PAD34_SEL_O_MSK 0x00003000
+#define PAD34_SEL_O_I_MSK 0xffffcfff
+#define PAD34_SEL_O_SFT 12
+#define PAD34_SEL_O_HI 13
+#define PAD34_SEL_O_SZ 2
+#define TEST_10_ID_MSK 0x10000000
+#define TEST_10_ID_I_MSK 0xefffffff
+#define TEST_10_ID_SFT 28
+#define TEST_10_ID_HI 28
+#define TEST_10_ID_SZ 1
+#define PAD42_OE_MSK 0x00000001
+#define PAD42_OE_I_MSK 0xfffffffe
+#define PAD42_OE_SFT 0
+#define PAD42_OE_HI 0
+#define PAD42_OE_SZ 1
+#define PAD42_PE_MSK 0x00000002
+#define PAD42_PE_I_MSK 0xfffffffd
+#define PAD42_PE_SFT 1
+#define PAD42_PE_HI 1
+#define PAD42_PE_SZ 1
+#define PAD42_DS_MSK 0x00000004
+#define PAD42_DS_I_MSK 0xfffffffb
+#define PAD42_DS_SFT 2
+#define PAD42_DS_HI 2
+#define PAD42_DS_SZ 1
+#define PAD42_IE_MSK 0x00000008
+#define PAD42_IE_I_MSK 0xfffffff7
+#define PAD42_IE_SFT 3
+#define PAD42_IE_HI 3
+#define PAD42_IE_SZ 1
+#define PAD42_SEL_I_MSK 0x00000030
+#define PAD42_SEL_I_I_MSK 0xffffffcf
+#define PAD42_SEL_I_SFT 4
+#define PAD42_SEL_I_HI 5
+#define PAD42_SEL_I_SZ 2
+#define PAD42_OD_MSK 0x00000100
+#define PAD42_OD_I_MSK 0xfffffeff
+#define PAD42_OD_SFT 8
+#define PAD42_OD_HI 8
+#define PAD42_OD_SZ 1
+#define PAD42_SEL_O_MSK 0x00001000
+#define PAD42_SEL_O_I_MSK 0xffffefff
+#define PAD42_SEL_O_SFT 12
+#define PAD42_SEL_O_HI 12
+#define PAD42_SEL_O_SZ 1
+#define TEST_11_ID_MSK 0x10000000
+#define TEST_11_ID_I_MSK 0xefffffff
+#define TEST_11_ID_SFT 28
+#define TEST_11_ID_HI 28
+#define TEST_11_ID_SZ 1
+#define PAD43_OE_MSK 0x00000001
+#define PAD43_OE_I_MSK 0xfffffffe
+#define PAD43_OE_SFT 0
+#define PAD43_OE_HI 0
+#define PAD43_OE_SZ 1
+#define PAD43_PE_MSK 0x00000002
+#define PAD43_PE_I_MSK 0xfffffffd
+#define PAD43_PE_SFT 1
+#define PAD43_PE_HI 1
+#define PAD43_PE_SZ 1
+#define PAD43_DS_MSK 0x00000004
+#define PAD43_DS_I_MSK 0xfffffffb
+#define PAD43_DS_SFT 2
+#define PAD43_DS_HI 2
+#define PAD43_DS_SZ 1
+#define PAD43_IE_MSK 0x00000008
+#define PAD43_IE_I_MSK 0xfffffff7
+#define PAD43_IE_SFT 3
+#define PAD43_IE_HI 3
+#define PAD43_IE_SZ 1
+#define PAD43_SEL_I_MSK 0x00000030
+#define PAD43_SEL_I_I_MSK 0xffffffcf
+#define PAD43_SEL_I_SFT 4
+#define PAD43_SEL_I_HI 5
+#define PAD43_SEL_I_SZ 2
+#define PAD43_OD_MSK 0x00000100
+#define PAD43_OD_I_MSK 0xfffffeff
+#define PAD43_OD_SFT 8
+#define PAD43_OD_HI 8
+#define PAD43_OD_SZ 1
+#define PAD43_SEL_O_MSK 0x00001000
+#define PAD43_SEL_O_I_MSK 0xffffefff
+#define PAD43_SEL_O_SFT 12
+#define PAD43_SEL_O_HI 12
+#define PAD43_SEL_O_SZ 1
+#define TEST_12_ID_MSK 0x10000000
+#define TEST_12_ID_I_MSK 0xefffffff
+#define TEST_12_ID_SFT 28
+#define TEST_12_ID_HI 28
+#define TEST_12_ID_SZ 1
+#define PAD44_OE_MSK 0x00000001
+#define PAD44_OE_I_MSK 0xfffffffe
+#define PAD44_OE_SFT 0
+#define PAD44_OE_HI 0
+#define PAD44_OE_SZ 1
+#define PAD44_PE_MSK 0x00000002
+#define PAD44_PE_I_MSK 0xfffffffd
+#define PAD44_PE_SFT 1
+#define PAD44_PE_HI 1
+#define PAD44_PE_SZ 1
+#define PAD44_DS_MSK 0x00000004
+#define PAD44_DS_I_MSK 0xfffffffb
+#define PAD44_DS_SFT 2
+#define PAD44_DS_HI 2
+#define PAD44_DS_SZ 1
+#define PAD44_IE_MSK 0x00000008
+#define PAD44_IE_I_MSK 0xfffffff7
+#define PAD44_IE_SFT 3
+#define PAD44_IE_HI 3
+#define PAD44_IE_SZ 1
+#define PAD44_SEL_I_MSK 0x00000030
+#define PAD44_SEL_I_I_MSK 0xffffffcf
+#define PAD44_SEL_I_SFT 4
+#define PAD44_SEL_I_HI 5
+#define PAD44_SEL_I_SZ 2
+#define PAD44_OD_MSK 0x00000100
+#define PAD44_OD_I_MSK 0xfffffeff
+#define PAD44_OD_SFT 8
+#define PAD44_OD_HI 8
+#define PAD44_OD_SZ 1
+#define PAD44_SEL_O_MSK 0x00003000
+#define PAD44_SEL_O_I_MSK 0xffffcfff
+#define PAD44_SEL_O_SFT 12
+#define PAD44_SEL_O_HI 13
+#define PAD44_SEL_O_SZ 2
+#define TEST_13_ID_MSK 0x10000000
+#define TEST_13_ID_I_MSK 0xefffffff
+#define TEST_13_ID_SFT 28
+#define TEST_13_ID_HI 28
+#define TEST_13_ID_SZ 1
+#define PAD45_OE_MSK 0x00000001
+#define PAD45_OE_I_MSK 0xfffffffe
+#define PAD45_OE_SFT 0
+#define PAD45_OE_HI 0
+#define PAD45_OE_SZ 1
+#define PAD45_PE_MSK 0x00000002
+#define PAD45_PE_I_MSK 0xfffffffd
+#define PAD45_PE_SFT 1
+#define PAD45_PE_HI 1
+#define PAD45_PE_SZ 1
+#define PAD45_DS_MSK 0x00000004
+#define PAD45_DS_I_MSK 0xfffffffb
+#define PAD45_DS_SFT 2
+#define PAD45_DS_HI 2
+#define PAD45_DS_SZ 1
+#define PAD45_IE_MSK 0x00000008
+#define PAD45_IE_I_MSK 0xfffffff7
+#define PAD45_IE_SFT 3
+#define PAD45_IE_HI 3
+#define PAD45_IE_SZ 1
+#define PAD45_SEL_I_MSK 0x00000030
+#define PAD45_SEL_I_I_MSK 0xffffffcf
+#define PAD45_SEL_I_SFT 4
+#define PAD45_SEL_I_HI 5
+#define PAD45_SEL_I_SZ 2
+#define PAD45_OD_MSK 0x00000100
+#define PAD45_OD_I_MSK 0xfffffeff
+#define PAD45_OD_SFT 8
+#define PAD45_OD_HI 8
+#define PAD45_OD_SZ 1
+#define PAD45_SEL_O_MSK 0x00003000
+#define PAD45_SEL_O_I_MSK 0xffffcfff
+#define PAD45_SEL_O_SFT 12
+#define PAD45_SEL_O_HI 13
+#define PAD45_SEL_O_SZ 2
+#define TEST_14_ID_MSK 0x10000000
+#define TEST_14_ID_I_MSK 0xefffffff
+#define TEST_14_ID_SFT 28
+#define TEST_14_ID_HI 28
+#define TEST_14_ID_SZ 1
+#define PAD46_OE_MSK 0x00000001
+#define PAD46_OE_I_MSK 0xfffffffe
+#define PAD46_OE_SFT 0
+#define PAD46_OE_HI 0
+#define PAD46_OE_SZ 1
+#define PAD46_PE_MSK 0x00000002
+#define PAD46_PE_I_MSK 0xfffffffd
+#define PAD46_PE_SFT 1
+#define PAD46_PE_HI 1
+#define PAD46_PE_SZ 1
+#define PAD46_DS_MSK 0x00000004
+#define PAD46_DS_I_MSK 0xfffffffb
+#define PAD46_DS_SFT 2
+#define PAD46_DS_HI 2
+#define PAD46_DS_SZ 1
+#define PAD46_IE_MSK 0x00000008
+#define PAD46_IE_I_MSK 0xfffffff7
+#define PAD46_IE_SFT 3
+#define PAD46_IE_HI 3
+#define PAD46_IE_SZ 1
+#define PAD46_SEL_I_MSK 0x00000030
+#define PAD46_SEL_I_I_MSK 0xffffffcf
+#define PAD46_SEL_I_SFT 4
+#define PAD46_SEL_I_HI 5
+#define PAD46_SEL_I_SZ 2
+#define PAD46_OD_MSK 0x00000100
+#define PAD46_OD_I_MSK 0xfffffeff
+#define PAD46_OD_SFT 8
+#define PAD46_OD_HI 8
+#define PAD46_OD_SZ 1
+#define PAD46_SEL_O_MSK 0x00003000
+#define PAD46_SEL_O_I_MSK 0xffffcfff
+#define PAD46_SEL_O_SFT 12
+#define PAD46_SEL_O_HI 13
+#define PAD46_SEL_O_SZ 2
+#define TEST_15_ID_MSK 0x10000000
+#define TEST_15_ID_I_MSK 0xefffffff
+#define TEST_15_ID_SFT 28
+#define TEST_15_ID_HI 28
+#define TEST_15_ID_SZ 1
+#define PAD47_OE_MSK 0x00000001
+#define PAD47_OE_I_MSK 0xfffffffe
+#define PAD47_OE_SFT 0
+#define PAD47_OE_HI 0
+#define PAD47_OE_SZ 1
+#define PAD47_PE_MSK 0x00000002
+#define PAD47_PE_I_MSK 0xfffffffd
+#define PAD47_PE_SFT 1
+#define PAD47_PE_HI 1
+#define PAD47_PE_SZ 1
+#define PAD47_DS_MSK 0x00000004
+#define PAD47_DS_I_MSK 0xfffffffb
+#define PAD47_DS_SFT 2
+#define PAD47_DS_HI 2
+#define PAD47_DS_SZ 1
+#define PAD47_SEL_I_MSK 0x00000030
+#define PAD47_SEL_I_I_MSK 0xffffffcf
+#define PAD47_SEL_I_SFT 4
+#define PAD47_SEL_I_HI 5
+#define PAD47_SEL_I_SZ 2
+#define PAD47_OD_MSK 0x00000100
+#define PAD47_OD_I_MSK 0xfffffeff
+#define PAD47_OD_SFT 8
+#define PAD47_OD_HI 8
+#define PAD47_OD_SZ 1
+#define PAD47_SEL_O_MSK 0x00003000
+#define PAD47_SEL_O_I_MSK 0xffffcfff
+#define PAD47_SEL_O_SFT 12
+#define PAD47_SEL_O_HI 13
+#define PAD47_SEL_O_SZ 2
+#define PAD47_SEL_OE_MSK 0x00100000
+#define PAD47_SEL_OE_I_MSK 0xffefffff
+#define PAD47_SEL_OE_SFT 20
+#define PAD47_SEL_OE_HI 20
+#define PAD47_SEL_OE_SZ 1
+#define GPIO_9_ID_MSK 0x10000000
+#define GPIO_9_ID_I_MSK 0xefffffff
+#define GPIO_9_ID_SFT 28
+#define GPIO_9_ID_HI 28
+#define GPIO_9_ID_SZ 1
+#define PAD48_OE_MSK 0x00000001
+#define PAD48_OE_I_MSK 0xfffffffe
+#define PAD48_OE_SFT 0
+#define PAD48_OE_HI 0
+#define PAD48_OE_SZ 1
+#define PAD48_PE_MSK 0x00000002
+#define PAD48_PE_I_MSK 0xfffffffd
+#define PAD48_PE_SFT 1
+#define PAD48_PE_HI 1
+#define PAD48_PE_SZ 1
+#define PAD48_DS_MSK 0x00000004
+#define PAD48_DS_I_MSK 0xfffffffb
+#define PAD48_DS_SFT 2
+#define PAD48_DS_HI 2
+#define PAD48_DS_SZ 1
+#define PAD48_IE_MSK 0x00000008
+#define PAD48_IE_I_MSK 0xfffffff7
+#define PAD48_IE_SFT 3
+#define PAD48_IE_HI 3
+#define PAD48_IE_SZ 1
+#define PAD48_SEL_I_MSK 0x00000070
+#define PAD48_SEL_I_I_MSK 0xffffff8f
+#define PAD48_SEL_I_SFT 4
+#define PAD48_SEL_I_HI 6
+#define PAD48_SEL_I_SZ 3
+#define PAD48_OD_MSK 0x00000100
+#define PAD48_OD_I_MSK 0xfffffeff
+#define PAD48_OD_SFT 8
+#define PAD48_OD_HI 8
+#define PAD48_OD_SZ 1
+#define PAD48_PE_SEL_MSK 0x00000800
+#define PAD48_PE_SEL_I_MSK 0xfffff7ff
+#define PAD48_PE_SEL_SFT 11
+#define PAD48_PE_SEL_HI 11
+#define PAD48_PE_SEL_SZ 1
+#define PAD48_SEL_O_MSK 0x00003000
+#define PAD48_SEL_O_I_MSK 0xffffcfff
+#define PAD48_SEL_O_SFT 12
+#define PAD48_SEL_O_HI 13
+#define PAD48_SEL_O_SZ 2
+#define PAD48_SEL_OE_MSK 0x00100000
+#define PAD48_SEL_OE_I_MSK 0xffefffff
+#define PAD48_SEL_OE_SFT 20
+#define PAD48_SEL_OE_HI 20
+#define PAD48_SEL_OE_SZ 1
+#define GPIO_10_ID_MSK 0x10000000
+#define GPIO_10_ID_I_MSK 0xefffffff
+#define GPIO_10_ID_SFT 28
+#define GPIO_10_ID_HI 28
+#define GPIO_10_ID_SZ 1
+#define PAD49_OE_MSK 0x00000001
+#define PAD49_OE_I_MSK 0xfffffffe
+#define PAD49_OE_SFT 0
+#define PAD49_OE_HI 0
+#define PAD49_OE_SZ 1
+#define PAD49_PE_MSK 0x00000002
+#define PAD49_PE_I_MSK 0xfffffffd
+#define PAD49_PE_SFT 1
+#define PAD49_PE_HI 1
+#define PAD49_PE_SZ 1
+#define PAD49_DS_MSK 0x00000004
+#define PAD49_DS_I_MSK 0xfffffffb
+#define PAD49_DS_SFT 2
+#define PAD49_DS_HI 2
+#define PAD49_DS_SZ 1
+#define PAD49_IE_MSK 0x00000008
+#define PAD49_IE_I_MSK 0xfffffff7
+#define PAD49_IE_SFT 3
+#define PAD49_IE_HI 3
+#define PAD49_IE_SZ 1
+#define PAD49_SEL_I_MSK 0x00000070
+#define PAD49_SEL_I_I_MSK 0xffffff8f
+#define PAD49_SEL_I_SFT 4
+#define PAD49_SEL_I_HI 6
+#define PAD49_SEL_I_SZ 3
+#define PAD49_OD_MSK 0x00000100
+#define PAD49_OD_I_MSK 0xfffffeff
+#define PAD49_OD_SFT 8
+#define PAD49_OD_HI 8
+#define PAD49_OD_SZ 1
+#define PAD49_SEL_O_MSK 0x00003000
+#define PAD49_SEL_O_I_MSK 0xffffcfff
+#define PAD49_SEL_O_SFT 12
+#define PAD49_SEL_O_HI 13
+#define PAD49_SEL_O_SZ 2
+#define PAD49_SEL_OE_MSK 0x00100000
+#define PAD49_SEL_OE_I_MSK 0xffefffff
+#define PAD49_SEL_OE_SFT 20
+#define PAD49_SEL_OE_HI 20
+#define PAD49_SEL_OE_SZ 1
+#define GPIO_11_ID_MSK 0x10000000
+#define GPIO_11_ID_I_MSK 0xefffffff
+#define GPIO_11_ID_SFT 28
+#define GPIO_11_ID_HI 28
+#define GPIO_11_ID_SZ 1
+#define PAD50_OE_MSK 0x00000001
+#define PAD50_OE_I_MSK 0xfffffffe
+#define PAD50_OE_SFT 0
+#define PAD50_OE_HI 0
+#define PAD50_OE_SZ 1
+#define PAD50_PE_MSK 0x00000002
+#define PAD50_PE_I_MSK 0xfffffffd
+#define PAD50_PE_SFT 1
+#define PAD50_PE_HI 1
+#define PAD50_PE_SZ 1
+#define PAD50_DS_MSK 0x00000004
+#define PAD50_DS_I_MSK 0xfffffffb
+#define PAD50_DS_SFT 2
+#define PAD50_DS_HI 2
+#define PAD50_DS_SZ 1
+#define PAD50_IE_MSK 0x00000008
+#define PAD50_IE_I_MSK 0xfffffff7
+#define PAD50_IE_SFT 3
+#define PAD50_IE_HI 3
+#define PAD50_IE_SZ 1
+#define PAD50_SEL_I_MSK 0x00000070
+#define PAD50_SEL_I_I_MSK 0xffffff8f
+#define PAD50_SEL_I_SFT 4
+#define PAD50_SEL_I_HI 6
+#define PAD50_SEL_I_SZ 3
+#define PAD50_OD_MSK 0x00000100
+#define PAD50_OD_I_MSK 0xfffffeff
+#define PAD50_OD_SFT 8
+#define PAD50_OD_HI 8
+#define PAD50_OD_SZ 1
+#define PAD50_SEL_O_MSK 0x00003000
+#define PAD50_SEL_O_I_MSK 0xffffcfff
+#define PAD50_SEL_O_SFT 12
+#define PAD50_SEL_O_HI 13
+#define PAD50_SEL_O_SZ 2
+#define PAD50_SEL_OE_MSK 0x00100000
+#define PAD50_SEL_OE_I_MSK 0xffefffff
+#define PAD50_SEL_OE_SFT 20
+#define PAD50_SEL_OE_HI 20
+#define PAD50_SEL_OE_SZ 1
+#define GPIO_12_ID_MSK 0x10000000
+#define GPIO_12_ID_I_MSK 0xefffffff
+#define GPIO_12_ID_SFT 28
+#define GPIO_12_ID_HI 28
+#define GPIO_12_ID_SZ 1
+#define PAD51_OE_MSK 0x00000001
+#define PAD51_OE_I_MSK 0xfffffffe
+#define PAD51_OE_SFT 0
+#define PAD51_OE_HI 0
+#define PAD51_OE_SZ 1
+#define PAD51_PE_MSK 0x00000002
+#define PAD51_PE_I_MSK 0xfffffffd
+#define PAD51_PE_SFT 1
+#define PAD51_PE_HI 1
+#define PAD51_PE_SZ 1
+#define PAD51_DS_MSK 0x00000004
+#define PAD51_DS_I_MSK 0xfffffffb
+#define PAD51_DS_SFT 2
+#define PAD51_DS_HI 2
+#define PAD51_DS_SZ 1
+#define PAD51_IE_MSK 0x00000008
+#define PAD51_IE_I_MSK 0xfffffff7
+#define PAD51_IE_SFT 3
+#define PAD51_IE_HI 3
+#define PAD51_IE_SZ 1
+#define PAD51_SEL_I_MSK 0x00000030
+#define PAD51_SEL_I_I_MSK 0xffffffcf
+#define PAD51_SEL_I_SFT 4
+#define PAD51_SEL_I_HI 5
+#define PAD51_SEL_I_SZ 2
+#define PAD51_OD_MSK 0x00000100
+#define PAD51_OD_I_MSK 0xfffffeff
+#define PAD51_OD_SFT 8
+#define PAD51_OD_HI 8
+#define PAD51_OD_SZ 1
+#define PAD51_SEL_O_MSK 0x00001000
+#define PAD51_SEL_O_I_MSK 0xffffefff
+#define PAD51_SEL_O_SFT 12
+#define PAD51_SEL_O_HI 12
+#define PAD51_SEL_O_SZ 1
+#define PAD51_SEL_OE_MSK 0x00100000
+#define PAD51_SEL_OE_I_MSK 0xffefffff
+#define PAD51_SEL_OE_SFT 20
+#define PAD51_SEL_OE_HI 20
+#define PAD51_SEL_OE_SZ 1
+#define GPIO_13_ID_MSK 0x10000000
+#define GPIO_13_ID_I_MSK 0xefffffff
+#define GPIO_13_ID_SFT 28
+#define GPIO_13_ID_HI 28
+#define GPIO_13_ID_SZ 1
+#define PAD52_OE_MSK 0x00000001
+#define PAD52_OE_I_MSK 0xfffffffe
+#define PAD52_OE_SFT 0
+#define PAD52_OE_HI 0
+#define PAD52_OE_SZ 1
+#define PAD52_PE_MSK 0x00000002
+#define PAD52_PE_I_MSK 0xfffffffd
+#define PAD52_PE_SFT 1
+#define PAD52_PE_HI 1
+#define PAD52_PE_SZ 1
+#define PAD52_DS_MSK 0x00000004
+#define PAD52_DS_I_MSK 0xfffffffb
+#define PAD52_DS_SFT 2
+#define PAD52_DS_HI 2
+#define PAD52_DS_SZ 1
+#define PAD52_SEL_I_MSK 0x00000030
+#define PAD52_SEL_I_I_MSK 0xffffffcf
+#define PAD52_SEL_I_SFT 4
+#define PAD52_SEL_I_HI 5
+#define PAD52_SEL_I_SZ 2
+#define PAD52_OD_MSK 0x00000100
+#define PAD52_OD_I_MSK 0xfffffeff
+#define PAD52_OD_SFT 8
+#define PAD52_OD_HI 8
+#define PAD52_OD_SZ 1
+#define PAD52_SEL_O_MSK 0x00001000
+#define PAD52_SEL_O_I_MSK 0xffffefff
+#define PAD52_SEL_O_SFT 12
+#define PAD52_SEL_O_HI 12
+#define PAD52_SEL_O_SZ 1
+#define PAD52_SEL_OE_MSK 0x00100000
+#define PAD52_SEL_OE_I_MSK 0xffefffff
+#define PAD52_SEL_OE_SFT 20
+#define PAD52_SEL_OE_HI 20
+#define PAD52_SEL_OE_SZ 1
+#define GPIO_14_ID_MSK 0x10000000
+#define GPIO_14_ID_I_MSK 0xefffffff
+#define GPIO_14_ID_SFT 28
+#define GPIO_14_ID_HI 28
+#define GPIO_14_ID_SZ 1
+#define PAD53_OE_MSK 0x00000001
+#define PAD53_OE_I_MSK 0xfffffffe
+#define PAD53_OE_SFT 0
+#define PAD53_OE_HI 0
+#define PAD53_OE_SZ 1
+#define PAD53_PE_MSK 0x00000002
+#define PAD53_PE_I_MSK 0xfffffffd
+#define PAD53_PE_SFT 1
+#define PAD53_PE_HI 1
+#define PAD53_PE_SZ 1
+#define PAD53_DS_MSK 0x00000004
+#define PAD53_DS_I_MSK 0xfffffffb
+#define PAD53_DS_SFT 2
+#define PAD53_DS_HI 2
+#define PAD53_DS_SZ 1
+#define PAD53_IE_MSK 0x00000008
+#define PAD53_IE_I_MSK 0xfffffff7
+#define PAD53_IE_SFT 3
+#define PAD53_IE_HI 3
+#define PAD53_IE_SZ 1
+#define PAD53_SEL_I_MSK 0x00000030
+#define PAD53_SEL_I_I_MSK 0xffffffcf
+#define PAD53_SEL_I_SFT 4
+#define PAD53_SEL_I_HI 5
+#define PAD53_SEL_I_SZ 2
+#define PAD53_OD_MSK 0x00000100
+#define PAD53_OD_I_MSK 0xfffffeff
+#define PAD53_OD_SFT 8
+#define PAD53_OD_HI 8
+#define PAD53_OD_SZ 1
+#define PAD53_SEL_O_MSK 0x00001000
+#define PAD53_SEL_O_I_MSK 0xffffefff
+#define PAD53_SEL_O_SFT 12
+#define PAD53_SEL_O_HI 12
+#define PAD53_SEL_O_SZ 1
+#define JTAG_TMS_ID_MSK 0x10000000
+#define JTAG_TMS_ID_I_MSK 0xefffffff
+#define JTAG_TMS_ID_SFT 28
+#define JTAG_TMS_ID_HI 28
+#define JTAG_TMS_ID_SZ 1
+#define PAD54_OE_MSK 0x00000001
+#define PAD54_OE_I_MSK 0xfffffffe
+#define PAD54_OE_SFT 0
+#define PAD54_OE_HI 0
+#define PAD54_OE_SZ 1
+#define PAD54_PE_MSK 0x00000002
+#define PAD54_PE_I_MSK 0xfffffffd
+#define PAD54_PE_SFT 1
+#define PAD54_PE_HI 1
+#define PAD54_PE_SZ 1
+#define PAD54_DS_MSK 0x00000004
+#define PAD54_DS_I_MSK 0xfffffffb
+#define PAD54_DS_SFT 2
+#define PAD54_DS_HI 2
+#define PAD54_DS_SZ 1
+#define PAD54_OD_MSK 0x00000100
+#define PAD54_OD_I_MSK 0xfffffeff
+#define PAD54_OD_SFT 8
+#define PAD54_OD_HI 8
+#define PAD54_OD_SZ 1
+#define PAD54_SEL_O_MSK 0x00003000
+#define PAD54_SEL_O_I_MSK 0xffffcfff
+#define PAD54_SEL_O_SFT 12
+#define PAD54_SEL_O_HI 13
+#define PAD54_SEL_O_SZ 2
+#define JTAG_TCK_ID_MSK 0x10000000
+#define JTAG_TCK_ID_I_MSK 0xefffffff
+#define JTAG_TCK_ID_SFT 28
+#define JTAG_TCK_ID_HI 28
+#define JTAG_TCK_ID_SZ 1
+#define PAD56_PE_MSK 0x00000002
+#define PAD56_PE_I_MSK 0xfffffffd
+#define PAD56_PE_SFT 1
+#define PAD56_PE_HI 1
+#define PAD56_PE_SZ 1
+#define PAD56_DS_MSK 0x00000004
+#define PAD56_DS_I_MSK 0xfffffffb
+#define PAD56_DS_SFT 2
+#define PAD56_DS_HI 2
+#define PAD56_DS_SZ 1
+#define PAD56_SEL_I_MSK 0x00000010
+#define PAD56_SEL_I_I_MSK 0xffffffef
+#define PAD56_SEL_I_SFT 4
+#define PAD56_SEL_I_HI 4
+#define PAD56_SEL_I_SZ 1
+#define PAD56_OD_MSK 0x00000100
+#define PAD56_OD_I_MSK 0xfffffeff
+#define PAD56_OD_SFT 8
+#define PAD56_OD_HI 8
+#define PAD56_OD_SZ 1
+#define JTAG_TDI_ID_MSK 0x10000000
+#define JTAG_TDI_ID_I_MSK 0xefffffff
+#define JTAG_TDI_ID_SFT 28
+#define JTAG_TDI_ID_HI 28
+#define JTAG_TDI_ID_SZ 1
+#define PAD57_OE_MSK 0x00000001
+#define PAD57_OE_I_MSK 0xfffffffe
+#define PAD57_OE_SFT 0
+#define PAD57_OE_HI 0
+#define PAD57_OE_SZ 1
+#define PAD57_PE_MSK 0x00000002
+#define PAD57_PE_I_MSK 0xfffffffd
+#define PAD57_PE_SFT 1
+#define PAD57_PE_HI 1
+#define PAD57_PE_SZ 1
+#define PAD57_DS_MSK 0x00000004
+#define PAD57_DS_I_MSK 0xfffffffb
+#define PAD57_DS_SFT 2
+#define PAD57_DS_HI 2
+#define PAD57_DS_SZ 1
+#define PAD57_IE_MSK 0x00000008
+#define PAD57_IE_I_MSK 0xfffffff7
+#define PAD57_IE_SFT 3
+#define PAD57_IE_HI 3
+#define PAD57_IE_SZ 1
+#define PAD57_SEL_I_MSK 0x00000030
+#define PAD57_SEL_I_I_MSK 0xffffffcf
+#define PAD57_SEL_I_SFT 4
+#define PAD57_SEL_I_HI 5
+#define PAD57_SEL_I_SZ 2
+#define PAD57_OD_MSK 0x00000100
+#define PAD57_OD_I_MSK 0xfffffeff
+#define PAD57_OD_SFT 8
+#define PAD57_OD_HI 8
+#define PAD57_OD_SZ 1
+#define PAD57_SEL_O_MSK 0x00003000
+#define PAD57_SEL_O_I_MSK 0xffffcfff
+#define PAD57_SEL_O_SFT 12
+#define PAD57_SEL_O_HI 13
+#define PAD57_SEL_O_SZ 2
+#define PAD57_SEL_OE_MSK 0x00100000
+#define PAD57_SEL_OE_I_MSK 0xffefffff
+#define PAD57_SEL_OE_SFT 20
+#define PAD57_SEL_OE_HI 20
+#define PAD57_SEL_OE_SZ 1
+#define JTAG_TDO_ID_MSK 0x10000000
+#define JTAG_TDO_ID_I_MSK 0xefffffff
+#define JTAG_TDO_ID_SFT 28
+#define JTAG_TDO_ID_HI 28
+#define JTAG_TDO_ID_SZ 1
+#define PAD58_OE_MSK 0x00000001
+#define PAD58_OE_I_MSK 0xfffffffe
+#define PAD58_OE_SFT 0
+#define PAD58_OE_HI 0
+#define PAD58_OE_SZ 1
+#define PAD58_PE_MSK 0x00000002
+#define PAD58_PE_I_MSK 0xfffffffd
+#define PAD58_PE_SFT 1
+#define PAD58_PE_HI 1
+#define PAD58_PE_SZ 1
+#define PAD58_DS_MSK 0x00000004
+#define PAD58_DS_I_MSK 0xfffffffb
+#define PAD58_DS_SFT 2
+#define PAD58_DS_HI 2
+#define PAD58_DS_SZ 1
+#define PAD58_IE_MSK 0x00000008
+#define PAD58_IE_I_MSK 0xfffffff7
+#define PAD58_IE_SFT 3
+#define PAD58_IE_HI 3
+#define PAD58_IE_SZ 1
+#define PAD58_SEL_I_MSK 0x00000030
+#define PAD58_SEL_I_I_MSK 0xffffffcf
+#define PAD58_SEL_I_SFT 4
+#define PAD58_SEL_I_HI 5
+#define PAD58_SEL_I_SZ 2
+#define PAD58_OD_MSK 0x00000100
+#define PAD58_OD_I_MSK 0xfffffeff
+#define PAD58_OD_SFT 8
+#define PAD58_OD_HI 8
+#define PAD58_OD_SZ 1
+#define PAD58_SEL_O_MSK 0x00001000
+#define PAD58_SEL_O_I_MSK 0xffffefff
+#define PAD58_SEL_O_SFT 12
+#define PAD58_SEL_O_HI 12
+#define PAD58_SEL_O_SZ 1
+#define TEST_16_ID_MSK 0x10000000
+#define TEST_16_ID_I_MSK 0xefffffff
+#define TEST_16_ID_SFT 28
+#define TEST_16_ID_HI 28
+#define TEST_16_ID_SZ 1
+#define PAD59_OE_MSK 0x00000001
+#define PAD59_OE_I_MSK 0xfffffffe
+#define PAD59_OE_SFT 0
+#define PAD59_OE_HI 0
+#define PAD59_OE_SZ 1
+#define PAD59_PE_MSK 0x00000002
+#define PAD59_PE_I_MSK 0xfffffffd
+#define PAD59_PE_SFT 1
+#define PAD59_PE_HI 1
+#define PAD59_PE_SZ 1
+#define PAD59_DS_MSK 0x00000004
+#define PAD59_DS_I_MSK 0xfffffffb
+#define PAD59_DS_SFT 2
+#define PAD59_DS_HI 2
+#define PAD59_DS_SZ 1
+#define PAD59_IE_MSK 0x00000008
+#define PAD59_IE_I_MSK 0xfffffff7
+#define PAD59_IE_SFT 3
+#define PAD59_IE_HI 3
+#define PAD59_IE_SZ 1
+#define PAD59_SEL_I_MSK 0x00000030
+#define PAD59_SEL_I_I_MSK 0xffffffcf
+#define PAD59_SEL_I_SFT 4
+#define PAD59_SEL_I_HI 5
+#define PAD59_SEL_I_SZ 2
+#define PAD59_OD_MSK 0x00000100
+#define PAD59_OD_I_MSK 0xfffffeff
+#define PAD59_OD_SFT 8
+#define PAD59_OD_HI 8
+#define PAD59_OD_SZ 1
+#define PAD59_SEL_O_MSK 0x00001000
+#define PAD59_SEL_O_I_MSK 0xffffefff
+#define PAD59_SEL_O_SFT 12
+#define PAD59_SEL_O_HI 12
+#define PAD59_SEL_O_SZ 1
+#define TEST_17_ID_MSK 0x10000000
+#define TEST_17_ID_I_MSK 0xefffffff
+#define TEST_17_ID_SFT 28
+#define TEST_17_ID_HI 28
+#define TEST_17_ID_SZ 1
+#define PAD60_OE_MSK 0x00000001
+#define PAD60_OE_I_MSK 0xfffffffe
+#define PAD60_OE_SFT 0
+#define PAD60_OE_HI 0
+#define PAD60_OE_SZ 1
+#define PAD60_PE_MSK 0x00000002
+#define PAD60_PE_I_MSK 0xfffffffd
+#define PAD60_PE_SFT 1
+#define PAD60_PE_HI 1
+#define PAD60_PE_SZ 1
+#define PAD60_DS_MSK 0x00000004
+#define PAD60_DS_I_MSK 0xfffffffb
+#define PAD60_DS_SFT 2
+#define PAD60_DS_HI 2
+#define PAD60_DS_SZ 1
+#define PAD60_IE_MSK 0x00000008
+#define PAD60_IE_I_MSK 0xfffffff7
+#define PAD60_IE_SFT 3
+#define PAD60_IE_HI 3
+#define PAD60_IE_SZ 1
+#define PAD60_SEL_I_MSK 0x00000030
+#define PAD60_SEL_I_I_MSK 0xffffffcf
+#define PAD60_SEL_I_SFT 4
+#define PAD60_SEL_I_HI 5
+#define PAD60_SEL_I_SZ 2
+#define PAD60_OD_MSK 0x00000100
+#define PAD60_OD_I_MSK 0xfffffeff
+#define PAD60_OD_SFT 8
+#define PAD60_OD_HI 8
+#define PAD60_OD_SZ 1
+#define PAD60_SEL_O_MSK 0x00001000
+#define PAD60_SEL_O_I_MSK 0xffffefff
+#define PAD60_SEL_O_SFT 12
+#define PAD60_SEL_O_HI 12
+#define PAD60_SEL_O_SZ 1
+#define TEST_18_ID_MSK 0x10000000
+#define TEST_18_ID_I_MSK 0xefffffff
+#define TEST_18_ID_SFT 28
+#define TEST_18_ID_HI 28
+#define TEST_18_ID_SZ 1
+#define PAD61_OE_MSK 0x00000001
+#define PAD61_OE_I_MSK 0xfffffffe
+#define PAD61_OE_SFT 0
+#define PAD61_OE_HI 0
+#define PAD61_OE_SZ 1
+#define PAD61_PE_MSK 0x00000002
+#define PAD61_PE_I_MSK 0xfffffffd
+#define PAD61_PE_SFT 1
+#define PAD61_PE_HI 1
+#define PAD61_PE_SZ 1
+#define PAD61_DS_MSK 0x00000004
+#define PAD61_DS_I_MSK 0xfffffffb
+#define PAD61_DS_SFT 2
+#define PAD61_DS_HI 2
+#define PAD61_DS_SZ 1
+#define PAD61_IE_MSK 0x00000008
+#define PAD61_IE_I_MSK 0xfffffff7
+#define PAD61_IE_SFT 3
+#define PAD61_IE_HI 3
+#define PAD61_IE_SZ 1
+#define PAD61_SEL_I_MSK 0x00000010
+#define PAD61_SEL_I_I_MSK 0xffffffef
+#define PAD61_SEL_I_SFT 4
+#define PAD61_SEL_I_HI 4
+#define PAD61_SEL_I_SZ 1
+#define PAD61_OD_MSK 0x00000100
+#define PAD61_OD_I_MSK 0xfffffeff
+#define PAD61_OD_SFT 8
+#define PAD61_OD_HI 8
+#define PAD61_OD_SZ 1
+#define PAD61_SEL_O_MSK 0x00003000
+#define PAD61_SEL_O_I_MSK 0xffffcfff
+#define PAD61_SEL_O_SFT 12
+#define PAD61_SEL_O_HI 13
+#define PAD61_SEL_O_SZ 2
+#define TEST_19_ID_MSK 0x10000000
+#define TEST_19_ID_I_MSK 0xefffffff
+#define TEST_19_ID_SFT 28
+#define TEST_19_ID_HI 28
+#define TEST_19_ID_SZ 1
+#define PAD62_OE_MSK 0x00000001
+#define PAD62_OE_I_MSK 0xfffffffe
+#define PAD62_OE_SFT 0
+#define PAD62_OE_HI 0
+#define PAD62_OE_SZ 1
+#define PAD62_PE_MSK 0x00000002
+#define PAD62_PE_I_MSK 0xfffffffd
+#define PAD62_PE_SFT 1
+#define PAD62_PE_HI 1
+#define PAD62_PE_SZ 1
+#define PAD62_DS_MSK 0x00000004
+#define PAD62_DS_I_MSK 0xfffffffb
+#define PAD62_DS_SFT 2
+#define PAD62_DS_HI 2
+#define PAD62_DS_SZ 1
+#define PAD62_IE_MSK 0x00000008
+#define PAD62_IE_I_MSK 0xfffffff7
+#define PAD62_IE_SFT 3
+#define PAD62_IE_HI 3
+#define PAD62_IE_SZ 1
+#define PAD62_SEL_I_MSK 0x00000010
+#define PAD62_SEL_I_I_MSK 0xffffffef
+#define PAD62_SEL_I_SFT 4
+#define PAD62_SEL_I_HI 4
+#define PAD62_SEL_I_SZ 1
+#define PAD62_OD_MSK 0x00000100
+#define PAD62_OD_I_MSK 0xfffffeff
+#define PAD62_OD_SFT 8
+#define PAD62_OD_HI 8
+#define PAD62_OD_SZ 1
+#define PAD62_SEL_O_MSK 0x00001000
+#define PAD62_SEL_O_I_MSK 0xffffefff
+#define PAD62_SEL_O_SFT 12
+#define PAD62_SEL_O_HI 12
+#define PAD62_SEL_O_SZ 1
+#define TEST_20_ID_MSK 0x10000000
+#define TEST_20_ID_I_MSK 0xefffffff
+#define TEST_20_ID_SFT 28
+#define TEST_20_ID_HI 28
+#define TEST_20_ID_SZ 1
+#define PAD64_OE_MSK 0x00000001
+#define PAD64_OE_I_MSK 0xfffffffe
+#define PAD64_OE_SFT 0
+#define PAD64_OE_HI 0
+#define PAD64_OE_SZ 1
+#define PAD64_PE_MSK 0x00000002
+#define PAD64_PE_I_MSK 0xfffffffd
+#define PAD64_PE_SFT 1
+#define PAD64_PE_HI 1
+#define PAD64_PE_SZ 1
+#define PAD64_DS_MSK 0x00000004
+#define PAD64_DS_I_MSK 0xfffffffb
+#define PAD64_DS_SFT 2
+#define PAD64_DS_HI 2
+#define PAD64_DS_SZ 1
+#define PAD64_IE_MSK 0x00000008
+#define PAD64_IE_I_MSK 0xfffffff7
+#define PAD64_IE_SFT 3
+#define PAD64_IE_HI 3
+#define PAD64_IE_SZ 1
+#define PAD64_SEL_I_MSK 0x00000070
+#define PAD64_SEL_I_I_MSK 0xffffff8f
+#define PAD64_SEL_I_SFT 4
+#define PAD64_SEL_I_HI 6
+#define PAD64_SEL_I_SZ 3
+#define PAD64_OD_MSK 0x00000100
+#define PAD64_OD_I_MSK 0xfffffeff
+#define PAD64_OD_SFT 8
+#define PAD64_OD_HI 8
+#define PAD64_OD_SZ 1
+#define PAD64_SEL_O_MSK 0x00003000
+#define PAD64_SEL_O_I_MSK 0xffffcfff
+#define PAD64_SEL_O_SFT 12
+#define PAD64_SEL_O_HI 13
+#define PAD64_SEL_O_SZ 2
+#define PAD64_SEL_OE_MSK 0x00100000
+#define PAD64_SEL_OE_I_MSK 0xffefffff
+#define PAD64_SEL_OE_SFT 20
+#define PAD64_SEL_OE_HI 20
+#define PAD64_SEL_OE_SZ 1
+#define GPIO_15_IP_ID_MSK 0x10000000
+#define GPIO_15_IP_ID_I_MSK 0xefffffff
+#define GPIO_15_IP_ID_SFT 28
+#define GPIO_15_IP_ID_HI 28
+#define GPIO_15_IP_ID_SZ 1
+#define PAD65_OE_MSK 0x00000001
+#define PAD65_OE_I_MSK 0xfffffffe
+#define PAD65_OE_SFT 0
+#define PAD65_OE_HI 0
+#define PAD65_OE_SZ 1
+#define PAD65_PE_MSK 0x00000002
+#define PAD65_PE_I_MSK 0xfffffffd
+#define PAD65_PE_SFT 1
+#define PAD65_PE_HI 1
+#define PAD65_PE_SZ 1
+#define PAD65_DS_MSK 0x00000004
+#define PAD65_DS_I_MSK 0xfffffffb
+#define PAD65_DS_SFT 2
+#define PAD65_DS_HI 2
+#define PAD65_DS_SZ 1
+#define PAD65_IE_MSK 0x00000008
+#define PAD65_IE_I_MSK 0xfffffff7
+#define PAD65_IE_SFT 3
+#define PAD65_IE_HI 3
+#define PAD65_IE_SZ 1
+#define PAD65_SEL_I_MSK 0x00000070
+#define PAD65_SEL_I_I_MSK 0xffffff8f
+#define PAD65_SEL_I_SFT 4
+#define PAD65_SEL_I_HI 6
+#define PAD65_SEL_I_SZ 3
+#define PAD65_OD_MSK 0x00000100
+#define PAD65_OD_I_MSK 0xfffffeff
+#define PAD65_OD_SFT 8
+#define PAD65_OD_HI 8
+#define PAD65_OD_SZ 1
+#define PAD65_SEL_O_MSK 0x00001000
+#define PAD65_SEL_O_I_MSK 0xffffefff
+#define PAD65_SEL_O_SFT 12
+#define PAD65_SEL_O_HI 12
+#define PAD65_SEL_O_SZ 1
+#define GPIO_TEST_7_IN_ID_MSK 0x10000000
+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_7_IN_ID_SFT 28
+#define GPIO_TEST_7_IN_ID_HI 28
+#define GPIO_TEST_7_IN_ID_SZ 1
+#define PAD66_OE_MSK 0x00000001
+#define PAD66_OE_I_MSK 0xfffffffe
+#define PAD66_OE_SFT 0
+#define PAD66_OE_HI 0
+#define PAD66_OE_SZ 1
+#define PAD66_PE_MSK 0x00000002
+#define PAD66_PE_I_MSK 0xfffffffd
+#define PAD66_PE_SFT 1
+#define PAD66_PE_HI 1
+#define PAD66_PE_SZ 1
+#define PAD66_DS_MSK 0x00000004
+#define PAD66_DS_I_MSK 0xfffffffb
+#define PAD66_DS_SFT 2
+#define PAD66_DS_HI 2
+#define PAD66_DS_SZ 1
+#define PAD66_IE_MSK 0x00000008
+#define PAD66_IE_I_MSK 0xfffffff7
+#define PAD66_IE_SFT 3
+#define PAD66_IE_HI 3
+#define PAD66_IE_SZ 1
+#define PAD66_SEL_I_MSK 0x00000030
+#define PAD66_SEL_I_I_MSK 0xffffffcf
+#define PAD66_SEL_I_SFT 4
+#define PAD66_SEL_I_HI 5
+#define PAD66_SEL_I_SZ 2
+#define PAD66_OD_MSK 0x00000100
+#define PAD66_OD_I_MSK 0xfffffeff
+#define PAD66_OD_SFT 8
+#define PAD66_OD_HI 8
+#define PAD66_OD_SZ 1
+#define PAD66_SEL_O_MSK 0x00003000
+#define PAD66_SEL_O_I_MSK 0xffffcfff
+#define PAD66_SEL_O_SFT 12
+#define PAD66_SEL_O_HI 13
+#define PAD66_SEL_O_SZ 2
+#define GPIO_17_QP_ID_MSK 0x10000000
+#define GPIO_17_QP_ID_I_MSK 0xefffffff
+#define GPIO_17_QP_ID_SFT 28
+#define GPIO_17_QP_ID_HI 28
+#define GPIO_17_QP_ID_SZ 1
+#define PAD68_OE_MSK 0x00000001
+#define PAD68_OE_I_MSK 0xfffffffe
+#define PAD68_OE_SFT 0
+#define PAD68_OE_HI 0
+#define PAD68_OE_SZ 1
+#define PAD68_PE_MSK 0x00000002
+#define PAD68_PE_I_MSK 0xfffffffd
+#define PAD68_PE_SFT 1
+#define PAD68_PE_HI 1
+#define PAD68_PE_SZ 1
+#define PAD68_DS_MSK 0x00000004
+#define PAD68_DS_I_MSK 0xfffffffb
+#define PAD68_DS_SFT 2
+#define PAD68_DS_HI 2
+#define PAD68_DS_SZ 1
+#define PAD68_IE_MSK 0x00000008
+#define PAD68_IE_I_MSK 0xfffffff7
+#define PAD68_IE_SFT 3
+#define PAD68_IE_HI 3
+#define PAD68_IE_SZ 1
+#define PAD68_OD_MSK 0x00000100
+#define PAD68_OD_I_MSK 0xfffffeff
+#define PAD68_OD_SFT 8
+#define PAD68_OD_HI 8
+#define PAD68_OD_SZ 1
+#define PAD68_SEL_O_MSK 0x00001000
+#define PAD68_SEL_O_I_MSK 0xffffefff
+#define PAD68_SEL_O_SFT 12
+#define PAD68_SEL_O_HI 12
+#define PAD68_SEL_O_SZ 1
+#define GPIO_19_ID_MSK 0x10000000
+#define GPIO_19_ID_I_MSK 0xefffffff
+#define GPIO_19_ID_SFT 28
+#define GPIO_19_ID_HI 28
+#define GPIO_19_ID_SZ 1
+#define PAD67_OE_MSK 0x00000001
+#define PAD67_OE_I_MSK 0xfffffffe
+#define PAD67_OE_SFT 0
+#define PAD67_OE_HI 0
+#define PAD67_OE_SZ 1
+#define PAD67_PE_MSK 0x00000002
+#define PAD67_PE_I_MSK 0xfffffffd
+#define PAD67_PE_SFT 1
+#define PAD67_PE_HI 1
+#define PAD67_PE_SZ 1
+#define PAD67_DS_MSK 0x00000004
+#define PAD67_DS_I_MSK 0xfffffffb
+#define PAD67_DS_SFT 2
+#define PAD67_DS_HI 2
+#define PAD67_DS_SZ 1
+#define PAD67_IE_MSK 0x00000008
+#define PAD67_IE_I_MSK 0xfffffff7
+#define PAD67_IE_SFT 3
+#define PAD67_IE_HI 3
+#define PAD67_IE_SZ 1
+#define PAD67_SEL_I_MSK 0x00000070
+#define PAD67_SEL_I_I_MSK 0xffffff8f
+#define PAD67_SEL_I_SFT 4
+#define PAD67_SEL_I_HI 6
+#define PAD67_SEL_I_SZ 3
+#define PAD67_OD_MSK 0x00000100
+#define PAD67_OD_I_MSK 0xfffffeff
+#define PAD67_OD_SFT 8
+#define PAD67_OD_HI 8
+#define PAD67_OD_SZ 1
+#define PAD67_SEL_O_MSK 0x00003000
+#define PAD67_SEL_O_I_MSK 0xffffcfff
+#define PAD67_SEL_O_SFT 12
+#define PAD67_SEL_O_HI 13
+#define PAD67_SEL_O_SZ 2
+#define GPIO_TEST_8_QN_ID_MSK 0x10000000
+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_8_QN_ID_SFT 28
+#define GPIO_TEST_8_QN_ID_HI 28
+#define GPIO_TEST_8_QN_ID_SZ 1
+#define PAD69_OE_MSK 0x00000001
+#define PAD69_OE_I_MSK 0xfffffffe
+#define PAD69_OE_SFT 0
+#define PAD69_OE_HI 0
+#define PAD69_OE_SZ 1
+#define PAD69_PE_MSK 0x00000002
+#define PAD69_PE_I_MSK 0xfffffffd
+#define PAD69_PE_SFT 1
+#define PAD69_PE_HI 1
+#define PAD69_PE_SZ 1
+#define PAD69_DS_MSK 0x00000004
+#define PAD69_DS_I_MSK 0xfffffffb
+#define PAD69_DS_SFT 2
+#define PAD69_DS_HI 2
+#define PAD69_DS_SZ 1
+#define PAD69_IE_MSK 0x00000008
+#define PAD69_IE_I_MSK 0xfffffff7
+#define PAD69_IE_SFT 3
+#define PAD69_IE_HI 3
+#define PAD69_IE_SZ 1
+#define PAD69_SEL_I_MSK 0x00000030
+#define PAD69_SEL_I_I_MSK 0xffffffcf
+#define PAD69_SEL_I_SFT 4
+#define PAD69_SEL_I_HI 5
+#define PAD69_SEL_I_SZ 2
+#define PAD69_OD_MSK 0x00000100
+#define PAD69_OD_I_MSK 0xfffffeff
+#define PAD69_OD_SFT 8
+#define PAD69_OD_HI 8
+#define PAD69_OD_SZ 1
+#define PAD69_SEL_O_MSK 0x00001000
+#define PAD69_SEL_O_I_MSK 0xffffefff
+#define PAD69_SEL_O_SFT 12
+#define PAD69_SEL_O_HI 12
+#define PAD69_SEL_O_SZ 1
+#define STRAP2_MSK 0x08000000
+#define STRAP2_I_MSK 0xf7ffffff
+#define STRAP2_SFT 27
+#define STRAP2_HI 27
+#define STRAP2_SZ 1
+#define GPIO_20_ID_MSK 0x10000000
+#define GPIO_20_ID_I_MSK 0xefffffff
+#define GPIO_20_ID_SFT 28
+#define GPIO_20_ID_HI 28
+#define GPIO_20_ID_SZ 1
+#define PAD70_OE_MSK 0x00000001
+#define PAD70_OE_I_MSK 0xfffffffe
+#define PAD70_OE_SFT 0
+#define PAD70_OE_HI 0
+#define PAD70_OE_SZ 1
+#define PAD70_PE_MSK 0x00000002
+#define PAD70_PE_I_MSK 0xfffffffd
+#define PAD70_PE_SFT 1
+#define PAD70_PE_HI 1
+#define PAD70_PE_SZ 1
+#define PAD70_DS_MSK 0x00000004
+#define PAD70_DS_I_MSK 0xfffffffb
+#define PAD70_DS_SFT 2
+#define PAD70_DS_HI 2
+#define PAD70_DS_SZ 1
+#define PAD70_IE_MSK 0x00000008
+#define PAD70_IE_I_MSK 0xfffffff7
+#define PAD70_IE_SFT 3
+#define PAD70_IE_HI 3
+#define PAD70_IE_SZ 1
+#define PAD70_SEL_I_MSK 0x00000030
+#define PAD70_SEL_I_I_MSK 0xffffffcf
+#define PAD70_SEL_I_SFT 4
+#define PAD70_SEL_I_HI 5
+#define PAD70_SEL_I_SZ 2
+#define PAD70_OD_MSK 0x00000100
+#define PAD70_OD_I_MSK 0xfffffeff
+#define PAD70_OD_SFT 8
+#define PAD70_OD_HI 8
+#define PAD70_OD_SZ 1
+#define PAD70_SEL_O_MSK 0x00007000
+#define PAD70_SEL_O_I_MSK 0xffff8fff
+#define PAD70_SEL_O_SFT 12
+#define PAD70_SEL_O_HI 14
+#define PAD70_SEL_O_SZ 3
+#define GPIO_21_ID_MSK 0x10000000
+#define GPIO_21_ID_I_MSK 0xefffffff
+#define GPIO_21_ID_SFT 28
+#define GPIO_21_ID_HI 28
+#define GPIO_21_ID_SZ 1
+#define PAD231_OE_MSK 0x00000001
+#define PAD231_OE_I_MSK 0xfffffffe
+#define PAD231_OE_SFT 0
+#define PAD231_OE_HI 0
+#define PAD231_OE_SZ 1
+#define PAD231_PE_MSK 0x00000002
+#define PAD231_PE_I_MSK 0xfffffffd
+#define PAD231_PE_SFT 1
+#define PAD231_PE_HI 1
+#define PAD231_PE_SZ 1
+#define PAD231_DS_MSK 0x00000004
+#define PAD231_DS_I_MSK 0xfffffffb
+#define PAD231_DS_SFT 2
+#define PAD231_DS_HI 2
+#define PAD231_DS_SZ 1
+#define PAD231_IE_MSK 0x00000008
+#define PAD231_IE_I_MSK 0xfffffff7
+#define PAD231_IE_SFT 3
+#define PAD231_IE_HI 3
+#define PAD231_IE_SZ 1
+#define PAD231_OD_MSK 0x00000100
+#define PAD231_OD_I_MSK 0xfffffeff
+#define PAD231_OD_SFT 8
+#define PAD231_OD_HI 8
+#define PAD231_OD_SZ 1
+#define PIN_40_OR_56_ID_MSK 0x10000000
+#define PIN_40_OR_56_ID_I_MSK 0xefffffff
+#define PIN_40_OR_56_ID_SFT 28
+#define PIN_40_OR_56_ID_HI 28
+#define PIN_40_OR_56_ID_SZ 1
+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
+#define MP_PHY2RX_DATA__0_SEL_SFT 0
+#define MP_PHY2RX_DATA__0_SEL_HI 0
+#define MP_PHY2RX_DATA__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
+#define MP_PHY2RX_DATA__1_SEL_SFT 1
+#define MP_PHY2RX_DATA__1_SEL_HI 1
+#define MP_PHY2RX_DATA__1_SEL_SZ 1
+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
+#define MP_TX_FF_RPTR__1_SEL_SFT 2
+#define MP_TX_FF_RPTR__1_SEL_HI 2
+#define MP_TX_FF_RPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
+#define MP_RX_FF_WPTR__2_SEL_SFT 3
+#define MP_RX_FF_WPTR__2_SEL_HI 3
+#define MP_RX_FF_WPTR__2_SEL_SZ 1
+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
+#define MP_RX_FF_WPTR__1_SEL_SFT 4
+#define MP_RX_FF_WPTR__1_SEL_HI 4
+#define MP_RX_FF_WPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
+#define MP_RX_FF_WPTR__0_SEL_SFT 5
+#define MP_RX_FF_WPTR__0_SEL_HI 5
+#define MP_RX_FF_WPTR__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
+#define MP_PHY2RX_DATA__2_SEL_SFT 6
+#define MP_PHY2RX_DATA__2_SEL_HI 6
+#define MP_PHY2RX_DATA__2_SEL_SZ 1
+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
+#define MP_PHY2RX_DATA__4_SEL_SFT 7
+#define MP_PHY2RX_DATA__4_SEL_HI 7
+#define MP_PHY2RX_DATA__4_SEL_SZ 1
+#define I2CM_SDA_ID_SEL_MSK 0x00000300
+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
+#define I2CM_SDA_ID_SEL_SFT 8
+#define I2CM_SDA_ID_SEL_HI 9
+#define I2CM_SDA_ID_SEL_SZ 2
+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
+#define CRYSTAL_OUT_REQ_SEL_SFT 10
+#define CRYSTAL_OUT_REQ_SEL_HI 10
+#define CRYSTAL_OUT_REQ_SEL_SZ 1
+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
+#define MP_PHY2RX_DATA__5_SEL_SFT 11
+#define MP_PHY2RX_DATA__5_SEL_HI 11
+#define MP_PHY2RX_DATA__5_SEL_SZ 1
+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
+#define MP_PHY2RX_DATA__3_SEL_SFT 12
+#define MP_PHY2RX_DATA__3_SEL_HI 12
+#define MP_PHY2RX_DATA__3_SEL_SZ 1
+#define UART_RXD_SEL_MSK 0x00006000
+#define UART_RXD_SEL_I_MSK 0xffff9fff
+#define UART_RXD_SEL_SFT 13
+#define UART_RXD_SEL_HI 14
+#define UART_RXD_SEL_SZ 2
+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
+#define MP_PHY2RX_DATA__6_SEL_SFT 15
+#define MP_PHY2RX_DATA__6_SEL_HI 15
+#define MP_PHY2RX_DATA__6_SEL_SZ 1
+#define DAT_UART_NCTS_SEL_MSK 0x00010000
+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
+#define DAT_UART_NCTS_SEL_SFT 16
+#define DAT_UART_NCTS_SEL_HI 16
+#define DAT_UART_NCTS_SEL_SZ 1
+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
+#define GPIO_LOG_STOP_SEL_SFT 17
+#define GPIO_LOG_STOP_SEL_HI 19
+#define GPIO_LOG_STOP_SEL_SZ 3
+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
+#define MP_TX_FF_RPTR__0_SEL_SFT 20
+#define MP_TX_FF_RPTR__0_SEL_HI 20
+#define MP_TX_FF_RPTR__0_SEL_SZ 1
+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
+#define MP_PHY_RX_WRST_N_SEL_SFT 21
+#define MP_PHY_RX_WRST_N_SEL_HI 21
+#define MP_PHY_RX_WRST_N_SEL_SZ 1
+#define EXT_32K_SEL_MSK 0x00c00000
+#define EXT_32K_SEL_I_MSK 0xff3fffff
+#define EXT_32K_SEL_SFT 22
+#define EXT_32K_SEL_HI 23
+#define EXT_32K_SEL_SZ 2
+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
+#define MP_PHY2RX_DATA__7_SEL_SFT 24
+#define MP_PHY2RX_DATA__7_SEL_HI 24
+#define MP_PHY2RX_DATA__7_SEL_SZ 1
+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
+#define MP_TX_FF_RPTR__2_SEL_SFT 25
+#define MP_TX_FF_RPTR__2_SEL_HI 25
+#define MP_TX_FF_RPTR__2_SEL_SZ 1
+#define PMUINT_WAKE_SEL_MSK 0x1c000000
+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
+#define PMUINT_WAKE_SEL_SFT 26
+#define PMUINT_WAKE_SEL_HI 28
+#define PMUINT_WAKE_SEL_SZ 3
+#define I2CM_SCL_ID_SEL_MSK 0x20000000
+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
+#define I2CM_SCL_ID_SEL_SFT 29
+#define I2CM_SCL_ID_SEL_HI 29
+#define I2CM_SCL_ID_SEL_SZ 1
+#define MP_MRX_RX_EN_SEL_MSK 0x40000000
+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
+#define MP_MRX_RX_EN_SEL_SFT 30
+#define MP_MRX_RX_EN_SEL_HI 30
+#define MP_MRX_RX_EN_SEL_SZ 1
+#define DAT_UART_RXD_SEL_0_MSK 0x80000000
+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
+#define DAT_UART_RXD_SEL_0_SFT 31
+#define DAT_UART_RXD_SEL_0_HI 31
+#define DAT_UART_RXD_SEL_0_SZ 1
+#define DAT_UART_RXD_SEL_1_MSK 0x00000001
+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
+#define DAT_UART_RXD_SEL_1_SFT 0
+#define DAT_UART_RXD_SEL_1_HI 0
+#define DAT_UART_RXD_SEL_1_SZ 1
+#define SPI_DI_SEL_MSK 0x00000002
+#define SPI_DI_SEL_I_MSK 0xfffffffd
+#define SPI_DI_SEL_SFT 1
+#define SPI_DI_SEL_HI 1
+#define SPI_DI_SEL_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define MASK_TX_INT_MSK 0x00000002
+#define MASK_TX_INT_I_MSK 0xfffffffd
+#define MASK_TX_INT_SFT 1
+#define MASK_TX_INT_HI 1
+#define MASK_TX_INT_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define TX_COMPLETE_INT_MSK 0x00000002
+#define TX_COMPLETE_INT_I_MSK 0xfffffffd
+#define TX_COMPLETE_INT_SFT 1
+#define TX_COMPLETE_INT_HI 1
+#define TX_COMPLETE_INT_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define RX_PACKET_LENGTH_MSK 0x0000ffff
+#define RX_PACKET_LENGTH_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH_SFT 0
+#define RX_PACKET_LENGTH_HI 15
+#define RX_PACKET_LENGTH_SZ 16
+#define CARD_FW_DL_STATUS_MSK 0x00ff0000
+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
+#define CARD_FW_DL_STATUS_SFT 16
+#define CARD_FW_DL_STATUS_HI 23
+#define CARD_FW_DL_STATUS_SZ 8
+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
+#define TX_RX_LOOP_BACK_TEST_SFT 24
+#define TX_RX_LOOP_BACK_TEST_HI 24
+#define TX_RX_LOOP_BACK_TEST_SZ 1
+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
+#define SDIO_LOOP_BACK_TEST_SFT 25
+#define SDIO_LOOP_BACK_TEST_HI 25
+#define SDIO_LOOP_BACK_TEST_SZ 1
+#define CMD52_ABORT_ACTIVE_MSK 0x10000000
+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
+#define CMD52_ABORT_ACTIVE_SFT 28
+#define CMD52_ABORT_ACTIVE_HI 28
+#define CMD52_ABORT_ACTIVE_SZ 1
+#define CMD52_RESET_ACTIVE_MSK 0x20000000
+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
+#define CMD52_RESET_ACTIVE_SFT 29
+#define CMD52_RESET_ACTIVE_HI 29
+#define CMD52_RESET_ACTIVE_SZ 1
+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
+#define SDIO_ALL_RESE_ACTIVE_SFT 31
+#define SDIO_ALL_RESE_ACTIVE_HI 31
+#define SDIO_ALL_RESE_ACTIVE_SZ 1
+#define RX_PACKET_LENGTH2_MSK 0x0000ffff
+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH2_SFT 0
+#define RX_PACKET_LENGTH2_HI 15
+#define RX_PACKET_LENGTH2_SZ 16
+#define RX_INT1_MSK 0x00010000
+#define RX_INT1_I_MSK 0xfffeffff
+#define RX_INT1_SFT 16
+#define RX_INT1_HI 16
+#define RX_INT1_SZ 1
+#define TX_DONE_MSK 0x00020000
+#define TX_DONE_I_MSK 0xfffdffff
+#define TX_DONE_SFT 17
+#define TX_DONE_HI 17
+#define TX_DONE_SZ 1
+#define HCI_TRX_FINISH_MSK 0x00040000
+#define HCI_TRX_FINISH_I_MSK 0xfffbffff
+#define HCI_TRX_FINISH_SFT 18
+#define HCI_TRX_FINISH_HI 18
+#define HCI_TRX_FINISH_SZ 1
+#define ALLOCATE_STATUS_MSK 0x00080000
+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
+#define ALLOCATE_STATUS_SFT 19
+#define ALLOCATE_STATUS_HI 19
+#define ALLOCATE_STATUS_SZ 1
+#define HCI_INPUT_FF_CNT_MSK 0x00f00000
+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
+#define HCI_INPUT_FF_CNT_SFT 20
+#define HCI_INPUT_FF_CNT_HI 23
+#define HCI_INPUT_FF_CNT_SZ 4
+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
+#define HCI_OUTPUT_FF_CNT_SFT 24
+#define HCI_OUTPUT_FF_CNT_HI 28
+#define HCI_OUTPUT_FF_CNT_SZ 5
+#define AHB_HANG4_MSK 0x20000000
+#define AHB_HANG4_I_MSK 0xdfffffff
+#define AHB_HANG4_SFT 29
+#define AHB_HANG4_HI 29
+#define AHB_HANG4_SZ 1
+#define HCI_IN_QUE_EMPTY_MSK 0x40000000
+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
+#define HCI_IN_QUE_EMPTY_SFT 30
+#define HCI_IN_QUE_EMPTY_HI 30
+#define HCI_IN_QUE_EMPTY_SZ 1
+#define SYSTEM_INT_MSK 0x80000000
+#define SYSTEM_INT_I_MSK 0x7fffffff
+#define SYSTEM_INT_SFT 31
+#define SYSTEM_INT_HI 31
+#define SYSTEM_INT_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_THLD_REG_SFT 0
+#define SDIO_FIFO_WR_THLD_REG_HI 8
+#define SDIO_FIFO_WR_THLD_REG_SZ 9
+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
+#define SDIO_FIFO_WR_LIMIT_REG_HI 8
+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
+#define START_BYTE_VALUE_MSK 0x000000ff
+#define START_BYTE_VALUE_I_MSK 0xffffff00
+#define START_BYTE_VALUE_SFT 0
+#define START_BYTE_VALUE_HI 7
+#define START_BYTE_VALUE_SZ 8
+#define END_BYTE_VALUE_MSK 0x0000ff00
+#define END_BYTE_VALUE_I_MSK 0xffff00ff
+#define END_BYTE_VALUE_SFT 8
+#define END_BYTE_VALUE_HI 15
+#define END_BYTE_VALUE_SZ 8
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
+#define SDIO_LAST_CMD_INDEX_REG_SFT 0
+#define SDIO_LAST_CMD_INDEX_REG_HI 5
+#define SDIO_LAST_CMD_INDEX_REG_SZ 6
+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
+#define SDIO_LAST_CMD_CRC_REG_SFT 8
+#define SDIO_LAST_CMD_CRC_REG_HI 14
+#define SDIO_LAST_CMD_CRC_REG_SZ 7
+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
+#define SDIO_LAST_CMD_ARG_REG_SFT 0
+#define SDIO_LAST_CMD_ARG_REG_HI 31
+#define SDIO_LAST_CMD_ARG_REG_SZ 32
+#define SDIO_BUS_STATE_REG_MSK 0x0000001f
+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
+#define SDIO_BUS_STATE_REG_SFT 0
+#define SDIO_BUS_STATE_REG_HI 4
+#define SDIO_BUS_STATE_REG_SZ 5
+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
+#define SDIO_BUSY_LONG_CNT_SFT 16
+#define SDIO_BUSY_LONG_CNT_HI 31
+#define SDIO_BUSY_LONG_CNT_SZ 16
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define RESP_OUT_EDGE_MSK 0x00000100
+#define RESP_OUT_EDGE_I_MSK 0xfffffeff
+#define RESP_OUT_EDGE_SFT 8
+#define RESP_OUT_EDGE_HI 8
+#define RESP_OUT_EDGE_SZ 1
+#define DAT_OUT_EDGE_MSK 0x00000200
+#define DAT_OUT_EDGE_I_MSK 0xfffffdff
+#define DAT_OUT_EDGE_SFT 9
+#define DAT_OUT_EDGE_HI 9
+#define DAT_OUT_EDGE_SZ 1
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define WRITE_DATA_MSK 0x000000ff
+#define WRITE_DATA_I_MSK 0xffffff00
+#define WRITE_DATA_SFT 0
+#define WRITE_DATA_HI 7
+#define WRITE_DATA_SZ 8
+#define WRITE_ADDRESS_MSK 0x0000ff00
+#define WRITE_ADDRESS_I_MSK 0xffff00ff
+#define WRITE_ADDRESS_SFT 8
+#define WRITE_ADDRESS_HI 15
+#define WRITE_ADDRESS_SZ 8
+#define READ_DATA_MSK 0x00ff0000
+#define READ_DATA_I_MSK 0xff00ffff
+#define READ_DATA_SFT 16
+#define READ_DATA_HI 23
+#define READ_DATA_SZ 8
+#define READ_ADDRESS_MSK 0xff000000
+#define READ_ADDRESS_I_MSK 0x00ffffff
+#define READ_ADDRESS_SFT 24
+#define READ_ADDRESS_HI 31
+#define READ_ADDRESS_SZ 8
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define IO_REG_PORT_REG_MSK 0x0001ffff
+#define IO_REG_PORT_REG_I_MSK 0xfffe0000
+#define IO_REG_PORT_REG_SFT 0
+#define IO_REG_PORT_REG_HI 16
+#define IO_REG_PORT_REG_SZ 17
+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
+#define SDIO_FIFO_EMPTY_CNT_SFT 0
+#define SDIO_FIFO_EMPTY_CNT_HI 15
+#define SDIO_FIFO_EMPTY_CNT_SZ 16
+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
+#define SDIO_FIFO_FULL_CNT_SFT 16
+#define SDIO_FIFO_FULL_CNT_HI 31
+#define SDIO_FIFO_FULL_CNT_SZ 16
+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
+#define SDIO_CRC7_ERROR_CNT_SFT 0
+#define SDIO_CRC7_ERROR_CNT_HI 15
+#define SDIO_CRC7_ERROR_CNT_SZ 16
+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
+#define SDIO_CRC16_ERROR_CNT_SFT 16
+#define SDIO_CRC16_ERROR_CNT_HI 31
+#define SDIO_CRC16_ERROR_CNT_SZ 16
+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
+#define SDIO_RD_BLOCK_CNT_SFT 0
+#define SDIO_RD_BLOCK_CNT_HI 8
+#define SDIO_RD_BLOCK_CNT_SZ 9
+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
+#define SDIO_WR_BLOCK_CNT_SFT 16
+#define SDIO_WR_BLOCK_CNT_HI 24
+#define SDIO_WR_BLOCK_CNT_SZ 9
+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
+#define CMD52_RD_ABORT_CNT_SFT 16
+#define CMD52_RD_ABORT_CNT_HI 19
+#define CMD52_RD_ABORT_CNT_SZ 4
+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
+#define CMD52_WR_ABORT_CNT_SFT 20
+#define CMD52_WR_ABORT_CNT_HI 23
+#define CMD52_WR_ABORT_CNT_SZ 4
+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
+#define SDIO_FIFO_WR_PTR_REG_SFT 0
+#define SDIO_FIFO_WR_PTR_REG_HI 7
+#define SDIO_FIFO_WR_PTR_REG_SZ 8
+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
+#define SDIO_FIFO_RD_PTR_REG_SFT 8
+#define SDIO_FIFO_RD_PTR_REG_HI 15
+#define SDIO_FIFO_RD_PTR_REG_SZ 8
+#define SDIO_READ_DATA_CTRL_MSK 0x00010000
+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
+#define SDIO_READ_DATA_CTRL_SFT 16
+#define SDIO_READ_DATA_CTRL_HI 16
+#define SDIO_READ_DATA_CTRL_SZ 1
+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
+#define TX_SIZE_BEFORE_SHIFT_SFT 0
+#define TX_SIZE_BEFORE_SHIFT_HI 7
+#define TX_SIZE_BEFORE_SHIFT_SZ 8
+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
+#define TX_SIZE_SHIFT_BITS_SFT 8
+#define TX_SIZE_SHIFT_BITS_HI 10
+#define TX_SIZE_SHIFT_BITS_SZ 3
+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
+#define SDIO_TX_ALLOC_STATE_SFT 12
+#define SDIO_TX_ALLOC_STATE_HI 12
+#define SDIO_TX_ALLOC_STATE_SZ 1
+#define ALLOCATE_STATUS2_MSK 0x00010000
+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
+#define ALLOCATE_STATUS2_SFT 16
+#define ALLOCATE_STATUS2_HI 16
+#define ALLOCATE_STATUS2_SZ 1
+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
+#define NO_ALLOCATE_SEND_ERROR_SFT 17
+#define NO_ALLOCATE_SEND_ERROR_HI 17
+#define NO_ALLOCATE_SEND_ERROR_SZ 1
+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
+#define DOUBLE_ALLOCATE_ERROR_SFT 18
+#define DOUBLE_ALLOCATE_ERROR_HI 18
+#define DOUBLE_ALLOCATE_ERROR_SZ 1
+#define TX_DONE_STATUS_MSK 0x00080000
+#define TX_DONE_STATUS_I_MSK 0xfff7ffff
+#define TX_DONE_STATUS_SFT 19
+#define TX_DONE_STATUS_HI 19
+#define TX_DONE_STATUS_SZ 1
+#define AHB_HANG2_MSK 0x00100000
+#define AHB_HANG2_I_MSK 0xffefffff
+#define AHB_HANG2_SFT 20
+#define AHB_HANG2_HI 20
+#define AHB_HANG2_SZ 1
+#define HCI_TRX_FINISH2_MSK 0x00200000
+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
+#define HCI_TRX_FINISH2_SFT 21
+#define HCI_TRX_FINISH2_HI 21
+#define HCI_TRX_FINISH2_SZ 1
+#define INTR_RX_MSK 0x00400000
+#define INTR_RX_I_MSK 0xffbfffff
+#define INTR_RX_SFT 22
+#define INTR_RX_HI 22
+#define INTR_RX_SZ 1
+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
+#define HCI_INPUT_QUEUE_FULL_SFT 23
+#define HCI_INPUT_QUEUE_FULL_HI 23
+#define HCI_INPUT_QUEUE_FULL_SZ 1
+#define ALLOCATESTATUS_MSK 0x00000001
+#define ALLOCATESTATUS_I_MSK 0xfffffffe
+#define ALLOCATESTATUS_SFT 0
+#define ALLOCATESTATUS_HI 0
+#define ALLOCATESTATUS_SZ 1
+#define HCI_TRX_FINISH3_MSK 0x00000002
+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
+#define HCI_TRX_FINISH3_SFT 1
+#define HCI_TRX_FINISH3_HI 1
+#define HCI_TRX_FINISH3_SZ 1
+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
+#define HCI_IN_QUE_EMPTY2_SFT 2
+#define HCI_IN_QUE_EMPTY2_HI 2
+#define HCI_IN_QUE_EMPTY2_SZ 1
+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
+#define MTX_MNG_UPTHOLD_INT_SFT 3
+#define MTX_MNG_UPTHOLD_INT_HI 3
+#define MTX_MNG_UPTHOLD_INT_SZ 1
+#define EDCA0_UPTHOLD_INT_MSK 0x00000010
+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
+#define EDCA0_UPTHOLD_INT_SFT 4
+#define EDCA0_UPTHOLD_INT_HI 4
+#define EDCA0_UPTHOLD_INT_SZ 1
+#define EDCA1_UPTHOLD_INT_MSK 0x00000020
+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA1_UPTHOLD_INT_SFT 5
+#define EDCA1_UPTHOLD_INT_HI 5
+#define EDCA1_UPTHOLD_INT_SZ 1
+#define EDCA2_UPTHOLD_INT_MSK 0x00000040
+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA2_UPTHOLD_INT_SFT 6
+#define EDCA2_UPTHOLD_INT_HI 6
+#define EDCA2_UPTHOLD_INT_SZ 1
+#define EDCA3_UPTHOLD_INT_MSK 0x00000080
+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
+#define EDCA3_UPTHOLD_INT_SFT 7
+#define EDCA3_UPTHOLD_INT_HI 7
+#define EDCA3_UPTHOLD_INT_SZ 1
+#define TX_PAGE_REMAIN2_MSK 0x0000ff00
+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
+#define TX_PAGE_REMAIN2_SFT 8
+#define TX_PAGE_REMAIN2_HI 15
+#define TX_PAGE_REMAIN2_SZ 8
+#define TX_ID_REMAIN3_MSK 0x007f0000
+#define TX_ID_REMAIN3_I_MSK 0xff80ffff
+#define TX_ID_REMAIN3_SFT 16
+#define TX_ID_REMAIN3_HI 22
+#define TX_ID_REMAIN3_SZ 7
+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
+#define HCI_OUTPUT_FF_CNT_0_SFT 23
+#define HCI_OUTPUT_FF_CNT_0_HI 23
+#define HCI_OUTPUT_FF_CNT_0_SZ 1
+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
+#define HCI_OUTPUT_FF_CNT2_SFT 24
+#define HCI_OUTPUT_FF_CNT2_HI 27
+#define HCI_OUTPUT_FF_CNT2_SZ 4
+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
+#define HCI_INPUT_FF_CNT2_SFT 28
+#define HCI_INPUT_FF_CNT2_HI 31
+#define HCI_INPUT_FF_CNT2_SZ 4
+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
+#define F1_BLOCK_SIZE_0_REG_SFT 0
+#define F1_BLOCK_SIZE_0_REG_HI 11
+#define F1_BLOCK_SIZE_0_REG_SZ 12
+#define START_BYTE_VALUE2_MSK 0x000000ff
+#define START_BYTE_VALUE2_I_MSK 0xffffff00
+#define START_BYTE_VALUE2_SFT 0
+#define START_BYTE_VALUE2_HI 7
+#define START_BYTE_VALUE2_SZ 8
+#define COMMAND_COUNTER_MSK 0x0000ff00
+#define COMMAND_COUNTER_I_MSK 0xffff00ff
+#define COMMAND_COUNTER_SFT 8
+#define COMMAND_COUNTER_HI 15
+#define COMMAND_COUNTER_SZ 8
+#define CMD_LOG_PART1_MSK 0xffff0000
+#define CMD_LOG_PART1_I_MSK 0x0000ffff
+#define CMD_LOG_PART1_SFT 16
+#define CMD_LOG_PART1_HI 31
+#define CMD_LOG_PART1_SZ 16
+#define CMD_LOG_PART2_MSK 0x00ffffff
+#define CMD_LOG_PART2_I_MSK 0xff000000
+#define CMD_LOG_PART2_SFT 0
+#define CMD_LOG_PART2_HI 23
+#define CMD_LOG_PART2_SZ 24
+#define END_BYTE_VALUE2_MSK 0xff000000
+#define END_BYTE_VALUE2_I_MSK 0x00ffffff
+#define END_BYTE_VALUE2_SFT 24
+#define END_BYTE_VALUE2_HI 31
+#define END_BYTE_VALUE2_SZ 8
+#define RX_PACKET_LENGTH3_MSK 0x0000ffff
+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH3_SFT 0
+#define RX_PACKET_LENGTH3_HI 15
+#define RX_PACKET_LENGTH3_SZ 16
+#define RX_INT3_MSK 0x00010000
+#define RX_INT3_I_MSK 0xfffeffff
+#define RX_INT3_SFT 16
+#define RX_INT3_HI 16
+#define RX_INT3_SZ 1
+#define TX_ID_REMAIN2_MSK 0x00fe0000
+#define TX_ID_REMAIN2_I_MSK 0xff01ffff
+#define TX_ID_REMAIN2_SFT 17
+#define TX_ID_REMAIN2_HI 23
+#define TX_ID_REMAIN2_SZ 7
+#define TX_PAGE_REMAIN3_MSK 0xff000000
+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
+#define TX_PAGE_REMAIN3_SFT 24
+#define TX_PAGE_REMAIN3_HI 31
+#define TX_PAGE_REMAIN3_SZ 8
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPI_MODE_MSK 0xffffffff
+#define SPI_MODE_I_MSK 0x00000000
+#define SPI_MODE_SFT 0
+#define SPI_MODE_HI 31
+#define SPI_MODE_SZ 32
+#define RX_QUOTA_MSK 0x0000ffff
+#define RX_QUOTA_I_MSK 0xffff0000
+#define RX_QUOTA_SFT 0
+#define RX_QUOTA_HI 15
+#define RX_QUOTA_SZ 16
+#define CONDI_NUM_MSK 0x000000ff
+#define CONDI_NUM_I_MSK 0xffffff00
+#define CONDI_NUM_SFT 0
+#define CONDI_NUM_HI 7
+#define CONDI_NUM_SZ 8
+#define HOST_PATH_MSK 0x00000001
+#define HOST_PATH_I_MSK 0xfffffffe
+#define HOST_PATH_SFT 0
+#define HOST_PATH_HI 0
+#define HOST_PATH_SZ 1
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define BRST_MODE_MSK 0x00000001
+#define BRST_MODE_I_MSK 0xfffffffe
+#define BRST_MODE_SFT 0
+#define BRST_MODE_HI 0
+#define BRST_MODE_SZ 1
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define RX_FIFO_FAIL_MSK 0x00000002
+#define RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define RX_FIFO_FAIL_SFT 1
+#define RX_FIFO_FAIL_HI 1
+#define RX_FIFO_FAIL_SZ 1
+#define RX_HOST_FAIL_MSK 0x00000004
+#define RX_HOST_FAIL_I_MSK 0xfffffffb
+#define RX_HOST_FAIL_SFT 2
+#define RX_HOST_FAIL_HI 2
+#define RX_HOST_FAIL_SZ 1
+#define TX_FIFO_FAIL_MSK 0x00000008
+#define TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define TX_FIFO_FAIL_SFT 3
+#define TX_FIFO_FAIL_HI 3
+#define TX_FIFO_FAIL_SZ 1
+#define TX_HOST_FAIL_MSK 0x00000010
+#define TX_HOST_FAIL_I_MSK 0xffffffef
+#define TX_HOST_FAIL_SFT 4
+#define TX_HOST_FAIL_HI 4
+#define TX_HOST_FAIL_SZ 1
+#define SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define SPI_DOUBLE_ALLOC_SFT 5
+#define SPI_DOUBLE_ALLOC_HI 5
+#define SPI_DOUBLE_ALLOC_SZ 1
+#define SPI_TX_NO_ALLOC_MSK 0x00000040
+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define SPI_TX_NO_ALLOC_SFT 6
+#define SPI_TX_NO_ALLOC_HI 6
+#define SPI_TX_NO_ALLOC_SZ 1
+#define RDATA_RDY_MSK 0x00000080
+#define RDATA_RDY_I_MSK 0xffffff7f
+#define RDATA_RDY_SFT 7
+#define RDATA_RDY_HI 7
+#define RDATA_RDY_SZ 1
+#define SPI_ALLOC_STATUS_MSK 0x00000100
+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define SPI_ALLOC_STATUS_SFT 8
+#define SPI_ALLOC_STATUS_HI 8
+#define SPI_ALLOC_STATUS_SZ 1
+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define SPI_DBG_WR_FIFO_FULL_SFT 9
+#define SPI_DBG_WR_FIFO_FULL_HI 9
+#define SPI_DBG_WR_FIFO_FULL_SZ 1
+#define RX_LEN_MSK 0xffff0000
+#define RX_LEN_I_MSK 0x0000ffff
+#define RX_LEN_SFT 16
+#define RX_LEN_HI 31
+#define RX_LEN_SZ 16
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define SPI_TX_ALLOC_SIZE_SFT 0
+#define SPI_TX_ALLOC_SIZE_HI 7
+#define SPI_TX_ALLOC_SIZE_SZ 8
+#define RD_DAT_CNT_MSK 0x0000ffff
+#define RD_DAT_CNT_I_MSK 0xffff0000
+#define RD_DAT_CNT_SFT 0
+#define RD_DAT_CNT_HI 15
+#define RD_DAT_CNT_SZ 16
+#define RD_STS_CNT_MSK 0xffff0000
+#define RD_STS_CNT_I_MSK 0x0000ffff
+#define RD_STS_CNT_SFT 16
+#define RD_STS_CNT_HI 31
+#define RD_STS_CNT_SZ 16
+#define JUDGE_CNT_MSK 0x0000ffff
+#define JUDGE_CNT_I_MSK 0xffff0000
+#define JUDGE_CNT_SFT 0
+#define JUDGE_CNT_HI 15
+#define JUDGE_CNT_SZ 16
+#define RD_STS_CNT_CLR_MSK 0x00010000
+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define RD_STS_CNT_CLR_SFT 16
+#define RD_STS_CNT_CLR_HI 16
+#define RD_STS_CNT_CLR_SZ 1
+#define RD_DAT_CNT_CLR_MSK 0x00020000
+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define RD_DAT_CNT_CLR_SFT 17
+#define RD_DAT_CNT_CLR_HI 17
+#define RD_DAT_CNT_CLR_SZ 1
+#define JUDGE_CNT_CLR_MSK 0x00040000
+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define JUDGE_CNT_CLR_SFT 18
+#define JUDGE_CNT_CLR_HI 18
+#define JUDGE_CNT_CLR_SZ 1
+#define TX_DONE_CNT_MSK 0x0000ffff
+#define TX_DONE_CNT_I_MSK 0xffff0000
+#define TX_DONE_CNT_SFT 0
+#define TX_DONE_CNT_HI 15
+#define TX_DONE_CNT_SZ 16
+#define TX_DISCARD_CNT_MSK 0xffff0000
+#define TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define TX_DISCARD_CNT_SFT 16
+#define TX_DISCARD_CNT_HI 31
+#define TX_DISCARD_CNT_SZ 16
+#define TX_SET_CNT_MSK 0x0000ffff
+#define TX_SET_CNT_I_MSK 0xffff0000
+#define TX_SET_CNT_SFT 0
+#define TX_SET_CNT_HI 15
+#define TX_SET_CNT_SZ 16
+#define TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define TX_DISCARD_CNT_CLR_SFT 16
+#define TX_DISCARD_CNT_CLR_HI 16
+#define TX_DISCARD_CNT_CLR_SZ 1
+#define TX_DONE_CNT_CLR_MSK 0x00020000
+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define TX_DONE_CNT_CLR_SFT 17
+#define TX_DONE_CNT_CLR_HI 17
+#define TX_DONE_CNT_CLR_SZ 1
+#define TX_SET_CNT_CLR_MSK 0x00040000
+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define TX_SET_CNT_CLR_SFT 18
+#define TX_SET_CNT_CLR_HI 18
+#define TX_SET_CNT_CLR_SZ 1
+#define DAT_MODE_OFF_MSK 0x00080000
+#define DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DAT_MODE_OFF_SFT 19
+#define DAT_MODE_OFF_HI 19
+#define DAT_MODE_OFF_SZ 1
+#define TX_FIFO_RESIDUE_MSK 0x00700000
+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define TX_FIFO_RESIDUE_SFT 20
+#define TX_FIFO_RESIDUE_HI 22
+#define TX_FIFO_RESIDUE_SZ 3
+#define RX_FIFO_RESIDUE_MSK 0x07000000
+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define RX_FIFO_RESIDUE_SFT 24
+#define RX_FIFO_RESIDUE_HI 26
+#define RX_FIFO_RESIDUE_SZ 3
+#define RX_RDY_MSK 0x00000001
+#define RX_RDY_I_MSK 0xfffffffe
+#define RX_RDY_SFT 0
+#define RX_RDY_HI 0
+#define RX_RDY_SZ 1
+#define SDIO_SYS_INT_MSK 0x00000004
+#define SDIO_SYS_INT_I_MSK 0xfffffffb
+#define SDIO_SYS_INT_SFT 2
+#define SDIO_SYS_INT_HI 2
+#define SDIO_SYS_INT_SZ 1
+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define EDCA0_LOWTHOLD_INT_SFT 3
+#define EDCA0_LOWTHOLD_INT_HI 3
+#define EDCA0_LOWTHOLD_INT_SZ 1
+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define EDCA1_LOWTHOLD_INT_SFT 4
+#define EDCA1_LOWTHOLD_INT_HI 4
+#define EDCA1_LOWTHOLD_INT_SZ 1
+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA2_LOWTHOLD_INT_SFT 5
+#define EDCA2_LOWTHOLD_INT_HI 5
+#define EDCA2_LOWTHOLD_INT_SZ 1
+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA3_LOWTHOLD_INT_SFT 6
+#define EDCA3_LOWTHOLD_INT_HI 6
+#define EDCA3_LOWTHOLD_INT_SZ 1
+#define TX_LIMIT_INT_IN_MSK 0x00000080
+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_IN_SFT 7
+#define TX_LIMIT_INT_IN_HI 7
+#define TX_LIMIT_INT_IN_SZ 1
+#define SPI_FN1_MSK 0x00007f00
+#define SPI_FN1_I_MSK 0xffff80ff
+#define SPI_FN1_SFT 8
+#define SPI_FN1_HI 14
+#define SPI_FN1_SZ 7
+#define SPI_CLK_EN_INT_MSK 0x00008000
+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define SPI_CLK_EN_INT_SFT 15
+#define SPI_CLK_EN_INT_HI 15
+#define SPI_CLK_EN_INT_SZ 1
+#define SPI_HOST_MASK_MSK 0x00ff0000
+#define SPI_HOST_MASK_I_MSK 0xff00ffff
+#define SPI_HOST_MASK_SFT 16
+#define SPI_HOST_MASK_HI 23
+#define SPI_HOST_MASK_SZ 8
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define DMA_RXEND_IE_MSK 0x00000040
+#define DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DMA_RXEND_IE_SFT 6
+#define DMA_RXEND_IE_HI 6
+#define DMA_RXEND_IE_SZ 1
+#define DMA_TXEND_IE_MSK 0x00000080
+#define DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DMA_TXEND_IE_SFT 7
+#define DMA_TXEND_IE_HI 7
+#define DMA_TXEND_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define DAT_UART_DATA_MSK 0x000000ff
+#define DAT_UART_DATA_I_MSK 0xffffff00
+#define DAT_UART_DATA_SFT 0
+#define DAT_UART_DATA_HI 7
+#define DAT_UART_DATA_SZ 8
+#define DAT_DATA_RDY_IE_MSK 0x00000001
+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_IE_SFT 0
+#define DAT_DATA_RDY_IE_HI 0
+#define DAT_DATA_RDY_IE_SZ 1
+#define DAT_THR_EMPTY_IE_MSK 0x00000002
+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
+#define DAT_THR_EMPTY_IE_SFT 1
+#define DAT_THR_EMPTY_IE_HI 1
+#define DAT_THR_EMPTY_IE_SZ 1
+#define DAT_RX_LINESTS_IE_MSK 0x00000004
+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
+#define DAT_RX_LINESTS_IE_SFT 2
+#define DAT_RX_LINESTS_IE_HI 2
+#define DAT_RX_LINESTS_IE_SZ 1
+#define DAT_MDM_STS_IE_MSK 0x00000008
+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
+#define DAT_MDM_STS_IE_SFT 3
+#define DAT_MDM_STS_IE_HI 3
+#define DAT_MDM_STS_IE_SZ 1
+#define DAT_DMA_RXEND_IE_MSK 0x00000040
+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DAT_DMA_RXEND_IE_SFT 6
+#define DAT_DMA_RXEND_IE_HI 6
+#define DAT_DMA_RXEND_IE_SZ 1
+#define DAT_DMA_TXEND_IE_MSK 0x00000080
+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DAT_DMA_TXEND_IE_SFT 7
+#define DAT_DMA_TXEND_IE_HI 7
+#define DAT_DMA_TXEND_IE_SZ 1
+#define DAT_FIFO_EN_MSK 0x00000001
+#define DAT_FIFO_EN_I_MSK 0xfffffffe
+#define DAT_FIFO_EN_SFT 0
+#define DAT_FIFO_EN_HI 0
+#define DAT_FIFO_EN_SZ 1
+#define DAT_RXFIFO_RST_MSK 0x00000002
+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
+#define DAT_RXFIFO_RST_SFT 1
+#define DAT_RXFIFO_RST_HI 1
+#define DAT_RXFIFO_RST_SZ 1
+#define DAT_TXFIFO_RST_MSK 0x00000004
+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
+#define DAT_TXFIFO_RST_SFT 2
+#define DAT_TXFIFO_RST_HI 2
+#define DAT_TXFIFO_RST_SZ 1
+#define DAT_DMA_MODE_MSK 0x00000008
+#define DAT_DMA_MODE_I_MSK 0xfffffff7
+#define DAT_DMA_MODE_SFT 3
+#define DAT_DMA_MODE_HI 3
+#define DAT_DMA_MODE_SZ 1
+#define DAT_EN_AUTO_RTS_MSK 0x00000010
+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
+#define DAT_EN_AUTO_RTS_SFT 4
+#define DAT_EN_AUTO_RTS_HI 4
+#define DAT_EN_AUTO_RTS_SZ 1
+#define DAT_EN_AUTO_CTS_MSK 0x00000020
+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
+#define DAT_EN_AUTO_CTS_SFT 5
+#define DAT_EN_AUTO_CTS_HI 5
+#define DAT_EN_AUTO_CTS_SZ 1
+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define DAT_RXFIFO_TRGLVL_SFT 6
+#define DAT_RXFIFO_TRGLVL_HI 7
+#define DAT_RXFIFO_TRGLVL_SZ 2
+#define DAT_WORD_LEN_MSK 0x00000003
+#define DAT_WORD_LEN_I_MSK 0xfffffffc
+#define DAT_WORD_LEN_SFT 0
+#define DAT_WORD_LEN_HI 1
+#define DAT_WORD_LEN_SZ 2
+#define DAT_STOP_BIT_MSK 0x00000004
+#define DAT_STOP_BIT_I_MSK 0xfffffffb
+#define DAT_STOP_BIT_SFT 2
+#define DAT_STOP_BIT_HI 2
+#define DAT_STOP_BIT_SZ 1
+#define DAT_PARITY_EN_MSK 0x00000008
+#define DAT_PARITY_EN_I_MSK 0xfffffff7
+#define DAT_PARITY_EN_SFT 3
+#define DAT_PARITY_EN_HI 3
+#define DAT_PARITY_EN_SZ 1
+#define DAT_EVEN_PARITY_MSK 0x00000010
+#define DAT_EVEN_PARITY_I_MSK 0xffffffef
+#define DAT_EVEN_PARITY_SFT 4
+#define DAT_EVEN_PARITY_HI 4
+#define DAT_EVEN_PARITY_SZ 1
+#define DAT_FORCE_PARITY_MSK 0x00000020
+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
+#define DAT_FORCE_PARITY_SFT 5
+#define DAT_FORCE_PARITY_HI 5
+#define DAT_FORCE_PARITY_SZ 1
+#define DAT_SET_BREAK_MSK 0x00000040
+#define DAT_SET_BREAK_I_MSK 0xffffffbf
+#define DAT_SET_BREAK_SFT 6
+#define DAT_SET_BREAK_HI 6
+#define DAT_SET_BREAK_SZ 1
+#define DAT_DLAB_MSK 0x00000080
+#define DAT_DLAB_I_MSK 0xffffff7f
+#define DAT_DLAB_SFT 7
+#define DAT_DLAB_HI 7
+#define DAT_DLAB_SZ 1
+#define DAT_DTR_MSK 0x00000001
+#define DAT_DTR_I_MSK 0xfffffffe
+#define DAT_DTR_SFT 0
+#define DAT_DTR_HI 0
+#define DAT_DTR_SZ 1
+#define DAT_RTS_MSK 0x00000002
+#define DAT_RTS_I_MSK 0xfffffffd
+#define DAT_RTS_SFT 1
+#define DAT_RTS_HI 1
+#define DAT_RTS_SZ 1
+#define DAT_OUT_1_MSK 0x00000004
+#define DAT_OUT_1_I_MSK 0xfffffffb
+#define DAT_OUT_1_SFT 2
+#define DAT_OUT_1_HI 2
+#define DAT_OUT_1_SZ 1
+#define DAT_OUT_2_MSK 0x00000008
+#define DAT_OUT_2_I_MSK 0xfffffff7
+#define DAT_OUT_2_SFT 3
+#define DAT_OUT_2_HI 3
+#define DAT_OUT_2_SZ 1
+#define DAT_LOOP_BACK_MSK 0x00000010
+#define DAT_LOOP_BACK_I_MSK 0xffffffef
+#define DAT_LOOP_BACK_SFT 4
+#define DAT_LOOP_BACK_HI 4
+#define DAT_LOOP_BACK_SZ 1
+#define DAT_DATA_RDY_MSK 0x00000001
+#define DAT_DATA_RDY_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_SFT 0
+#define DAT_DATA_RDY_HI 0
+#define DAT_DATA_RDY_SZ 1
+#define DAT_OVERRUN_ERR_MSK 0x00000002
+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
+#define DAT_OVERRUN_ERR_SFT 1
+#define DAT_OVERRUN_ERR_HI 1
+#define DAT_OVERRUN_ERR_SZ 1
+#define DAT_PARITY_ERR_MSK 0x00000004
+#define DAT_PARITY_ERR_I_MSK 0xfffffffb
+#define DAT_PARITY_ERR_SFT 2
+#define DAT_PARITY_ERR_HI 2
+#define DAT_PARITY_ERR_SZ 1
+#define DAT_FRAMING_ERR_MSK 0x00000008
+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
+#define DAT_FRAMING_ERR_SFT 3
+#define DAT_FRAMING_ERR_HI 3
+#define DAT_FRAMING_ERR_SZ 1
+#define DAT_BREAK_INT_MSK 0x00000010
+#define DAT_BREAK_INT_I_MSK 0xffffffef
+#define DAT_BREAK_INT_SFT 4
+#define DAT_BREAK_INT_HI 4
+#define DAT_BREAK_INT_SZ 1
+#define DAT_THR_EMPTY_MSK 0x00000020
+#define DAT_THR_EMPTY_I_MSK 0xffffffdf
+#define DAT_THR_EMPTY_SFT 5
+#define DAT_THR_EMPTY_HI 5
+#define DAT_THR_EMPTY_SZ 1
+#define DAT_TX_EMPTY_MSK 0x00000040
+#define DAT_TX_EMPTY_I_MSK 0xffffffbf
+#define DAT_TX_EMPTY_SFT 6
+#define DAT_TX_EMPTY_HI 6
+#define DAT_TX_EMPTY_SZ 1
+#define DAT_FIFODATA_ERR_MSK 0x00000080
+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
+#define DAT_FIFODATA_ERR_SFT 7
+#define DAT_FIFODATA_ERR_HI 7
+#define DAT_FIFODATA_ERR_SZ 1
+#define DAT_DELTA_CTS_MSK 0x00000001
+#define DAT_DELTA_CTS_I_MSK 0xfffffffe
+#define DAT_DELTA_CTS_SFT 0
+#define DAT_DELTA_CTS_HI 0
+#define DAT_DELTA_CTS_SZ 1
+#define DAT_DELTA_DSR_MSK 0x00000002
+#define DAT_DELTA_DSR_I_MSK 0xfffffffd
+#define DAT_DELTA_DSR_SFT 1
+#define DAT_DELTA_DSR_HI 1
+#define DAT_DELTA_DSR_SZ 1
+#define DAT_TRAILEDGE_RI_MSK 0x00000004
+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
+#define DAT_TRAILEDGE_RI_SFT 2
+#define DAT_TRAILEDGE_RI_HI 2
+#define DAT_TRAILEDGE_RI_SZ 1
+#define DAT_DELTA_CD_MSK 0x00000008
+#define DAT_DELTA_CD_I_MSK 0xfffffff7
+#define DAT_DELTA_CD_SFT 3
+#define DAT_DELTA_CD_HI 3
+#define DAT_DELTA_CD_SZ 1
+#define DAT_CTS_MSK 0x00000010
+#define DAT_CTS_I_MSK 0xffffffef
+#define DAT_CTS_SFT 4
+#define DAT_CTS_HI 4
+#define DAT_CTS_SZ 1
+#define DAT_DSR_MSK 0x00000020
+#define DAT_DSR_I_MSK 0xffffffdf
+#define DAT_DSR_SFT 5
+#define DAT_DSR_HI 5
+#define DAT_DSR_SZ 1
+#define DAT_RI_MSK 0x00000040
+#define DAT_RI_I_MSK 0xffffffbf
+#define DAT_RI_SFT 6
+#define DAT_RI_HI 6
+#define DAT_RI_SZ 1
+#define DAT_CD_MSK 0x00000080
+#define DAT_CD_I_MSK 0xffffff7f
+#define DAT_CD_SFT 7
+#define DAT_CD_HI 7
+#define DAT_CD_SZ 1
+#define DAT_BRDC_DIV_MSK 0x0000ffff
+#define DAT_BRDC_DIV_I_MSK 0xffff0000
+#define DAT_BRDC_DIV_SFT 0
+#define DAT_BRDC_DIV_HI 15
+#define DAT_BRDC_DIV_SZ 16
+#define DAT_RTHR_L_MSK 0x0000000f
+#define DAT_RTHR_L_I_MSK 0xfffffff0
+#define DAT_RTHR_L_SFT 0
+#define DAT_RTHR_L_HI 3
+#define DAT_RTHR_L_SZ 4
+#define DAT_RTHR_H_MSK 0x000000f0
+#define DAT_RTHR_H_I_MSK 0xffffff0f
+#define DAT_RTHR_H_SFT 4
+#define DAT_RTHR_H_HI 7
+#define DAT_RTHR_H_SZ 4
+#define DAT_INT_IDCODE_MSK 0x0000000f
+#define DAT_INT_IDCODE_I_MSK 0xfffffff0
+#define DAT_INT_IDCODE_SFT 0
+#define DAT_INT_IDCODE_HI 3
+#define DAT_INT_IDCODE_SZ 4
+#define DAT_FIFOS_ENABLED_MSK 0x000000c0
+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
+#define DAT_FIFOS_ENABLED_SFT 6
+#define DAT_FIFOS_ENABLED_HI 7
+#define DAT_FIFOS_ENABLED_SZ 2
+#define MASK_TOP_MSK 0xffffffff
+#define MASK_TOP_I_MSK 0x00000000
+#define MASK_TOP_SFT 0
+#define MASK_TOP_HI 31
+#define MASK_TOP_SZ 32
+#define INT_MODE_MSK 0xffffffff
+#define INT_MODE_I_MSK 0x00000000
+#define INT_MODE_SFT 0
+#define INT_MODE_HI 31
+#define INT_MODE_SZ 32
+#define IRQ_PHY_0_MSK 0x00000001
+#define IRQ_PHY_0_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SFT 0
+#define IRQ_PHY_0_HI 0
+#define IRQ_PHY_0_SZ 1
+#define IRQ_PHY_1_MSK 0x00000002
+#define IRQ_PHY_1_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SFT 1
+#define IRQ_PHY_1_HI 1
+#define IRQ_PHY_1_SZ 1
+#define IRQ_SDIO_MSK 0x00000004
+#define IRQ_SDIO_I_MSK 0xfffffffb
+#define IRQ_SDIO_SFT 2
+#define IRQ_SDIO_HI 2
+#define IRQ_SDIO_SZ 1
+#define IRQ_BEACON_DONE_MSK 0x00000008
+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SFT 3
+#define IRQ_BEACON_DONE_HI 3
+#define IRQ_BEACON_DONE_SZ 1
+#define IRQ_BEACON_MSK 0x00000010
+#define IRQ_BEACON_I_MSK 0xffffffef
+#define IRQ_BEACON_SFT 4
+#define IRQ_BEACON_HI 4
+#define IRQ_BEACON_SZ 1
+#define IRQ_PRE_BEACON_MSK 0x00000020
+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SFT 5
+#define IRQ_PRE_BEACON_HI 5
+#define IRQ_PRE_BEACON_SZ 1
+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SFT 6
+#define IRQ_EDCA0_TX_DONE_HI 6
+#define IRQ_EDCA0_TX_DONE_SZ 1
+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SFT 7
+#define IRQ_EDCA1_TX_DONE_HI 7
+#define IRQ_EDCA1_TX_DONE_SZ 1
+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SFT 8
+#define IRQ_EDCA2_TX_DONE_HI 8
+#define IRQ_EDCA2_TX_DONE_SZ 1
+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SFT 9
+#define IRQ_EDCA3_TX_DONE_HI 9
+#define IRQ_EDCA3_TX_DONE_SZ 1
+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SFT 10
+#define IRQ_EDCA4_TX_DONE_HI 10
+#define IRQ_EDCA4_TX_DONE_SZ 1
+#define IRQ_BEACON_DTIM_MSK 0x00001000
+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SFT 12
+#define IRQ_BEACON_DTIM_HI 12
+#define IRQ_BEACON_DTIM_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
+#define IRQ_FENCE_HIT_INT_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SFT 17
+#define IRQ_FENCE_HIT_INT_HI 17
+#define IRQ_FENCE_HIT_INT_SZ 1
+#define IRQ_ILL_ADDR_INT_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SFT 18
+#define IRQ_ILL_ADDR_INT_HI 18
+#define IRQ_ILL_ADDR_INT_SZ 1
+#define IRQ_MBOX_MSK 0x00080000
+#define IRQ_MBOX_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SFT 19
+#define IRQ_MBOX_HI 19
+#define IRQ_MBOX_SZ 1
+#define IRQ_US_TIMER0_MSK 0x00100000
+#define IRQ_US_TIMER0_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SFT 20
+#define IRQ_US_TIMER0_HI 20
+#define IRQ_US_TIMER0_SZ 1
+#define IRQ_US_TIMER1_MSK 0x00200000
+#define IRQ_US_TIMER1_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SFT 21
+#define IRQ_US_TIMER1_HI 21
+#define IRQ_US_TIMER1_SZ 1
+#define IRQ_US_TIMER2_MSK 0x00400000
+#define IRQ_US_TIMER2_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SFT 22
+#define IRQ_US_TIMER2_HI 22
+#define IRQ_US_TIMER2_SZ 1
+#define IRQ_US_TIMER3_MSK 0x00800000
+#define IRQ_US_TIMER3_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SFT 23
+#define IRQ_US_TIMER3_HI 23
+#define IRQ_US_TIMER3_SZ 1
+#define IRQ_MS_TIMER0_MSK 0x01000000
+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SFT 24
+#define IRQ_MS_TIMER0_HI 24
+#define IRQ_MS_TIMER0_SZ 1
+#define IRQ_MS_TIMER1_MSK 0x02000000
+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SFT 25
+#define IRQ_MS_TIMER1_HI 25
+#define IRQ_MS_TIMER1_SZ 1
+#define IRQ_MS_TIMER2_MSK 0x04000000
+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SFT 26
+#define IRQ_MS_TIMER2_HI 26
+#define IRQ_MS_TIMER2_SZ 1
+#define IRQ_MS_TIMER3_MSK 0x08000000
+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SFT 27
+#define IRQ_MS_TIMER3_HI 27
+#define IRQ_MS_TIMER3_SZ 1
+#define IRQ_TX_LIMIT_INT_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SFT 28
+#define IRQ_TX_LIMIT_INT_HI 28
+#define IRQ_TX_LIMIT_INT_SZ 1
+#define IRQ_DMA0_MSK 0x20000000
+#define IRQ_DMA0_I_MSK 0xdfffffff
+#define IRQ_DMA0_SFT 29
+#define IRQ_DMA0_HI 29
+#define IRQ_DMA0_SZ 1
+#define IRQ_CO_DMA_MSK 0x40000000
+#define IRQ_CO_DMA_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SFT 30
+#define IRQ_CO_DMA_HI 30
+#define IRQ_CO_DMA_SZ 1
+#define IRQ_PERI_GROUP_MSK 0x80000000
+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SFT 31
+#define IRQ_PERI_GROUP_HI 31
+#define IRQ_PERI_GROUP_SZ 1
+#define FIQ_STATUS_MSK 0xffffffff
+#define FIQ_STATUS_I_MSK 0x00000000
+#define FIQ_STATUS_SFT 0
+#define FIQ_STATUS_HI 31
+#define FIQ_STATUS_SZ 32
+#define IRQ_RAW_MSK 0xffffffff
+#define IRQ_RAW_I_MSK 0x00000000
+#define IRQ_RAW_SFT 0
+#define IRQ_RAW_HI 31
+#define IRQ_RAW_SZ 32
+#define FIQ_RAW_MSK 0xffffffff
+#define FIQ_RAW_I_MSK 0x00000000
+#define FIQ_RAW_SFT 0
+#define FIQ_RAW_HI 31
+#define FIQ_RAW_SZ 32
+#define INT_PERI_MASK_MSK 0xffffffff
+#define INT_PERI_MASK_I_MSK 0x00000000
+#define INT_PERI_MASK_SFT 0
+#define INT_PERI_MASK_HI 31
+#define INT_PERI_MASK_SZ 32
+#define PERI_RTC_MSK 0x00000001
+#define PERI_RTC_I_MSK 0xfffffffe
+#define PERI_RTC_SFT 0
+#define PERI_RTC_HI 0
+#define PERI_RTC_SZ 1
+#define IRQ_UART0_TX_MSK 0x00000002
+#define IRQ_UART0_TX_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SFT 1
+#define IRQ_UART0_TX_HI 1
+#define IRQ_UART0_TX_SZ 1
+#define IRQ_UART0_RX_MSK 0x00000004
+#define IRQ_UART0_RX_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SFT 2
+#define IRQ_UART0_RX_HI 2
+#define IRQ_UART0_RX_SZ 1
+#define PERI_GPI_2_MSK 0x00000008
+#define PERI_GPI_2_I_MSK 0xfffffff7
+#define PERI_GPI_2_SFT 3
+#define PERI_GPI_2_HI 3
+#define PERI_GPI_2_SZ 1
+#define IRQ_SPI_IPC_MSK 0x00000010
+#define IRQ_SPI_IPC_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SFT 4
+#define IRQ_SPI_IPC_HI 4
+#define IRQ_SPI_IPC_SZ 1
+#define PERI_GPI_1_0_MSK 0x00000060
+#define PERI_GPI_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_1_0_SFT 5
+#define PERI_GPI_1_0_HI 6
+#define PERI_GPI_1_0_SZ 2
+#define SCRT_INT_1_MSK 0x00000080
+#define SCRT_INT_1_I_MSK 0xffffff7f
+#define SCRT_INT_1_SFT 7
+#define SCRT_INT_1_HI 7
+#define SCRT_INT_1_SZ 1
+#define MMU_ALC_ERR_MSK 0x00000100
+#define MMU_ALC_ERR_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SFT 8
+#define MMU_ALC_ERR_HI 8
+#define MMU_ALC_ERR_SZ 1
+#define MMU_RLS_ERR_MSK 0x00000200
+#define MMU_RLS_ERR_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SFT 9
+#define MMU_RLS_ERR_HI 9
+#define MMU_RLS_ERR_SZ 1
+#define ID_MNG_INT_1_MSK 0x00000400
+#define ID_MNG_INT_1_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SFT 10
+#define ID_MNG_INT_1_HI 10
+#define ID_MNG_INT_1_SZ 1
+#define MBOX_INT_1_MSK 0x00000800
+#define MBOX_INT_1_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SFT 11
+#define MBOX_INT_1_HI 11
+#define MBOX_INT_1_SZ 1
+#define MBOX_INT_2_MSK 0x00001000
+#define MBOX_INT_2_I_MSK 0xffffefff
+#define MBOX_INT_2_SFT 12
+#define MBOX_INT_2_HI 12
+#define MBOX_INT_2_SZ 1
+#define MBOX_INT_3_MSK 0x00002000
+#define MBOX_INT_3_I_MSK 0xffffdfff
+#define MBOX_INT_3_SFT 13
+#define MBOX_INT_3_HI 13
+#define MBOX_INT_3_SZ 1
+#define HCI_INT_1_MSK 0x00004000
+#define HCI_INT_1_I_MSK 0xffffbfff
+#define HCI_INT_1_SFT 14
+#define HCI_INT_1_HI 14
+#define HCI_INT_1_SZ 1
+#define UART_RX_TIMEOUT_MSK 0x00008000
+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SFT 15
+#define UART_RX_TIMEOUT_HI 15
+#define UART_RX_TIMEOUT_SZ 1
+#define UART_MULTI_IRQ_MSK 0x00010000
+#define UART_MULTI_IRQ_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SFT 16
+#define UART_MULTI_IRQ_HI 16
+#define UART_MULTI_IRQ_SZ 1
+#define ID_MNG_INT_2_MSK 0x00020000
+#define ID_MNG_INT_2_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SFT 17
+#define ID_MNG_INT_2_HI 17
+#define ID_MNG_INT_2_SZ 1
+#define DMN_NOHIT_INT_MSK 0x00040000
+#define DMN_NOHIT_INT_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SFT 18
+#define DMN_NOHIT_INT_HI 18
+#define DMN_NOHIT_INT_SZ 1
+#define ID_THOLD_RX_MSK 0x00080000
+#define ID_THOLD_RX_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SFT 19
+#define ID_THOLD_RX_HI 19
+#define ID_THOLD_RX_SZ 1
+#define ID_THOLD_TX_MSK 0x00100000
+#define ID_THOLD_TX_I_MSK 0xffefffff
+#define ID_THOLD_TX_SFT 20
+#define ID_THOLD_TX_HI 20
+#define ID_THOLD_TX_SZ 1
+#define ID_DOUBLE_RLS_MSK 0x00200000
+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SFT 21
+#define ID_DOUBLE_RLS_HI 21
+#define ID_DOUBLE_RLS_SZ 1
+#define RX_ID_LEN_THOLD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SFT 22
+#define RX_ID_LEN_THOLD_HI 22
+#define RX_ID_LEN_THOLD_SZ 1
+#define TX_ID_LEN_THOLD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SFT 23
+#define TX_ID_LEN_THOLD_HI 23
+#define TX_ID_LEN_THOLD_SZ 1
+#define ALL_ID_LEN_THOLD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SFT 24
+#define ALL_ID_LEN_THOLD_HI 24
+#define ALL_ID_LEN_THOLD_SZ 1
+#define DMN_MCU_INT_MSK 0x02000000
+#define DMN_MCU_INT_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SFT 25
+#define DMN_MCU_INT_HI 25
+#define DMN_MCU_INT_SZ 1
+#define IRQ_DAT_UART_TX_MSK 0x04000000
+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SFT 26
+#define IRQ_DAT_UART_TX_HI 26
+#define IRQ_DAT_UART_TX_SZ 1
+#define IRQ_DAT_UART_RX_MSK 0x08000000
+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SFT 27
+#define IRQ_DAT_UART_RX_HI 27
+#define IRQ_DAT_UART_RX_SZ 1
+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SFT 28
+#define DAT_UART_RX_TIMEOUT_HI 28
+#define DAT_UART_RX_TIMEOUT_SZ 1
+#define DAT_UART_MULTI_IRQ_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SFT 29
+#define DAT_UART_MULTI_IRQ_HI 29
+#define DAT_UART_MULTI_IRQ_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
+#define INTR_PERI_RAW_MSK 0xffffffff
+#define INTR_PERI_RAW_I_MSK 0x00000000
+#define INTR_PERI_RAW_SFT 0
+#define INTR_PERI_RAW_HI 31
+#define INTR_PERI_RAW_SZ 32
+#define INTR_GPI00_CFG_MSK 0x00000003
+#define INTR_GPI00_CFG_I_MSK 0xfffffffc
+#define INTR_GPI00_CFG_SFT 0
+#define INTR_GPI00_CFG_HI 1
+#define INTR_GPI00_CFG_SZ 2
+#define INTR_GPI01_CFG_MSK 0x0000000c
+#define INTR_GPI01_CFG_I_MSK 0xfffffff3
+#define INTR_GPI01_CFG_SFT 2
+#define INTR_GPI01_CFG_HI 3
+#define INTR_GPI01_CFG_SZ 2
+#define SYS_RST_INT_MSK 0x00000001
+#define SYS_RST_INT_I_MSK 0xfffffffe
+#define SYS_RST_INT_SFT 0
+#define SYS_RST_INT_HI 0
+#define SYS_RST_INT_SZ 1
+#define SPI_IPC_ADDR_MSK 0xffffffff
+#define SPI_IPC_ADDR_I_MSK 0x00000000
+#define SPI_IPC_ADDR_SFT 0
+#define SPI_IPC_ADDR_HI 31
+#define SPI_IPC_ADDR_SZ 32
+#define SD_MASK_TOP_MSK 0xffffffff
+#define SD_MASK_TOP_I_MSK 0x00000000
+#define SD_MASK_TOP_SFT 0
+#define SD_MASK_TOP_HI 31
+#define SD_MASK_TOP_SZ 32
+#define IRQ_PHY_0_SD_MSK 0x00000001
+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SD_SFT 0
+#define IRQ_PHY_0_SD_HI 0
+#define IRQ_PHY_0_SD_SZ 1
+#define IRQ_PHY_1_SD_MSK 0x00000002
+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SD_SFT 1
+#define IRQ_PHY_1_SD_HI 1
+#define IRQ_PHY_1_SD_SZ 1
+#define IRQ_SDIO_SD_MSK 0x00000004
+#define IRQ_SDIO_SD_I_MSK 0xfffffffb
+#define IRQ_SDIO_SD_SFT 2
+#define IRQ_SDIO_SD_HI 2
+#define IRQ_SDIO_SD_SZ 1
+#define IRQ_BEACON_DONE_SD_MSK 0x00000008
+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SD_SFT 3
+#define IRQ_BEACON_DONE_SD_HI 3
+#define IRQ_BEACON_DONE_SD_SZ 1
+#define IRQ_BEACON_SD_MSK 0x00000010
+#define IRQ_BEACON_SD_I_MSK 0xffffffef
+#define IRQ_BEACON_SD_SFT 4
+#define IRQ_BEACON_SD_HI 4
+#define IRQ_BEACON_SD_SZ 1
+#define IRQ_PRE_BEACON_SD_MSK 0x00000020
+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SD_SFT 5
+#define IRQ_PRE_BEACON_SD_HI 5
+#define IRQ_PRE_BEACON_SD_SZ 1
+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SD_SFT 6
+#define IRQ_EDCA0_TX_DONE_SD_HI 6
+#define IRQ_EDCA0_TX_DONE_SD_SZ 1
+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SD_SFT 7
+#define IRQ_EDCA1_TX_DONE_SD_HI 7
+#define IRQ_EDCA1_TX_DONE_SD_SZ 1
+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SD_SFT 8
+#define IRQ_EDCA2_TX_DONE_SD_HI 8
+#define IRQ_EDCA2_TX_DONE_SD_SZ 1
+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SD_SFT 9
+#define IRQ_EDCA3_TX_DONE_SD_HI 9
+#define IRQ_EDCA3_TX_DONE_SD_SZ 1
+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SD_SFT 10
+#define IRQ_EDCA4_TX_DONE_SD_HI 10
+#define IRQ_EDCA4_TX_DONE_SD_SZ 1
+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SD_SFT 12
+#define IRQ_BEACON_DTIM_SD_HI 12
+#define IRQ_BEACON_DTIM_SD_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SD_SFT 17
+#define IRQ_FENCE_HIT_INT_SD_HI 17
+#define IRQ_FENCE_HIT_INT_SD_SZ 1
+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SD_SFT 18
+#define IRQ_ILL_ADDR_INT_SD_HI 18
+#define IRQ_ILL_ADDR_INT_SD_SZ 1
+#define IRQ_MBOX_SD_MSK 0x00080000
+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SD_SFT 19
+#define IRQ_MBOX_SD_HI 19
+#define IRQ_MBOX_SD_SZ 1
+#define IRQ_US_TIMER0_SD_MSK 0x00100000
+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SD_SFT 20
+#define IRQ_US_TIMER0_SD_HI 20
+#define IRQ_US_TIMER0_SD_SZ 1
+#define IRQ_US_TIMER1_SD_MSK 0x00200000
+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SD_SFT 21
+#define IRQ_US_TIMER1_SD_HI 21
+#define IRQ_US_TIMER1_SD_SZ 1
+#define IRQ_US_TIMER2_SD_MSK 0x00400000
+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SD_SFT 22
+#define IRQ_US_TIMER2_SD_HI 22
+#define IRQ_US_TIMER2_SD_SZ 1
+#define IRQ_US_TIMER3_SD_MSK 0x00800000
+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SD_SFT 23
+#define IRQ_US_TIMER3_SD_HI 23
+#define IRQ_US_TIMER3_SD_SZ 1
+#define IRQ_MS_TIMER0_SD_MSK 0x01000000
+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SD_SFT 24
+#define IRQ_MS_TIMER0_SD_HI 24
+#define IRQ_MS_TIMER0_SD_SZ 1
+#define IRQ_MS_TIMER1_SD_MSK 0x02000000
+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SD_SFT 25
+#define IRQ_MS_TIMER1_SD_HI 25
+#define IRQ_MS_TIMER1_SD_SZ 1
+#define IRQ_MS_TIMER2_SD_MSK 0x04000000
+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SD_SFT 26
+#define IRQ_MS_TIMER2_SD_HI 26
+#define IRQ_MS_TIMER2_SD_SZ 1
+#define IRQ_MS_TIMER3_SD_MSK 0x08000000
+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SD_SFT 27
+#define IRQ_MS_TIMER3_SD_HI 27
+#define IRQ_MS_TIMER3_SD_SZ 1
+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SD_SFT 28
+#define IRQ_TX_LIMIT_INT_SD_HI 28
+#define IRQ_TX_LIMIT_INT_SD_SZ 1
+#define IRQ_DMA0_SD_MSK 0x20000000
+#define IRQ_DMA0_SD_I_MSK 0xdfffffff
+#define IRQ_DMA0_SD_SFT 29
+#define IRQ_DMA0_SD_HI 29
+#define IRQ_DMA0_SD_SZ 1
+#define IRQ_CO_DMA_SD_MSK 0x40000000
+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SD_SFT 30
+#define IRQ_CO_DMA_SD_HI 30
+#define IRQ_CO_DMA_SD_SZ 1
+#define IRQ_PERI_GROUP_SD_MSK 0x80000000
+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SD_SFT 31
+#define IRQ_PERI_GROUP_SD_HI 31
+#define IRQ_PERI_GROUP_SD_SZ 1
+#define INT_PERI_MASK_SD_MSK 0xffffffff
+#define INT_PERI_MASK_SD_I_MSK 0x00000000
+#define INT_PERI_MASK_SD_SFT 0
+#define INT_PERI_MASK_SD_HI 31
+#define INT_PERI_MASK_SD_SZ 32
+#define PERI_RTC_SD_MSK 0x00000001
+#define PERI_RTC_SD_I_MSK 0xfffffffe
+#define PERI_RTC_SD_SFT 0
+#define PERI_RTC_SD_HI 0
+#define PERI_RTC_SD_SZ 1
+#define IRQ_UART0_TX_SD_MSK 0x00000002
+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SD_SFT 1
+#define IRQ_UART0_TX_SD_HI 1
+#define IRQ_UART0_TX_SD_SZ 1
+#define IRQ_UART0_RX_SD_MSK 0x00000004
+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SD_SFT 2
+#define IRQ_UART0_RX_SD_HI 2
+#define IRQ_UART0_RX_SD_SZ 1
+#define PERI_GPI_SD_2_MSK 0x00000008
+#define PERI_GPI_SD_2_I_MSK 0xfffffff7
+#define PERI_GPI_SD_2_SFT 3
+#define PERI_GPI_SD_2_HI 3
+#define PERI_GPI_SD_2_SZ 1
+#define IRQ_SPI_IPC_SD_MSK 0x00000010
+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SD_SFT 4
+#define IRQ_SPI_IPC_SD_HI 4
+#define IRQ_SPI_IPC_SD_SZ 1
+#define PERI_GPI_SD_1_0_MSK 0x00000060
+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_SD_1_0_SFT 5
+#define PERI_GPI_SD_1_0_HI 6
+#define PERI_GPI_SD_1_0_SZ 2
+#define SCRT_INT_1_SD_MSK 0x00000080
+#define SCRT_INT_1_SD_I_MSK 0xffffff7f
+#define SCRT_INT_1_SD_SFT 7
+#define SCRT_INT_1_SD_HI 7
+#define SCRT_INT_1_SD_SZ 1
+#define MMU_ALC_ERR_SD_MSK 0x00000100
+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SD_SFT 8
+#define MMU_ALC_ERR_SD_HI 8
+#define MMU_ALC_ERR_SD_SZ 1
+#define MMU_RLS_ERR_SD_MSK 0x00000200
+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SD_SFT 9
+#define MMU_RLS_ERR_SD_HI 9
+#define MMU_RLS_ERR_SD_SZ 1
+#define ID_MNG_INT_1_SD_MSK 0x00000400
+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SD_SFT 10
+#define ID_MNG_INT_1_SD_HI 10
+#define ID_MNG_INT_1_SD_SZ 1
+#define MBOX_INT_1_SD_MSK 0x00000800
+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SD_SFT 11
+#define MBOX_INT_1_SD_HI 11
+#define MBOX_INT_1_SD_SZ 1
+#define MBOX_INT_2_SD_MSK 0x00001000
+#define MBOX_INT_2_SD_I_MSK 0xffffefff
+#define MBOX_INT_2_SD_SFT 12
+#define MBOX_INT_2_SD_HI 12
+#define MBOX_INT_2_SD_SZ 1
+#define MBOX_INT_3_SD_MSK 0x00002000
+#define MBOX_INT_3_SD_I_MSK 0xffffdfff
+#define MBOX_INT_3_SD_SFT 13
+#define MBOX_INT_3_SD_HI 13
+#define MBOX_INT_3_SD_SZ 1
+#define HCI_INT_1_SD_MSK 0x00004000
+#define HCI_INT_1_SD_I_MSK 0xffffbfff
+#define HCI_INT_1_SD_SFT 14
+#define HCI_INT_1_SD_HI 14
+#define HCI_INT_1_SD_SZ 1
+#define UART_RX_TIMEOUT_SD_MSK 0x00008000
+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SD_SFT 15
+#define UART_RX_TIMEOUT_SD_HI 15
+#define UART_RX_TIMEOUT_SD_SZ 1
+#define UART_MULTI_IRQ_SD_MSK 0x00010000
+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SD_SFT 16
+#define UART_MULTI_IRQ_SD_HI 16
+#define UART_MULTI_IRQ_SD_SZ 1
+#define ID_MNG_INT_2_SD_MSK 0x00020000
+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SD_SFT 17
+#define ID_MNG_INT_2_SD_HI 17
+#define ID_MNG_INT_2_SD_SZ 1
+#define DMN_NOHIT_INT_SD_MSK 0x00040000
+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SD_SFT 18
+#define DMN_NOHIT_INT_SD_HI 18
+#define DMN_NOHIT_INT_SD_SZ 1
+#define ID_THOLD_RX_SD_MSK 0x00080000
+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SD_SFT 19
+#define ID_THOLD_RX_SD_HI 19
+#define ID_THOLD_RX_SD_SZ 1
+#define ID_THOLD_TX_SD_MSK 0x00100000
+#define ID_THOLD_TX_SD_I_MSK 0xffefffff
+#define ID_THOLD_TX_SD_SFT 20
+#define ID_THOLD_TX_SD_HI 20
+#define ID_THOLD_TX_SD_SZ 1
+#define ID_DOUBLE_RLS_SD_MSK 0x00200000
+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SD_SFT 21
+#define ID_DOUBLE_RLS_SD_HI 21
+#define ID_DOUBLE_RLS_SD_SZ 1
+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SD_SFT 22
+#define RX_ID_LEN_THOLD_SD_HI 22
+#define RX_ID_LEN_THOLD_SD_SZ 1
+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SD_SFT 23
+#define TX_ID_LEN_THOLD_SD_HI 23
+#define TX_ID_LEN_THOLD_SD_SZ 1
+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SD_SFT 24
+#define ALL_ID_LEN_THOLD_SD_HI 24
+#define ALL_ID_LEN_THOLD_SD_SZ 1
+#define DMN_MCU_INT_SD_MSK 0x02000000
+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SD_SFT 25
+#define DMN_MCU_INT_SD_HI 25
+#define DMN_MCU_INT_SD_SZ 1
+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SD_SFT 26
+#define IRQ_DAT_UART_TX_SD_HI 26
+#define IRQ_DAT_UART_TX_SD_SZ 1
+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SD_SFT 27
+#define IRQ_DAT_UART_RX_SD_HI 27
+#define IRQ_DAT_UART_RX_SD_SZ 1
+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SD_SFT 28
+#define DAT_UART_RX_TIMEOUT_SD_HI 28
+#define DAT_UART_RX_TIMEOUT_SD_SZ 1
+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SD_SFT 29
+#define DAT_UART_MULTI_IRQ_SD_HI 29
+#define DAT_UART_MULTI_IRQ_SD_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
+#define DBG_SPI_MODE_MSK 0xffffffff
+#define DBG_SPI_MODE_I_MSK 0x00000000
+#define DBG_SPI_MODE_SFT 0
+#define DBG_SPI_MODE_HI 31
+#define DBG_SPI_MODE_SZ 32
+#define DBG_RX_QUOTA_MSK 0x0000ffff
+#define DBG_RX_QUOTA_I_MSK 0xffff0000
+#define DBG_RX_QUOTA_SFT 0
+#define DBG_RX_QUOTA_HI 15
+#define DBG_RX_QUOTA_SZ 16
+#define DBG_CONDI_NUM_MSK 0x000000ff
+#define DBG_CONDI_NUM_I_MSK 0xffffff00
+#define DBG_CONDI_NUM_SFT 0
+#define DBG_CONDI_NUM_HI 7
+#define DBG_CONDI_NUM_SZ 8
+#define DBG_HOST_PATH_MSK 0x00000001
+#define DBG_HOST_PATH_I_MSK 0xfffffffe
+#define DBG_HOST_PATH_SFT 0
+#define DBG_HOST_PATH_HI 0
+#define DBG_HOST_PATH_SZ 1
+#define DBG_TX_SEG_MSK 0xffffffff
+#define DBG_TX_SEG_I_MSK 0x00000000
+#define DBG_TX_SEG_SFT 0
+#define DBG_TX_SEG_HI 31
+#define DBG_TX_SEG_SZ 32
+#define DBG_BRST_MODE_MSK 0x00000001
+#define DBG_BRST_MODE_I_MSK 0xfffffffe
+#define DBG_BRST_MODE_SFT 0
+#define DBG_BRST_MODE_HI 0
+#define DBG_BRST_MODE_SZ 1
+#define DBG_CLK_WIDTH_MSK 0x0000ffff
+#define DBG_CLK_WIDTH_I_MSK 0xffff0000
+#define DBG_CLK_WIDTH_SFT 0
+#define DBG_CLK_WIDTH_HI 15
+#define DBG_CLK_WIDTH_SZ 16
+#define DBG_CSN_INTER_MSK 0xffff0000
+#define DBG_CSN_INTER_I_MSK 0x0000ffff
+#define DBG_CSN_INTER_SFT 16
+#define DBG_CSN_INTER_HI 31
+#define DBG_CSN_INTER_SZ 16
+#define DBG_BACK_DLY_MSK 0x0000ffff
+#define DBG_BACK_DLY_I_MSK 0xffff0000
+#define DBG_BACK_DLY_SFT 0
+#define DBG_BACK_DLY_HI 15
+#define DBG_BACK_DLY_SZ 16
+#define DBG_FRONT_DLY_MSK 0xffff0000
+#define DBG_FRONT_DLY_I_MSK 0x0000ffff
+#define DBG_FRONT_DLY_SFT 16
+#define DBG_FRONT_DLY_HI 31
+#define DBG_FRONT_DLY_SZ 16
+#define DBG_RX_FIFO_FAIL_MSK 0x00000002
+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define DBG_RX_FIFO_FAIL_SFT 1
+#define DBG_RX_FIFO_FAIL_HI 1
+#define DBG_RX_FIFO_FAIL_SZ 1
+#define DBG_RX_HOST_FAIL_MSK 0x00000004
+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
+#define DBG_RX_HOST_FAIL_SFT 2
+#define DBG_RX_HOST_FAIL_HI 2
+#define DBG_RX_HOST_FAIL_SZ 1
+#define DBG_TX_FIFO_FAIL_MSK 0x00000008
+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define DBG_TX_FIFO_FAIL_SFT 3
+#define DBG_TX_FIFO_FAIL_HI 3
+#define DBG_TX_FIFO_FAIL_SZ 1
+#define DBG_TX_HOST_FAIL_MSK 0x00000010
+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
+#define DBG_TX_HOST_FAIL_SFT 4
+#define DBG_TX_HOST_FAIL_HI 4
+#define DBG_TX_HOST_FAIL_SZ 1
+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define DBG_SPI_DOUBLE_ALLOC_SFT 5
+#define DBG_SPI_DOUBLE_ALLOC_HI 5
+#define DBG_SPI_DOUBLE_ALLOC_SZ 1
+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define DBG_SPI_TX_NO_ALLOC_SFT 6
+#define DBG_SPI_TX_NO_ALLOC_HI 6
+#define DBG_SPI_TX_NO_ALLOC_SZ 1
+#define DBG_RDATA_RDY_MSK 0x00000080
+#define DBG_RDATA_RDY_I_MSK 0xffffff7f
+#define DBG_RDATA_RDY_SFT 7
+#define DBG_RDATA_RDY_HI 7
+#define DBG_RDATA_RDY_SZ 1
+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define DBG_SPI_ALLOC_STATUS_SFT 8
+#define DBG_SPI_ALLOC_STATUS_HI 8
+#define DBG_SPI_ALLOC_STATUS_SZ 1
+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
+#define DBG_RX_LEN_MSK 0xffff0000
+#define DBG_RX_LEN_I_MSK 0x0000ffff
+#define DBG_RX_LEN_SFT 16
+#define DBG_RX_LEN_HI 31
+#define DBG_RX_LEN_SZ 16
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_HI 7
+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
+#define DBG_RD_DAT_CNT_MSK 0x0000ffff
+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
+#define DBG_RD_DAT_CNT_SFT 0
+#define DBG_RD_DAT_CNT_HI 15
+#define DBG_RD_DAT_CNT_SZ 16
+#define DBG_RD_STS_CNT_MSK 0xffff0000
+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
+#define DBG_RD_STS_CNT_SFT 16
+#define DBG_RD_STS_CNT_HI 31
+#define DBG_RD_STS_CNT_SZ 16
+#define DBG_JUDGE_CNT_MSK 0x0000ffff
+#define DBG_JUDGE_CNT_I_MSK 0xffff0000
+#define DBG_JUDGE_CNT_SFT 0
+#define DBG_JUDGE_CNT_HI 15
+#define DBG_JUDGE_CNT_SZ 16
+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_RD_STS_CNT_CLR_SFT 16
+#define DBG_RD_STS_CNT_CLR_HI 16
+#define DBG_RD_STS_CNT_CLR_SZ 1
+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_RD_DAT_CNT_CLR_SFT 17
+#define DBG_RD_DAT_CNT_CLR_HI 17
+#define DBG_RD_DAT_CNT_CLR_SZ 1
+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_JUDGE_CNT_CLR_SFT 18
+#define DBG_JUDGE_CNT_CLR_HI 18
+#define DBG_JUDGE_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_MSK 0x0000ffff
+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
+#define DBG_TX_DONE_CNT_SFT 0
+#define DBG_TX_DONE_CNT_HI 15
+#define DBG_TX_DONE_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define DBG_TX_DISCARD_CNT_SFT 16
+#define DBG_TX_DISCARD_CNT_HI 31
+#define DBG_TX_DISCARD_CNT_SZ 16
+#define DBG_TX_SET_CNT_MSK 0x0000ffff
+#define DBG_TX_SET_CNT_I_MSK 0xffff0000
+#define DBG_TX_SET_CNT_SFT 0
+#define DBG_TX_SET_CNT_HI 15
+#define DBG_TX_SET_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_TX_DISCARD_CNT_CLR_SFT 16
+#define DBG_TX_DISCARD_CNT_CLR_HI 16
+#define DBG_TX_DISCARD_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_TX_DONE_CNT_CLR_SFT 17
+#define DBG_TX_DONE_CNT_CLR_HI 17
+#define DBG_TX_DONE_CNT_CLR_SZ 1
+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_TX_SET_CNT_CLR_SFT 18
+#define DBG_TX_SET_CNT_CLR_HI 18
+#define DBG_TX_SET_CNT_CLR_SZ 1
+#define DBG_DAT_MODE_OFF_MSK 0x00080000
+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DBG_DAT_MODE_OFF_SFT 19
+#define DBG_DAT_MODE_OFF_HI 19
+#define DBG_DAT_MODE_OFF_SZ 1
+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define DBG_TX_FIFO_RESIDUE_SFT 20
+#define DBG_TX_FIFO_RESIDUE_HI 22
+#define DBG_TX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define DBG_RX_FIFO_RESIDUE_SFT 24
+#define DBG_RX_FIFO_RESIDUE_HI 26
+#define DBG_RX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_RDY_MSK 0x00000001
+#define DBG_RX_RDY_I_MSK 0xfffffffe
+#define DBG_RX_RDY_SFT 0
+#define DBG_RX_RDY_HI 0
+#define DBG_RX_RDY_SZ 1
+#define DBG_SDIO_SYS_INT_MSK 0x00000004
+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
+#define DBG_SDIO_SYS_INT_SFT 2
+#define DBG_SDIO_SYS_INT_HI 2
+#define DBG_SDIO_SYS_INT_SZ 1
+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
+#define DBG_EDCA0_LOWTHOLD_INT_HI 3
+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
+#define DBG_EDCA1_LOWTHOLD_INT_HI 4
+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
+#define DBG_EDCA2_LOWTHOLD_INT_HI 5
+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
+#define DBG_EDCA3_LOWTHOLD_INT_HI 6
+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define DBG_TX_LIMIT_INT_IN_SFT 7
+#define DBG_TX_LIMIT_INT_IN_HI 7
+#define DBG_TX_LIMIT_INT_IN_SZ 1
+#define DBG_SPI_FN1_MSK 0x00007f00
+#define DBG_SPI_FN1_I_MSK 0xffff80ff
+#define DBG_SPI_FN1_SFT 8
+#define DBG_SPI_FN1_HI 14
+#define DBG_SPI_FN1_SZ 7
+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define DBG_SPI_CLK_EN_INT_SFT 15
+#define DBG_SPI_CLK_EN_INT_HI 15
+#define DBG_SPI_CLK_EN_INT_SZ 1
+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
+#define DBG_SPI_HOST_MASK_SFT 16
+#define DBG_SPI_HOST_MASK_HI 23
+#define DBG_SPI_HOST_MASK_SZ 8
+#define BOOT_ADDR_MSK 0x00ffffff
+#define BOOT_ADDR_I_MSK 0xff000000
+#define BOOT_ADDR_SFT 0
+#define BOOT_ADDR_HI 23
+#define BOOT_ADDR_SZ 24
+#define CHECK_SUM_FAIL_MSK 0x80000000
+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
+#define CHECK_SUM_FAIL_SFT 31
+#define CHECK_SUM_FAIL_HI 31
+#define CHECK_SUM_FAIL_SZ 1
+#define VERIFY_DATA_MSK 0xffffffff
+#define VERIFY_DATA_I_MSK 0x00000000
+#define VERIFY_DATA_SFT 0
+#define VERIFY_DATA_HI 31
+#define VERIFY_DATA_SZ 32
+#define FLASH_ADDR_MSK 0x00ffffff
+#define FLASH_ADDR_I_MSK 0xff000000
+#define FLASH_ADDR_SFT 0
+#define FLASH_ADDR_HI 23
+#define FLASH_ADDR_SZ 24
+#define FLASH_CMD_CLR_MSK 0x10000000
+#define FLASH_CMD_CLR_I_MSK 0xefffffff
+#define FLASH_CMD_CLR_SFT 28
+#define FLASH_CMD_CLR_HI 28
+#define FLASH_CMD_CLR_SZ 1
+#define FLASH_DMA_CLR_MSK 0x20000000
+#define FLASH_DMA_CLR_I_MSK 0xdfffffff
+#define FLASH_DMA_CLR_SFT 29
+#define FLASH_DMA_CLR_HI 29
+#define FLASH_DMA_CLR_SZ 1
+#define DMA_EN_MSK 0x40000000
+#define DMA_EN_I_MSK 0xbfffffff
+#define DMA_EN_SFT 30
+#define DMA_EN_HI 30
+#define DMA_EN_SZ 1
+#define DMA_BUSY_MSK 0x80000000
+#define DMA_BUSY_I_MSK 0x7fffffff
+#define DMA_BUSY_SFT 31
+#define DMA_BUSY_HI 31
+#define DMA_BUSY_SZ 1
+#define SRAM_ADDR_MSK 0xffffffff
+#define SRAM_ADDR_I_MSK 0x00000000
+#define SRAM_ADDR_SFT 0
+#define SRAM_ADDR_HI 31
+#define SRAM_ADDR_SZ 32
+#define FLASH_DMA_LEN_MSK 0xffffffff
+#define FLASH_DMA_LEN_I_MSK 0x00000000
+#define FLASH_DMA_LEN_SFT 0
+#define FLASH_DMA_LEN_HI 31
+#define FLASH_DMA_LEN_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000ffff
+#define FLASH_FRONT_DLY_I_MSK 0xffff0000
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 15
+#define FLASH_FRONT_DLY_SZ 16
+#define FLASH_BACK_DLY_MSK 0xffff0000
+#define FLASH_BACK_DLY_I_MSK 0x0000ffff
+#define FLASH_BACK_DLY_SFT 16
+#define FLASH_BACK_DLY_HI 31
+#define FLASH_BACK_DLY_SZ 16
+#define FLASH_CLK_WIDTH_MSK 0x0000ffff
+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
+#define FLASH_CLK_WIDTH_SFT 0
+#define FLASH_CLK_WIDTH_HI 15
+#define FLASH_CLK_WIDTH_SZ 16
+#define SPI_BUSY_MSK 0x00010000
+#define SPI_BUSY_I_MSK 0xfffeffff
+#define SPI_BUSY_SFT 16
+#define SPI_BUSY_HI 16
+#define SPI_BUSY_SZ 1
+#define FLS_REMAP_MSK 0x00020000
+#define FLS_REMAP_I_MSK 0xfffdffff
+#define FLS_REMAP_SFT 17
+#define FLS_REMAP_HI 17
+#define FLS_REMAP_SZ 1
+#define PBUS_SWP_MSK 0x00040000
+#define PBUS_SWP_I_MSK 0xfffbffff
+#define PBUS_SWP_SFT 18
+#define PBUS_SWP_HI 18
+#define PBUS_SWP_SZ 1
+#define BIT_MODE1_MSK 0x00080000
+#define BIT_MODE1_I_MSK 0xfff7ffff
+#define BIT_MODE1_SFT 19
+#define BIT_MODE1_HI 19
+#define BIT_MODE1_SZ 1
+#define BIT_MODE2_MSK 0x00100000
+#define BIT_MODE2_I_MSK 0xffefffff
+#define BIT_MODE2_SFT 20
+#define BIT_MODE2_HI 20
+#define BIT_MODE2_SZ 1
+#define BIT_MODE4_MSK 0x00200000
+#define BIT_MODE4_I_MSK 0xffdfffff
+#define BIT_MODE4_SFT 21
+#define BIT_MODE4_HI 21
+#define BIT_MODE4_SZ 1
+#define BOOT_CHECK_SUM_MSK 0xffffffff
+#define BOOT_CHECK_SUM_I_MSK 0x00000000
+#define BOOT_CHECK_SUM_SFT 0
+#define BOOT_CHECK_SUM_HI 31
+#define BOOT_CHECK_SUM_SZ 32
+#define CHECK_SUM_TAG_MSK 0xffffffff
+#define CHECK_SUM_TAG_I_MSK 0x00000000
+#define CHECK_SUM_TAG_SFT 0
+#define CHECK_SUM_TAG_HI 31
+#define CHECK_SUM_TAG_SZ 32
+#define CMD_LEN_MSK 0x0000ffff
+#define CMD_LEN_I_MSK 0xffff0000
+#define CMD_LEN_SFT 0
+#define CMD_LEN_HI 15
+#define CMD_LEN_SZ 16
+#define CMD_ADDR_MSK 0xffffffff
+#define CMD_ADDR_I_MSK 0x00000000
+#define CMD_ADDR_SFT 0
+#define CMD_ADDR_HI 31
+#define CMD_ADDR_SZ 32
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define SLEEP_WAKE_CNT_SFT 0
+#define SLEEP_WAKE_CNT_HI 23
+#define SLEEP_WAKE_CNT_SZ 24
+#define RG_DLDO_LEVEL_MSK 0x07000000
+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
+#define RG_DLDO_LEVEL_SFT 24
+#define RG_DLDO_LEVEL_HI 26
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_DLDO_BOOST_IQ_MSK 0x08000000
+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
+#define RG_DLDO_BOOST_IQ_SFT 27
+#define RG_DLDO_BOOST_IQ_HI 27
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_LEVEL_MSK 0x70000000
+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
+#define RG_BUCK_LEVEL_SFT 28
+#define RG_BUCK_LEVEL_HI 30
+#define RG_BUCK_LEVEL_SZ 3
+#define RG_BUCK_VREF_SEL_MSK 0x80000000
+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
+#define RG_BUCK_VREF_SEL_SFT 31
+#define RG_BUCK_VREF_SEL_HI 31
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RG_RTC_OSC_RES_SW_SFT 16
+#define RG_RTC_OSC_RES_SW_HI 25
+#define RG_RTC_OSC_RES_SW_SZ 10
+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RTC_OSC_CAL_RES_RDY_SFT 31
+#define RTC_OSC_CAL_RES_RDY_HI 31
+#define RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000010
+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
+#define RG_BUCK_EN_PSM_SFT 4
+#define RG_BUCK_EN_PSM_HI 4
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000100
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
+#define RG_BUCK_PSM_VTH_SFT 8
+#define RG_BUCK_PSM_VTH_HI 8
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
+#define RTC_CAL_ENA_MSK 0x00010000
+#define RTC_CAL_ENA_I_MSK 0xfffeffff
+#define RTC_CAL_ENA_SFT 16
+#define RTC_CAL_ENA_HI 16
+#define RTC_CAL_ENA_SZ 1
+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
+#define PMU_WAKE_TRIG_EVENT_SFT 0
+#define PMU_WAKE_TRIG_EVENT_HI 1
+#define PMU_WAKE_TRIG_EVENT_SZ 2
+#define DIGI_TOP_POR_MASK_MSK 0x00000010
+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
+#define DIGI_TOP_POR_MASK_SFT 4
+#define DIGI_TOP_POR_MASK_HI 4
+#define DIGI_TOP_POR_MASK_SZ 1
+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
+#define PMU_ENTER_SLEEP_MODE_SFT 8
+#define PMU_ENTER_SLEEP_MODE_HI 8
+#define PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_RTC_DUMMIES_MSK 0xffff0000
+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
+#define RG_RTC_DUMMIES_SFT 16
+#define RG_RTC_DUMMIES_HI 31
+#define RG_RTC_DUMMIES_SZ 16
+#define RTC_EN_MSK 0x00000001
+#define RTC_EN_I_MSK 0xfffffffe
+#define RTC_EN_SFT 0
+#define RTC_EN_HI 0
+#define RTC_EN_SZ 1
+#define RTC_SRC_MSK 0x00000002
+#define RTC_SRC_I_MSK 0xfffffffd
+#define RTC_SRC_SFT 1
+#define RTC_SRC_HI 1
+#define RTC_SRC_SZ 1
+#define RTC_TICK_CNT_MSK 0x7fff0000
+#define RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RTC_TICK_CNT_SFT 16
+#define RTC_TICK_CNT_HI 30
+#define RTC_TICK_CNT_SZ 15
+#define RTC_INT_SEC_MASK_MSK 0x00000001
+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RTC_INT_SEC_MASK_SFT 0
+#define RTC_INT_SEC_MASK_HI 0
+#define RTC_INT_SEC_MASK_SZ 1
+#define RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RTC_INT_ALARM_MASK_SFT 1
+#define RTC_INT_ALARM_MASK_HI 1
+#define RTC_INT_ALARM_MASK_SZ 1
+#define RTC_INT_SEC_MSK 0x00010000
+#define RTC_INT_SEC_I_MSK 0xfffeffff
+#define RTC_INT_SEC_SFT 16
+#define RTC_INT_SEC_HI 16
+#define RTC_INT_SEC_SZ 1
+#define RTC_INT_ALARM_MSK 0x00020000
+#define RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RTC_INT_ALARM_SFT 17
+#define RTC_INT_ALARM_HI 17
+#define RTC_INT_ALARM_SZ 1
+#define RTC_SEC_START_CNT_MSK 0xffffffff
+#define RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RTC_SEC_START_CNT_SFT 0
+#define RTC_SEC_START_CNT_HI 31
+#define RTC_SEC_START_CNT_SZ 32
+#define RTC_SEC_CNT_MSK 0xffffffff
+#define RTC_SEC_CNT_I_MSK 0x00000000
+#define RTC_SEC_CNT_SFT 0
+#define RTC_SEC_CNT_HI 31
+#define RTC_SEC_CNT_SZ 32
+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RTC_SEC_ALARM_VALUE_SFT 0
+#define RTC_SEC_ALARM_VALUE_HI 31
+#define RTC_SEC_ALARM_VALUE_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
+#define TRAP_UNKNOWN_TYPE_SFT 0
+#define TRAP_UNKNOWN_TYPE_HI 0
+#define TRAP_UNKNOWN_TYPE_SZ 1
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASSS_TX_PARSER_ENCAP_SFT 4
+#define BYPASSS_TX_PARSER_ENCAP_HI 4
+#define BYPASSS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
+#define RX_GET_TX_QUEUE_EN_SFT 25
+#define RX_GET_TX_QUEUE_EN_HI 25
+#define RX_GET_TX_QUEUE_EN_SZ 1
+#define HCI_INQ_SEL_MSK 0x04000000
+#define HCI_INQ_SEL_I_MSK 0xfbffffff
+#define HCI_INQ_SEL_SFT 26
+#define HCI_INQ_SEL_HI 26
+#define HCI_INQ_SEL_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0x000000ff
+#define HOST_CMD_COUNTER_I_MSK 0xffffff00
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 7
+#define HOST_CMD_COUNTER_SZ 8
+#define HOST_EVENT_COUNTER_MSK 0x000000ff
+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 7
+#define HOST_EVENT_COUNTER_SZ 8
+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 7
+#define TX_PKT_DROP_COUNTER_SZ 8
+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 7
+#define RX_PKT_DROP_COUNTER_SZ 8
+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 7
+#define TX_PKT_TRAP_COUNTER_SZ 8
+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 7
+#define RX_PKT_TRAP_COUNTER_SZ 8
+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 7
+#define HOST_TX_FAIL_COUNTER_SZ 8
+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 7
+#define HOST_RX_FAIL_COUNTER_SZ 8
+#define HCI_STATE_MONITOR_MSK 0xffffffff
+#define HCI_STATE_MONITOR_I_MSK 0x00000000
+#define HCI_STATE_MONITOR_SFT 0
+#define HCI_STATE_MONITOR_HI 31
+#define HCI_STATE_MONITOR_SZ 32
+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
+#define HCI_ST_TIMEOUT_MONITOR_SFT 0
+#define HCI_ST_TIMEOUT_MONITOR_HI 31
+#define HCI_ST_TIMEOUT_MONITOR_SZ 32
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_MONITOR_REG1_MSK 0xffffffff
+#define HCI_MONITOR_REG1_I_MSK 0x00000000
+#define HCI_MONITOR_REG1_SFT 0
+#define HCI_MONITOR_REG1_HI 31
+#define HCI_MONITOR_REG1_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_31_0_SFT 0
+#define HCI_TX_ALLOC_TIME_31_0_HI 31
+#define HCI_TX_ALLOC_TIME_31_0_SZ 32
+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_TIME_47_32_SFT 0
+#define HCI_TX_ALLOC_TIME_47_32_HI 15
+#define HCI_TX_ALLOC_TIME_47_32_SZ 16
+#define HCI_MB_MAX_CNT_MSK 0x00ff0000
+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
+#define HCI_MB_MAX_CNT_SFT 16
+#define HCI_MB_MAX_CNT_HI 23
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_31_0_SFT 0
+#define HCI_TX_ALLOC_CNT_31_0_HI 31
+#define HCI_TX_ALLOC_CNT_31_0_SZ 32
+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_CNT_47_32_SFT 0
+#define HCI_TX_ALLOC_CNT_47_32_HI 15
+#define HCI_TX_ALLOC_CNT_47_32_SZ 16
+#define HCI_PROC_CNT_MSK 0x00ff0000
+#define HCI_PROC_CNT_I_MSK 0xff00ffff
+#define HCI_PROC_CNT_SFT 16
+#define HCI_PROC_CNT_HI 23
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0xff000000
+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
+#define SDIO_TRANS_CNT_SFT 24
+#define SDIO_TRANS_CNT_HI 31
+#define SDIO_TRANS_CNT_SZ 8
+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_31_0_SFT 0
+#define SDIO_TX_INVALID_CNT_31_0_HI 31
+#define SDIO_TX_INVALID_CNT_31_0_SZ 32
+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
+#define SDIO_TX_INVALID_CNT_47_32_SFT 0
+#define SDIO_TX_INVALID_CNT_47_32_HI 15
+#define SDIO_TX_INVALID_CNT_47_32_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define LOW_ACTIVE_MSK 0x00010000
+#define LOW_ACTIVE_I_MSK 0xfffeffff
+#define LOW_ACTIVE_SFT 16
+#define LOW_ACTIVE_HI 16
+#define LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RDATA_0_MSK 0xffffffff
+#define EFS_RDATA_0_I_MSK 0x00000000
+#define EFS_RDATA_0_SFT 0
+#define EFS_RDATA_0_HI 31
+#define EFS_RDATA_0_SZ 32
+#define EFS_WDATA_0_MSK 0xffffffff
+#define EFS_WDATA_0_I_MSK 0x00000000
+#define EFS_WDATA_0_SFT 0
+#define EFS_WDATA_0_HI 31
+#define EFS_WDATA_0_SZ 32
+#define EFS_RDATA_1_MSK 0xffffffff
+#define EFS_RDATA_1_I_MSK 0x00000000
+#define EFS_RDATA_1_SFT 0
+#define EFS_RDATA_1_HI 31
+#define EFS_RDATA_1_SZ 32
+#define EFS_WDATA_1_MSK 0xffffffff
+#define EFS_WDATA_1_I_MSK 0x00000000
+#define EFS_WDATA_1_SFT 0
+#define EFS_WDATA_1_HI 31
+#define EFS_WDATA_1_SZ 32
+#define EFS_RDATA_2_MSK 0xffffffff
+#define EFS_RDATA_2_I_MSK 0x00000000
+#define EFS_RDATA_2_SFT 0
+#define EFS_RDATA_2_HI 31
+#define EFS_RDATA_2_SZ 32
+#define EFS_WDATA_2_MSK 0xffffffff
+#define EFS_WDATA_2_I_MSK 0x00000000
+#define EFS_WDATA_2_SFT 0
+#define EFS_WDATA_2_HI 31
+#define EFS_WDATA_2_SZ 32
+#define EFS_RDATA_3_MSK 0xffffffff
+#define EFS_RDATA_3_I_MSK 0x00000000
+#define EFS_RDATA_3_SFT 0
+#define EFS_RDATA_3_HI 31
+#define EFS_RDATA_3_SZ 32
+#define EFS_WDATA_3_MSK 0xffffffff
+#define EFS_WDATA_3_I_MSK 0x00000000
+#define EFS_WDATA_3_SFT 0
+#define EFS_WDATA_3_HI 31
+#define EFS_WDATA_3_SZ 32
+#define EFS_RDATA_4_MSK 0xffffffff
+#define EFS_RDATA_4_I_MSK 0x00000000
+#define EFS_RDATA_4_SFT 0
+#define EFS_RDATA_4_HI 31
+#define EFS_RDATA_4_SZ 32
+#define EFS_WDATA_4_MSK 0xffffffff
+#define EFS_WDATA_4_I_MSK 0x00000000
+#define EFS_WDATA_4_SFT 0
+#define EFS_WDATA_4_HI 31
+#define EFS_WDATA_4_SZ 32
+#define EFS_RDATA_5_MSK 0xffffffff
+#define EFS_RDATA_5_I_MSK 0x00000000
+#define EFS_RDATA_5_SFT 0
+#define EFS_RDATA_5_HI 31
+#define EFS_RDATA_5_SZ 32
+#define EFS_WDATA_5_MSK 0xffffffff
+#define EFS_WDATA_5_I_MSK 0x00000000
+#define EFS_WDATA_5_SFT 0
+#define EFS_WDATA_5_HI 31
+#define EFS_WDATA_5_SZ 32
+#define EFS_RDATA_6_MSK 0xffffffff
+#define EFS_RDATA_6_I_MSK 0x00000000
+#define EFS_RDATA_6_SFT 0
+#define EFS_RDATA_6_HI 31
+#define EFS_RDATA_6_SZ 32
+#define EFS_WDATA_6_MSK 0xffffffff
+#define EFS_WDATA_6_I_MSK 0x00000000
+#define EFS_WDATA_6_SFT 0
+#define EFS_WDATA_6_HI 31
+#define EFS_WDATA_6_SZ 32
+#define EFS_RDATA_7_MSK 0xffffffff
+#define EFS_RDATA_7_I_MSK 0x00000000
+#define EFS_RDATA_7_SFT 0
+#define EFS_RDATA_7_HI 31
+#define EFS_RDATA_7_SZ 32
+#define EFS_WDATA_7_MSK 0xffffffff
+#define EFS_WDATA_7_I_MSK 0x00000000
+#define EFS_WDATA_7_SFT 0
+#define EFS_WDATA_7_HI 31
+#define EFS_WDATA_7_SZ 32
+#define EFS_SPI_RD0_EN_MSK 0x00000001
+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD0_EN_SFT 0
+#define EFS_SPI_RD0_EN_HI 0
+#define EFS_SPI_RD0_EN_SZ 1
+#define EFS_SPI_RD1_EN_MSK 0x00000001
+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD1_EN_SFT 0
+#define EFS_SPI_RD1_EN_HI 0
+#define EFS_SPI_RD1_EN_SZ 1
+#define EFS_SPI_RD2_EN_MSK 0x00000001
+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD2_EN_SFT 0
+#define EFS_SPI_RD2_EN_HI 0
+#define EFS_SPI_RD2_EN_SZ 1
+#define EFS_SPI_RD3_EN_MSK 0x00000001
+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD3_EN_SFT 0
+#define EFS_SPI_RD3_EN_HI 0
+#define EFS_SPI_RD3_EN_SZ 1
+#define EFS_SPI_RD4_EN_MSK 0x00000001
+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD4_EN_SFT 0
+#define EFS_SPI_RD4_EN_HI 0
+#define EFS_SPI_RD4_EN_SZ 1
+#define EFS_SPI_RD5_EN_MSK 0x00000001
+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD5_EN_SFT 0
+#define EFS_SPI_RD5_EN_HI 0
+#define EFS_SPI_RD5_EN_SZ 1
+#define EFS_SPI_RD6_EN_MSK 0x00000001
+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD6_EN_SFT 0
+#define EFS_SPI_RD6_EN_HI 0
+#define EFS_SPI_RD6_EN_SZ 1
+#define EFS_SPI_RD7_EN_MSK 0x00000001
+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD7_EN_SFT 0
+#define EFS_SPI_RD7_EN_HI 0
+#define EFS_SPI_RD7_EN_SZ 1
+#define EFS_SPI_RBUSY_MSK 0x00000001
+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
+#define EFS_SPI_RBUSY_SFT 0
+#define EFS_SPI_RBUSY_HI 0
+#define EFS_SPI_RBUSY_SZ 1
+#define EFS_SPI_RDATA_0_MSK 0xffffffff
+#define EFS_SPI_RDATA_0_I_MSK 0x00000000
+#define EFS_SPI_RDATA_0_SFT 0
+#define EFS_SPI_RDATA_0_HI 31
+#define EFS_SPI_RDATA_0_SZ 32
+#define EFS_SPI_RDATA_1_MSK 0xffffffff
+#define EFS_SPI_RDATA_1_I_MSK 0x00000000
+#define EFS_SPI_RDATA_1_SFT 0
+#define EFS_SPI_RDATA_1_HI 31
+#define EFS_SPI_RDATA_1_SZ 32
+#define EFS_SPI_RDATA_2_MSK 0xffffffff
+#define EFS_SPI_RDATA_2_I_MSK 0x00000000
+#define EFS_SPI_RDATA_2_SFT 0
+#define EFS_SPI_RDATA_2_HI 31
+#define EFS_SPI_RDATA_2_SZ 32
+#define EFS_SPI_RDATA_3_MSK 0xffffffff
+#define EFS_SPI_RDATA_3_I_MSK 0x00000000
+#define EFS_SPI_RDATA_3_SFT 0
+#define EFS_SPI_RDATA_3_HI 31
+#define EFS_SPI_RDATA_3_SZ 32
+#define EFS_SPI_RDATA_4_MSK 0xffffffff
+#define EFS_SPI_RDATA_4_I_MSK 0x00000000
+#define EFS_SPI_RDATA_4_SFT 0
+#define EFS_SPI_RDATA_4_HI 31
+#define EFS_SPI_RDATA_4_SZ 32
+#define EFS_SPI_RDATA_5_MSK 0xffffffff
+#define EFS_SPI_RDATA_5_I_MSK 0x00000000
+#define EFS_SPI_RDATA_5_SFT 0
+#define EFS_SPI_RDATA_5_HI 31
+#define EFS_SPI_RDATA_5_SZ 32
+#define EFS_SPI_RDATA_6_MSK 0xffffffff
+#define EFS_SPI_RDATA_6_I_MSK 0x00000000
+#define EFS_SPI_RDATA_6_SFT 0
+#define EFS_SPI_RDATA_6_HI 31
+#define EFS_SPI_RDATA_6_SZ 32
+#define EFS_SPI_RDATA_7_MSK 0xffffffff
+#define EFS_SPI_RDATA_7_I_MSK 0x00000000
+#define EFS_SPI_RDATA_7_SFT 0
+#define EFS_SPI_RDATA_7_HI 31
+#define EFS_SPI_RDATA_7_SZ 32
+#define GET_RK_MSK 0x00000001
+#define GET_RK_I_MSK 0xfffffffe
+#define GET_RK_SFT 0
+#define GET_RK_HI 0
+#define GET_RK_SZ 1
+#define FORCE_GET_RK_MSK 0x00000002
+#define FORCE_GET_RK_I_MSK 0xfffffffd
+#define FORCE_GET_RK_SFT 1
+#define FORCE_GET_RK_HI 1
+#define FORCE_GET_RK_SZ 1
+#define SMS4_DESCRY_EN_MSK 0x00000010
+#define SMS4_DESCRY_EN_I_MSK 0xffffffef
+#define SMS4_DESCRY_EN_SFT 4
+#define SMS4_DESCRY_EN_HI 4
+#define SMS4_DESCRY_EN_SZ 1
+#define DEC_DOUT_MSB_MSK 0x00000001
+#define DEC_DOUT_MSB_I_MSK 0xfffffffe
+#define DEC_DOUT_MSB_SFT 0
+#define DEC_DOUT_MSB_HI 0
+#define DEC_DOUT_MSB_SZ 1
+#define DEC_DIN_MSB_MSK 0x00000002
+#define DEC_DIN_MSB_I_MSK 0xfffffffd
+#define DEC_DIN_MSB_SFT 1
+#define DEC_DIN_MSB_HI 1
+#define DEC_DIN_MSB_SZ 1
+#define ENC_DOUT_MSB_MSK 0x00000004
+#define ENC_DOUT_MSB_I_MSK 0xfffffffb
+#define ENC_DOUT_MSB_SFT 2
+#define ENC_DOUT_MSB_HI 2
+#define ENC_DOUT_MSB_SZ 1
+#define ENC_DIN_MSB_MSK 0x00000008
+#define ENC_DIN_MSB_I_MSK 0xfffffff7
+#define ENC_DIN_MSB_SFT 3
+#define ENC_DIN_MSB_HI 3
+#define ENC_DIN_MSB_SZ 1
+#define KEY_DIN_MSB_MSK 0x00000010
+#define KEY_DIN_MSB_I_MSK 0xffffffef
+#define KEY_DIN_MSB_SFT 4
+#define KEY_DIN_MSB_HI 4
+#define KEY_DIN_MSB_SZ 1
+#define SMS4_CBC_EN_MSK 0x00000001
+#define SMS4_CBC_EN_I_MSK 0xfffffffe
+#define SMS4_CBC_EN_SFT 0
+#define SMS4_CBC_EN_HI 0
+#define SMS4_CBC_EN_SZ 1
+#define SMS4_CFB_EN_MSK 0x00000002
+#define SMS4_CFB_EN_I_MSK 0xfffffffd
+#define SMS4_CFB_EN_SFT 1
+#define SMS4_CFB_EN_HI 1
+#define SMS4_CFB_EN_SZ 1
+#define SMS4_OFB_EN_MSK 0x00000004
+#define SMS4_OFB_EN_I_MSK 0xfffffffb
+#define SMS4_OFB_EN_SFT 2
+#define SMS4_OFB_EN_HI 2
+#define SMS4_OFB_EN_SZ 1
+#define SMS4_START_TRIG_MSK 0x00000001
+#define SMS4_START_TRIG_I_MSK 0xfffffffe
+#define SMS4_START_TRIG_SFT 0
+#define SMS4_START_TRIG_HI 0
+#define SMS4_START_TRIG_SZ 1
+#define SMS4_BUSY_MSK 0x00000001
+#define SMS4_BUSY_I_MSK 0xfffffffe
+#define SMS4_BUSY_SFT 0
+#define SMS4_BUSY_HI 0
+#define SMS4_BUSY_SZ 1
+#define SMS4_DONE_MSK 0x00000001
+#define SMS4_DONE_I_MSK 0xfffffffe
+#define SMS4_DONE_SFT 0
+#define SMS4_DONE_HI 0
+#define SMS4_DONE_SZ 1
+#define SMS4_DATAIN_0_MSK 0xffffffff
+#define SMS4_DATAIN_0_I_MSK 0x00000000
+#define SMS4_DATAIN_0_SFT 0
+#define SMS4_DATAIN_0_HI 31
+#define SMS4_DATAIN_0_SZ 32
+#define SMS4_DATAIN_1_MSK 0xffffffff
+#define SMS4_DATAIN_1_I_MSK 0x00000000
+#define SMS4_DATAIN_1_SFT 0
+#define SMS4_DATAIN_1_HI 31
+#define SMS4_DATAIN_1_SZ 32
+#define SMS4_DATAIN_2_MSK 0xffffffff
+#define SMS4_DATAIN_2_I_MSK 0x00000000
+#define SMS4_DATAIN_2_SFT 0
+#define SMS4_DATAIN_2_HI 31
+#define SMS4_DATAIN_2_SZ 32
+#define SMS4_DATAIN_3_MSK 0xffffffff
+#define SMS4_DATAIN_3_I_MSK 0x00000000
+#define SMS4_DATAIN_3_SFT 0
+#define SMS4_DATAIN_3_HI 31
+#define SMS4_DATAIN_3_SZ 32
+#define SMS4_DATAOUT_0_MSK 0xffffffff
+#define SMS4_DATAOUT_0_I_MSK 0x00000000
+#define SMS4_DATAOUT_0_SFT 0
+#define SMS4_DATAOUT_0_HI 31
+#define SMS4_DATAOUT_0_SZ 32
+#define SMS4_DATAOUT_1_MSK 0xffffffff
+#define SMS4_DATAOUT_1_I_MSK 0x00000000
+#define SMS4_DATAOUT_1_SFT 0
+#define SMS4_DATAOUT_1_HI 31
+#define SMS4_DATAOUT_1_SZ 32
+#define SMS4_DATAOUT_2_MSK 0xffffffff
+#define SMS4_DATAOUT_2_I_MSK 0x00000000
+#define SMS4_DATAOUT_2_SFT 0
+#define SMS4_DATAOUT_2_HI 31
+#define SMS4_DATAOUT_2_SZ 32
+#define SMS4_DATAOUT_3_MSK 0xffffffff
+#define SMS4_DATAOUT_3_I_MSK 0x00000000
+#define SMS4_DATAOUT_3_SFT 0
+#define SMS4_DATAOUT_3_HI 31
+#define SMS4_DATAOUT_3_SZ 32
+#define SMS4_KEY_0_MSK 0xffffffff
+#define SMS4_KEY_0_I_MSK 0x00000000
+#define SMS4_KEY_0_SFT 0
+#define SMS4_KEY_0_HI 31
+#define SMS4_KEY_0_SZ 32
+#define SMS4_KEY_1_MSK 0xffffffff
+#define SMS4_KEY_1_I_MSK 0x00000000
+#define SMS4_KEY_1_SFT 0
+#define SMS4_KEY_1_HI 31
+#define SMS4_KEY_1_SZ 32
+#define SMS4_KEY_2_MSK 0xffffffff
+#define SMS4_KEY_2_I_MSK 0x00000000
+#define SMS4_KEY_2_SFT 0
+#define SMS4_KEY_2_HI 31
+#define SMS4_KEY_2_SZ 32
+#define SMS4_KEY_3_MSK 0xffffffff
+#define SMS4_KEY_3_I_MSK 0x00000000
+#define SMS4_KEY_3_SFT 0
+#define SMS4_KEY_3_HI 31
+#define SMS4_KEY_3_SZ 32
+#define SMS4_MODE_IV0_MSK 0xffffffff
+#define SMS4_MODE_IV0_I_MSK 0x00000000
+#define SMS4_MODE_IV0_SFT 0
+#define SMS4_MODE_IV0_HI 31
+#define SMS4_MODE_IV0_SZ 32
+#define SMS4_MODE_IV1_MSK 0xffffffff
+#define SMS4_MODE_IV1_I_MSK 0x00000000
+#define SMS4_MODE_IV1_SFT 0
+#define SMS4_MODE_IV1_HI 31
+#define SMS4_MODE_IV1_SZ 32
+#define SMS4_MODE_IV2_MSK 0xffffffff
+#define SMS4_MODE_IV2_I_MSK 0x00000000
+#define SMS4_MODE_IV2_SFT 0
+#define SMS4_MODE_IV2_HI 31
+#define SMS4_MODE_IV2_SZ 32
+#define SMS4_MODE_IV3_MSK 0xffffffff
+#define SMS4_MODE_IV3_I_MSK 0x00000000
+#define SMS4_MODE_IV3_SFT 0
+#define SMS4_MODE_IV3_HI 31
+#define SMS4_MODE_IV3_SZ 32
+#define SMS4_OFB_ENC0_MSK 0xffffffff
+#define SMS4_OFB_ENC0_I_MSK 0x00000000
+#define SMS4_OFB_ENC0_SFT 0
+#define SMS4_OFB_ENC0_HI 31
+#define SMS4_OFB_ENC0_SZ 32
+#define SMS4_OFB_ENC1_MSK 0xffffffff
+#define SMS4_OFB_ENC1_I_MSK 0x00000000
+#define SMS4_OFB_ENC1_SFT 0
+#define SMS4_OFB_ENC1_HI 31
+#define SMS4_OFB_ENC1_SZ 32
+#define SMS4_OFB_ENC2_MSK 0xffffffff
+#define SMS4_OFB_ENC2_I_MSK 0x00000000
+#define SMS4_OFB_ENC2_SFT 0
+#define SMS4_OFB_ENC2_HI 31
+#define SMS4_OFB_ENC2_SZ 32
+#define SMS4_OFB_ENC3_MSK 0xffffffff
+#define SMS4_OFB_ENC3_I_MSK 0x00000000
+#define SMS4_OFB_ENC3_SFT 0
+#define SMS4_OFB_ENC3_HI 31
+#define SMS4_OFB_ENC3_SZ 32
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x003f0000
+#define ACK_GEN_INFO_I_MSK 0xffc0ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 21
+#define ACK_GEN_INFO_SZ 6
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define W0_T0_SEQ_MSK 0x0000ffff
+#define W0_T0_SEQ_I_MSK 0xffff0000
+#define W0_T0_SEQ_SFT 0
+#define W0_T0_SEQ_HI 15
+#define W0_T0_SEQ_SZ 16
+#define W0_T1_SEQ_MSK 0x0000ffff
+#define W0_T1_SEQ_I_MSK 0xffff0000
+#define W0_T1_SEQ_SFT 0
+#define W0_T1_SEQ_HI 15
+#define W0_T1_SEQ_SZ 16
+#define W0_T2_SEQ_MSK 0x0000ffff
+#define W0_T2_SEQ_I_MSK 0xffff0000
+#define W0_T2_SEQ_SFT 0
+#define W0_T2_SEQ_HI 15
+#define W0_T2_SEQ_SZ 16
+#define W0_T3_SEQ_MSK 0x0000ffff
+#define W0_T3_SEQ_I_MSK 0xffff0000
+#define W0_T3_SEQ_SFT 0
+#define W0_T3_SEQ_HI 15
+#define W0_T3_SEQ_SZ 16
+#define W0_T4_SEQ_MSK 0x0000ffff
+#define W0_T4_SEQ_I_MSK 0xffff0000
+#define W0_T4_SEQ_SFT 0
+#define W0_T4_SEQ_HI 15
+#define W0_T4_SEQ_SZ 16
+#define W0_T5_SEQ_MSK 0x0000ffff
+#define W0_T5_SEQ_I_MSK 0xffff0000
+#define W0_T5_SEQ_SFT 0
+#define W0_T5_SEQ_HI 15
+#define W0_T5_SEQ_SZ 16
+#define W0_T6_SEQ_MSK 0x0000ffff
+#define W0_T6_SEQ_I_MSK 0xffff0000
+#define W0_T6_SEQ_SFT 0
+#define W0_T6_SEQ_HI 15
+#define W0_T6_SEQ_SZ 16
+#define W0_T7_SEQ_MSK 0x0000ffff
+#define W0_T7_SEQ_I_MSK 0xffff0000
+#define W0_T7_SEQ_SFT 0
+#define W0_T7_SEQ_HI 15
+#define W0_T7_SEQ_SZ 16
+#define W1_T0_SEQ_MSK 0x0000ffff
+#define W1_T0_SEQ_I_MSK 0xffff0000
+#define W1_T0_SEQ_SFT 0
+#define W1_T0_SEQ_HI 15
+#define W1_T0_SEQ_SZ 16
+#define W1_T1_SEQ_MSK 0x0000ffff
+#define W1_T1_SEQ_I_MSK 0xffff0000
+#define W1_T1_SEQ_SFT 0
+#define W1_T1_SEQ_HI 15
+#define W1_T1_SEQ_SZ 16
+#define W1_T2_SEQ_MSK 0x0000ffff
+#define W1_T2_SEQ_I_MSK 0xffff0000
+#define W1_T2_SEQ_SFT 0
+#define W1_T2_SEQ_HI 15
+#define W1_T2_SEQ_SZ 16
+#define W1_T3_SEQ_MSK 0x0000ffff
+#define W1_T3_SEQ_I_MSK 0xffff0000
+#define W1_T3_SEQ_SFT 0
+#define W1_T3_SEQ_HI 15
+#define W1_T3_SEQ_SZ 16
+#define W1_T4_SEQ_MSK 0x0000ffff
+#define W1_T4_SEQ_I_MSK 0xffff0000
+#define W1_T4_SEQ_SFT 0
+#define W1_T4_SEQ_HI 15
+#define W1_T4_SEQ_SZ 16
+#define W1_T5_SEQ_MSK 0x0000ffff
+#define W1_T5_SEQ_I_MSK 0xffff0000
+#define W1_T5_SEQ_SFT 0
+#define W1_T5_SEQ_HI 15
+#define W1_T5_SEQ_SZ 16
+#define W1_T6_SEQ_MSK 0x0000ffff
+#define W1_T6_SEQ_I_MSK 0xffff0000
+#define W1_T6_SEQ_SFT 0
+#define W1_T6_SEQ_HI 15
+#define W1_T6_SEQ_SZ 16
+#define W1_T7_SEQ_MSK 0x0000ffff
+#define W1_T7_SEQ_I_MSK 0xffff0000
+#define W1_T7_SEQ_SFT 0
+#define W1_T7_SEQ_HI 15
+#define W1_T7_SEQ_SZ 16
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC_AUTO_SFT 5
+#define MTX_AMPDU_CRC_AUTO_HI 5
+#define MTX_AMPDU_CRC_AUTO_SZ 1
+#define MTX_FAST_RSP_MODE_MSK 0x00000040
+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
+#define MTX_FAST_RSP_MODE_SFT 6
+#define MTX_FAST_RSP_MODE_HI 6
+#define MTX_FAST_RSP_MODE_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_ACK_DUR0_MSK 0x00000100
+#define MTX_ACK_DUR0_I_MSK 0xfffffeff
+#define MTX_ACK_DUR0_SFT 8
+#define MTX_ACK_DUR0_HI 8
+#define MTX_ACK_DUR0_SZ 1
+#define MTX_TSF_AUTO_BCN_MSK 0x00000400
+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
+#define MTX_TSF_AUTO_BCN_SFT 10
+#define MTX_TSF_AUTO_BCN_HI 10
+#define MTX_TSF_AUTO_BCN_SZ 1
+#define MTX_TSF_AUTO_MISC_MSK 0x00000800
+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
+#define MTX_TSF_AUTO_MISC_SFT 11
+#define MTX_TSF_AUTO_MISC_HI 11
+#define MTX_TSF_AUTO_MISC_SZ 1
+#define MTX_FORCE_CS_IDLE_MSK 0x00001000
+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
+#define MTX_FORCE_CS_IDLE_SFT 12
+#define MTX_FORCE_CS_IDLE_HI 12
+#define MTX_FORCE_CS_IDLE_SZ 1
+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
+#define MTX_FORCE_BKF_RXEN0_SFT 13
+#define MTX_FORCE_BKF_RXEN0_HI 13
+#define MTX_FORCE_BKF_RXEN0_SZ 1
+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
+#define MTX_FORCE_DMA_RXEN0_SFT 14
+#define MTX_FORCE_DMA_RXEN0_HI 14
+#define MTX_FORCE_DMA_RXEN0_SZ 1
+#define MTX_FORCE_RXEN0_MSK 0x00008000
+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
+#define MTX_FORCE_RXEN0_SFT 15
+#define MTX_FORCE_RXEN0_HI 15
+#define MTX_FORCE_RXEN0_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x003f0000
+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 21
+#define MTX_HALT_Q_MB_SZ 6
+#define MTX_CTS_SET_DIF_MSK 0x00400000
+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
+#define MTX_CTS_SET_DIF_SFT 22
+#define MTX_CTS_SET_DIF_HI 22
+#define MTX_CTS_SET_DIF_SZ 1
+#define MTX_AMPDU_SET_DIF_MSK 0x00800000
+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
+#define MTX_AMPDU_SET_DIF_SFT 23
+#define MTX_AMPDU_SET_DIF_HI 23
+#define MTX_AMPDU_SET_DIF_SZ 1
+#define MTX_EDCCA_TOUT_MSK 0x000003ff
+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
+#define MTX_EDCCA_TOUT_SFT 0
+#define MTX_EDCCA_TOUT_HI 9
+#define MTX_EDCCA_TOUT_SZ 10
+#define MTX_INT_BCN_MSK 0x00000002
+#define MTX_INT_BCN_I_MSK 0xfffffffd
+#define MTX_INT_BCN_SFT 1
+#define MTX_INT_BCN_HI 1
+#define MTX_INT_BCN_SZ 1
+#define MTX_INT_DTIM_MSK 0x00000008
+#define MTX_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_INT_DTIM_SFT 3
+#define MTX_INT_DTIM_HI 3
+#define MTX_INT_DTIM_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
+#define MTX_AUTO_FLUSH_Q4_SFT 16
+#define MTX_AUTO_FLUSH_Q4_HI 16
+#define MTX_AUTO_FLUSH_Q4_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_DTIM_NUM_MSK 0xff000000
+#define MTX_DTIM_NUM_I_MSK 0x00ffffff
+#define MTX_DTIM_NUM_SFT 24
+#define MTX_DTIM_NUM_HI 31
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x03ff0000
+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST0_SFT 16
+#define MTX_DTIM_OFST0_HI 25
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST1_MSK 0x03ff0000
+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST1_SFT 16
+#define MTX_DTIM_OFST1_HI 25
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_CCA_MSK 0x00000001
+#define MTX_CCA_I_MSK 0xfffffffe
+#define MTX_CCA_SFT 0
+#define MTX_CCA_HI 0
+#define MTX_CCA_SZ 1
+#define MRX_CCA_MSK 0x00000002
+#define MRX_CCA_I_MSK 0xfffffffd
+#define MRX_CCA_SFT 1
+#define MRX_CCA_HI 1
+#define MRX_CCA_SZ 1
+#define MTX_DMA_FSM_MSK 0x0000001c
+#define MTX_DMA_FSM_I_MSK 0xffffffe3
+#define MTX_DMA_FSM_SFT 2
+#define MTX_DMA_FSM_HI 4
+#define MTX_DMA_FSM_SZ 3
+#define CH_ST_FSM_MSK 0x000000e0
+#define CH_ST_FSM_I_MSK 0xffffff1f
+#define CH_ST_FSM_SFT 5
+#define CH_ST_FSM_HI 7
+#define CH_ST_FSM_SZ 3
+#define MTX_GNT_LOCK_MSK 0x00000100
+#define MTX_GNT_LOCK_I_MSK 0xfffffeff
+#define MTX_GNT_LOCK_SFT 8
+#define MTX_GNT_LOCK_HI 8
+#define MTX_GNT_LOCK_SZ 1
+#define MTX_DMA_REQ_MSK 0x00000200
+#define MTX_DMA_REQ_I_MSK 0xfffffdff
+#define MTX_DMA_REQ_SFT 9
+#define MTX_DMA_REQ_HI 9
+#define MTX_DMA_REQ_SZ 1
+#define MTX_Q_REQ_MSK 0x00000400
+#define MTX_Q_REQ_I_MSK 0xfffffbff
+#define MTX_Q_REQ_SFT 10
+#define MTX_Q_REQ_HI 10
+#define MTX_Q_REQ_SZ 1
+#define MTX_TX_EN_MSK 0x00000800
+#define MTX_TX_EN_I_MSK 0xfffff7ff
+#define MTX_TX_EN_SFT 11
+#define MTX_TX_EN_HI 11
+#define MTX_TX_EN_SZ 1
+#define MRX_RX_EN_MSK 0x00001000
+#define MRX_RX_EN_I_MSK 0xffffefff
+#define MRX_RX_EN_SFT 12
+#define MRX_RX_EN_HI 12
+#define MRX_RX_EN_SZ 1
+#define DBG_PRTC_PRD_MSK 0x00002000
+#define DBG_PRTC_PRD_I_MSK 0xffffdfff
+#define DBG_PRTC_PRD_SFT 13
+#define DBG_PRTC_PRD_HI 13
+#define DBG_PRTC_PRD_SZ 1
+#define DBG_DMA_RDY_MSK 0x00004000
+#define DBG_DMA_RDY_I_MSK 0xffffbfff
+#define DBG_DMA_RDY_SFT 14
+#define DBG_DMA_RDY_HI 14
+#define DBG_DMA_RDY_SZ 1
+#define DBG_WAIT_RSP_MSK 0x00008000
+#define DBG_WAIT_RSP_I_MSK 0xffff7fff
+#define DBG_WAIT_RSP_SFT 15
+#define DBG_WAIT_RSP_HI 15
+#define DBG_WAIT_RSP_SZ 1
+#define DBG_CFRM_BUSY_MSK 0x00010000
+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
+#define DBG_CFRM_BUSY_SFT 16
+#define DBG_CFRM_BUSY_HI 16
+#define DBG_CFRM_BUSY_SZ 1
+#define DBG_RST_MSK 0x00000001
+#define DBG_RST_I_MSK 0xfffffffe
+#define DBG_RST_SFT 0
+#define DBG_RST_HI 0
+#define DBG_RST_SZ 1
+#define DBG_MODE_MSK 0x00000002
+#define DBG_MODE_I_MSK 0xfffffffd
+#define DBG_MODE_SFT 1
+#define DBG_MODE_HI 1
+#define DBG_MODE_SZ 1
+#define MB_REQ_DUR_MSK 0x0000ffff
+#define MB_REQ_DUR_I_MSK 0xffff0000
+#define MB_REQ_DUR_SFT 0
+#define MB_REQ_DUR_HI 15
+#define MB_REQ_DUR_SZ 16
+#define RX_EN_DUR_MSK 0xffff0000
+#define RX_EN_DUR_I_MSK 0x0000ffff
+#define RX_EN_DUR_SFT 16
+#define RX_EN_DUR_HI 31
+#define RX_EN_DUR_SZ 16
+#define RX_CS_DUR_MSK 0x0000ffff
+#define RX_CS_DUR_I_MSK 0xffff0000
+#define RX_CS_DUR_SFT 0
+#define RX_CS_DUR_HI 15
+#define RX_CS_DUR_SZ 16
+#define TX_CCA_DUR_MSK 0xffff0000
+#define TX_CCA_DUR_I_MSK 0x0000ffff
+#define TX_CCA_DUR_SFT 16
+#define TX_CCA_DUR_HI 31
+#define TX_CCA_DUR_SZ 16
+#define Q_REQ_DUR_MSK 0x0000ffff
+#define Q_REQ_DUR_I_MSK 0xffff0000
+#define Q_REQ_DUR_SFT 0
+#define Q_REQ_DUR_HI 15
+#define Q_REQ_DUR_SZ 16
+#define CH_STA0_DUR_MSK 0xffff0000
+#define CH_STA0_DUR_I_MSK 0x0000ffff
+#define CH_STA0_DUR_SFT 16
+#define CH_STA0_DUR_HI 31
+#define CH_STA0_DUR_SZ 16
+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
+#define MTX_DUR_RSP_TOUT_B_SFT 0
+#define MTX_DUR_RSP_TOUT_B_HI 7
+#define MTX_DUR_RSP_TOUT_B_SZ 8
+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
+#define MTX_DUR_RSP_TOUT_G_SFT 8
+#define MTX_DUR_RSP_TOUT_G_HI 15
+#define MTX_DUR_RSP_TOUT_G_SZ 8
+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_SFT 0
+#define MTX_DUR_RSP_SIFS_HI 7
+#define MTX_DUR_RSP_SIFS_SZ 8
+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_SFT 8
+#define MTX_DUR_BURST_SIFS_HI 15
+#define MTX_DUR_BURST_SIFS_SZ 8
+#define MTX_DUR_SLOT_MSK 0x003f0000
+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_SFT 16
+#define MTX_DUR_SLOT_HI 21
+#define MTX_DUR_SLOT_SZ 6
+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_SFT 22
+#define MTX_DUR_RSP_EIFS_HI 31
+#define MTX_DUR_RSP_EIFS_SZ 10
+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_G_SFT 0
+#define MTX_DUR_RSP_SIFS_G_HI 7
+#define MTX_DUR_RSP_SIFS_G_SZ 8
+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_G_SFT 8
+#define MTX_DUR_BURST_SIFS_G_HI 15
+#define MTX_DUR_BURST_SIFS_G_SZ 8
+#define MTX_DUR_SLOT_G_MSK 0x003f0000
+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_G_SFT 16
+#define MTX_DUR_SLOT_G_HI 21
+#define MTX_DUR_SLOT_G_SZ 6
+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_G_SFT 22
+#define MTX_DUR_RSP_EIFS_G_HI 31
+#define MTX_DUR_RSP_EIFS_G_SZ 10
+#define CH_STA1_DUR_MSK 0x0000ffff
+#define CH_STA1_DUR_I_MSK 0xffff0000
+#define CH_STA1_DUR_SFT 0
+#define CH_STA1_DUR_HI 15
+#define CH_STA1_DUR_SZ 16
+#define CH_STA2_DUR_MSK 0xffff0000
+#define CH_STA2_DUR_I_MSK 0x0000ffff
+#define CH_STA2_DUR_SFT 16
+#define CH_STA2_DUR_HI 31
+#define CH_STA2_DUR_SZ 16
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define CH_STA3_DUR_MSK 0x0000ffff
+#define CH_STA3_DUR_I_MSK 0xffff0000
+#define CH_STA3_DUR_SFT 0
+#define CH_STA3_DUR_HI 15
+#define CH_STA3_DUR_SZ 16
+#define CH_STA4_DUR_MSK 0xffff0000
+#define CH_STA4_DUR_I_MSK 0x0000ffff
+#define CH_STA4_DUR_SFT 16
+#define CH_STA4_DUR_HI 31
+#define CH_STA4_DUR_SZ 16
+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ0_MTX_Q_PRE_LD_SFT 1
+#define TXQ0_MTX_Q_PRE_LD_HI 1
+#define TXQ0_MTX_Q_PRE_LD_SZ 1
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ0_MTX_Q_RND_MODE_SFT 6
+#define TXQ0_MTX_Q_RND_MODE_HI 7
+#define TXQ0_MTX_Q_RND_MODE_SZ 2
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_SZ 16
+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ0_MTX_Q_ID_MAP_L_HI 31
+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ1_MTX_Q_PRE_LD_SFT 1
+#define TXQ1_MTX_Q_PRE_LD_HI 1
+#define TXQ1_MTX_Q_PRE_LD_SZ 1
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ1_MTX_Q_RND_MODE_SFT 6
+#define TXQ1_MTX_Q_RND_MODE_HI 7
+#define TXQ1_MTX_Q_RND_MODE_SZ 2
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_SZ 16
+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ1_MTX_Q_ID_MAP_L_HI 31
+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ2_MTX_Q_PRE_LD_SFT 1
+#define TXQ2_MTX_Q_PRE_LD_HI 1
+#define TXQ2_MTX_Q_PRE_LD_SZ 1
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ2_MTX_Q_RND_MODE_SFT 6
+#define TXQ2_MTX_Q_RND_MODE_HI 7
+#define TXQ2_MTX_Q_RND_MODE_SZ 2
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_SZ 16
+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ2_MTX_Q_ID_MAP_L_HI 31
+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ3_MTX_Q_PRE_LD_SFT 1
+#define TXQ3_MTX_Q_PRE_LD_HI 1
+#define TXQ3_MTX_Q_PRE_LD_SZ 1
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ3_MTX_Q_RND_MODE_SFT 6
+#define TXQ3_MTX_Q_RND_MODE_HI 7
+#define TXQ3_MTX_Q_RND_MODE_SZ 2
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_SZ 16
+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ3_MTX_Q_ID_MAP_L_HI 31
+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ4_MTX_Q_PRE_LD_SFT 1
+#define TXQ4_MTX_Q_PRE_LD_HI 1
+#define TXQ4_MTX_Q_PRE_LD_SZ 1
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ4_MTX_Q_RND_MODE_SFT 6
+#define TXQ4_MTX_Q_RND_MODE_HI 7
+#define TXQ4_MTX_Q_RND_MODE_SZ 2
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_SZ 16
+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ4_MTX_Q_ID_MAP_L_HI 31
+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define INFO0_MSK 0xffffffff
+#define INFO0_I_MSK 0x00000000
+#define INFO0_SFT 0
+#define INFO0_HI 31
+#define INFO0_SZ 32
+#define INFO1_MSK 0xffffffff
+#define INFO1_I_MSK 0x00000000
+#define INFO1_SFT 0
+#define INFO1_HI 31
+#define INFO1_SZ 32
+#define INFO2_MSK 0xffffffff
+#define INFO2_I_MSK 0x00000000
+#define INFO2_SFT 0
+#define INFO2_HI 31
+#define INFO2_SZ 32
+#define INFO3_MSK 0xffffffff
+#define INFO3_I_MSK 0x00000000
+#define INFO3_SFT 0
+#define INFO3_HI 31
+#define INFO3_SZ 32
+#define INFO4_MSK 0xffffffff
+#define INFO4_I_MSK 0x00000000
+#define INFO4_SFT 0
+#define INFO4_HI 31
+#define INFO4_SZ 32
+#define INFO5_MSK 0xffffffff
+#define INFO5_I_MSK 0x00000000
+#define INFO5_SFT 0
+#define INFO5_HI 31
+#define INFO5_SZ 32
+#define INFO6_MSK 0xffffffff
+#define INFO6_I_MSK 0x00000000
+#define INFO6_SFT 0
+#define INFO6_HI 31
+#define INFO6_SZ 32
+#define INFO7_MSK 0xffffffff
+#define INFO7_I_MSK 0x00000000
+#define INFO7_SFT 0
+#define INFO7_HI 31
+#define INFO7_SZ 32
+#define INFO8_MSK 0xffffffff
+#define INFO8_I_MSK 0x00000000
+#define INFO8_SFT 0
+#define INFO8_HI 31
+#define INFO8_SZ 32
+#define INFO9_MSK 0xffffffff
+#define INFO9_I_MSK 0x00000000
+#define INFO9_SFT 0
+#define INFO9_HI 31
+#define INFO9_SZ 32
+#define INFO10_MSK 0xffffffff
+#define INFO10_I_MSK 0x00000000
+#define INFO10_SFT 0
+#define INFO10_HI 31
+#define INFO10_SZ 32
+#define INFO11_MSK 0xffffffff
+#define INFO11_I_MSK 0x00000000
+#define INFO11_SFT 0
+#define INFO11_HI 31
+#define INFO11_SZ 32
+#define INFO12_MSK 0xffffffff
+#define INFO12_I_MSK 0x00000000
+#define INFO12_SFT 0
+#define INFO12_HI 31
+#define INFO12_SZ 32
+#define INFO13_MSK 0xffffffff
+#define INFO13_I_MSK 0x00000000
+#define INFO13_SFT 0
+#define INFO13_HI 31
+#define INFO13_SZ 32
+#define INFO14_MSK 0xffffffff
+#define INFO14_I_MSK 0x00000000
+#define INFO14_SFT 0
+#define INFO14_HI 31
+#define INFO14_SZ 32
+#define INFO15_MSK 0xffffffff
+#define INFO15_I_MSK 0x00000000
+#define INFO15_SFT 0
+#define INFO15_HI 31
+#define INFO15_SZ 32
+#define INFO16_MSK 0xffffffff
+#define INFO16_I_MSK 0x00000000
+#define INFO16_SFT 0
+#define INFO16_HI 31
+#define INFO16_SZ 32
+#define INFO17_MSK 0xffffffff
+#define INFO17_I_MSK 0x00000000
+#define INFO17_SFT 0
+#define INFO17_HI 31
+#define INFO17_SZ 32
+#define INFO18_MSK 0xffffffff
+#define INFO18_I_MSK 0x00000000
+#define INFO18_SFT 0
+#define INFO18_HI 31
+#define INFO18_SZ 32
+#define INFO19_MSK 0xffffffff
+#define INFO19_I_MSK 0x00000000
+#define INFO19_SFT 0
+#define INFO19_HI 31
+#define INFO19_SZ 32
+#define INFO20_MSK 0xffffffff
+#define INFO20_I_MSK 0x00000000
+#define INFO20_SFT 0
+#define INFO20_HI 31
+#define INFO20_SZ 32
+#define INFO21_MSK 0xffffffff
+#define INFO21_I_MSK 0x00000000
+#define INFO21_SFT 0
+#define INFO21_HI 31
+#define INFO21_SZ 32
+#define INFO22_MSK 0xffffffff
+#define INFO22_I_MSK 0x00000000
+#define INFO22_SFT 0
+#define INFO22_HI 31
+#define INFO22_SZ 32
+#define INFO23_MSK 0xffffffff
+#define INFO23_I_MSK 0x00000000
+#define INFO23_SFT 0
+#define INFO23_HI 31
+#define INFO23_SZ 32
+#define INFO24_MSK 0xffffffff
+#define INFO24_I_MSK 0x00000000
+#define INFO24_SFT 0
+#define INFO24_HI 31
+#define INFO24_SZ 32
+#define INFO25_MSK 0xffffffff
+#define INFO25_I_MSK 0x00000000
+#define INFO25_SFT 0
+#define INFO25_HI 31
+#define INFO25_SZ 32
+#define INFO26_MSK 0xffffffff
+#define INFO26_I_MSK 0x00000000
+#define INFO26_SFT 0
+#define INFO26_HI 31
+#define INFO26_SZ 32
+#define INFO27_MSK 0xffffffff
+#define INFO27_I_MSK 0x00000000
+#define INFO27_SFT 0
+#define INFO27_HI 31
+#define INFO27_SZ 32
+#define INFO28_MSK 0xffffffff
+#define INFO28_I_MSK 0x00000000
+#define INFO28_SFT 0
+#define INFO28_HI 31
+#define INFO28_SZ 32
+#define INFO29_MSK 0xffffffff
+#define INFO29_I_MSK 0x00000000
+#define INFO29_SFT 0
+#define INFO29_HI 31
+#define INFO29_SZ 32
+#define INFO30_MSK 0xffffffff
+#define INFO30_I_MSK 0x00000000
+#define INFO30_SFT 0
+#define INFO30_HI 31
+#define INFO30_SZ 32
+#define INFO31_MSK 0xffffffff
+#define INFO31_I_MSK 0x00000000
+#define INFO31_SFT 0
+#define INFO31_HI 31
+#define INFO31_SZ 32
+#define INFO32_MSK 0xffffffff
+#define INFO32_I_MSK 0x00000000
+#define INFO32_SFT 0
+#define INFO32_HI 31
+#define INFO32_SZ 32
+#define INFO33_MSK 0xffffffff
+#define INFO33_I_MSK 0x00000000
+#define INFO33_SFT 0
+#define INFO33_HI 31
+#define INFO33_SZ 32
+#define INFO34_MSK 0xffffffff
+#define INFO34_I_MSK 0x00000000
+#define INFO34_SFT 0
+#define INFO34_HI 31
+#define INFO34_SZ 32
+#define INFO35_MSK 0xffffffff
+#define INFO35_I_MSK 0x00000000
+#define INFO35_SFT 0
+#define INFO35_HI 31
+#define INFO35_SZ 32
+#define INFO36_MSK 0xffffffff
+#define INFO36_I_MSK 0x00000000
+#define INFO36_SFT 0
+#define INFO36_HI 31
+#define INFO36_SZ 32
+#define INFO37_MSK 0xffffffff
+#define INFO37_I_MSK 0x00000000
+#define INFO37_SFT 0
+#define INFO37_HI 31
+#define INFO37_SZ 32
+#define INFO38_MSK 0xffffffff
+#define INFO38_I_MSK 0x00000000
+#define INFO38_SFT 0
+#define INFO38_HI 31
+#define INFO38_SZ 32
+#define INFO_MASK_MSK 0xffffffff
+#define INFO_MASK_I_MSK 0x00000000
+#define INFO_MASK_SFT 0
+#define INFO_MASK_HI 31
+#define INFO_MASK_SZ 32
+#define INFO_DEF_RATE_MSK 0x0000003f
+#define INFO_DEF_RATE_I_MSK 0xffffffc0
+#define INFO_DEF_RATE_SFT 0
+#define INFO_DEF_RATE_HI 5
+#define INFO_DEF_RATE_SZ 6
+#define INFO_MRX_OFFSET_MSK 0x000f0000
+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
+#define INFO_MRX_OFFSET_SFT 16
+#define INFO_MRX_OFFSET_HI 19
+#define INFO_MRX_OFFSET_SZ 4
+#define BCAST_RATEUNKNOW_MSK 0x3f000000
+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
+#define BCAST_RATEUNKNOW_SFT 24
+#define BCAST_RATEUNKNOW_HI 29
+#define BCAST_RATEUNKNOW_SZ 6
+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
+#define INFO_IDX_TBL_ADDR_SFT 0
+#define INFO_IDX_TBL_ADDR_HI 31
+#define INFO_IDX_TBL_ADDR_SZ 32
+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
+#define INFO_LEN_TBL_ADDR_SFT 0
+#define INFO_LEN_TBL_ADDR_HI 31
+#define INFO_LEN_TBL_ADDR_SZ 32
+#define IC_TAG_31_0_MSK 0xffffffff
+#define IC_TAG_31_0_I_MSK 0x00000000
+#define IC_TAG_31_0_SFT 0
+#define IC_TAG_31_0_HI 31
+#define IC_TAG_31_0_SZ 32
+#define IC_TAG_63_32_MSK 0xffffffff
+#define IC_TAG_63_32_I_MSK 0x00000000
+#define IC_TAG_63_32_SFT 0
+#define IC_TAG_63_32_HI 31
+#define IC_TAG_63_32_SZ 32
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define ASIC_TAG_MSK 0xff000000
+#define ASIC_TAG_I_MSK 0x00ffffff
+#define ASIC_TAG_SFT 24
+#define ASIC_TAG_HI 31
+#define ASIC_TAG_SZ 8
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define CBR_RG_EN_MANUAL_MSK 0x00000001
+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_MANUAL_SFT 0
+#define CBR_RG_EN_MANUAL_HI 0
+#define CBR_RG_EN_MANUAL_SZ 1
+#define CBR_RG_TX_EN_MSK 0x00000002
+#define CBR_RG_TX_EN_I_MSK 0xfffffffd
+#define CBR_RG_TX_EN_SFT 1
+#define CBR_RG_TX_EN_HI 1
+#define CBR_RG_TX_EN_SZ 1
+#define CBR_RG_TX_PA_EN_MSK 0x00000004
+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
+#define CBR_RG_TX_PA_EN_SFT 2
+#define CBR_RG_TX_PA_EN_HI 2
+#define CBR_RG_TX_PA_EN_SZ 1
+#define CBR_RG_TX_DAC_EN_MSK 0x00000008
+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define CBR_RG_TX_DAC_EN_SFT 3
+#define CBR_RG_TX_DAC_EN_HI 3
+#define CBR_RG_TX_DAC_EN_SZ 1
+#define CBR_RG_RX_AGC_MSK 0x00000010
+#define CBR_RG_RX_AGC_I_MSK 0xffffffef
+#define CBR_RG_RX_AGC_SFT 4
+#define CBR_RG_RX_AGC_HI 4
+#define CBR_RG_RX_AGC_SZ 1
+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define CBR_RG_RX_GAIN_MANUAL_SFT 5
+#define CBR_RG_RX_GAIN_MANUAL_HI 5
+#define CBR_RG_RX_GAIN_MANUAL_SZ 1
+#define CBR_RG_RFG_MSK 0x000000c0
+#define CBR_RG_RFG_I_MSK 0xffffff3f
+#define CBR_RG_RFG_SFT 6
+#define CBR_RG_RFG_HI 7
+#define CBR_RG_RFG_SZ 2
+#define CBR_RG_PGAG_MSK 0x00000f00
+#define CBR_RG_PGAG_I_MSK 0xfffff0ff
+#define CBR_RG_PGAG_SFT 8
+#define CBR_RG_PGAG_HI 11
+#define CBR_RG_PGAG_SZ 4
+#define CBR_RG_MODE_MSK 0x00003000
+#define CBR_RG_MODE_I_MSK 0xffffcfff
+#define CBR_RG_MODE_SFT 12
+#define CBR_RG_MODE_HI 13
+#define CBR_RG_MODE_SZ 2
+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define CBR_RG_EN_TX_TRSW_SFT 14
+#define CBR_RG_EN_TX_TRSW_HI 14
+#define CBR_RG_EN_TX_TRSW_SZ 1
+#define CBR_RG_EN_SX_MSK 0x00008000
+#define CBR_RG_EN_SX_I_MSK 0xffff7fff
+#define CBR_RG_EN_SX_SFT 15
+#define CBR_RG_EN_SX_HI 15
+#define CBR_RG_EN_SX_SZ 1
+#define CBR_RG_EN_RX_LNA_MSK 0x00010000
+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define CBR_RG_EN_RX_LNA_SFT 16
+#define CBR_RG_EN_RX_LNA_HI 16
+#define CBR_RG_EN_RX_LNA_SZ 1
+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define CBR_RG_EN_RX_MIXER_SFT 17
+#define CBR_RG_EN_RX_MIXER_HI 17
+#define CBR_RG_EN_RX_MIXER_SZ 1
+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define CBR_RG_EN_RX_DIV2_SFT 18
+#define CBR_RG_EN_RX_DIV2_HI 18
+#define CBR_RG_EN_RX_DIV2_SZ 1
+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define CBR_RG_EN_RX_LOBUF_SFT 19
+#define CBR_RG_EN_RX_LOBUF_HI 19
+#define CBR_RG_EN_RX_LOBUF_SZ 1
+#define CBR_RG_EN_RX_TZ_MSK 0x00100000
+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
+#define CBR_RG_EN_RX_TZ_SFT 20
+#define CBR_RG_EN_RX_TZ_HI 20
+#define CBR_RG_EN_RX_TZ_SZ 1
+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define CBR_RG_EN_RX_FILTER_SFT 21
+#define CBR_RG_EN_RX_FILTER_HI 21
+#define CBR_RG_EN_RX_FILTER_SZ 1
+#define CBR_RG_EN_RX_HPF_MSK 0x00400000
+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define CBR_RG_EN_RX_HPF_SFT 22
+#define CBR_RG_EN_RX_HPF_HI 22
+#define CBR_RG_EN_RX_HPF_SZ 1
+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define CBR_RG_EN_RX_RSSI_SFT 23
+#define CBR_RG_EN_RX_RSSI_HI 23
+#define CBR_RG_EN_RX_RSSI_SZ 1
+#define CBR_RG_EN_ADC_MSK 0x01000000
+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
+#define CBR_RG_EN_ADC_SFT 24
+#define CBR_RG_EN_ADC_HI 24
+#define CBR_RG_EN_ADC_SZ 1
+#define CBR_RG_EN_TX_MOD_MSK 0x02000000
+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define CBR_RG_EN_TX_MOD_SFT 25
+#define CBR_RG_EN_TX_MOD_HI 25
+#define CBR_RG_EN_TX_MOD_SZ 1
+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define CBR_RG_EN_TX_DIV2_SFT 26
+#define CBR_RG_EN_TX_DIV2_HI 26
+#define CBR_RG_EN_TX_DIV2_SZ 1
+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
+#define CBR_RG_EN_TX_DIV2_BUF_HI 27
+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define CBR_RG_EN_TX_LOBF_SFT 28
+#define CBR_RG_EN_TX_LOBF_HI 28
+#define CBR_RG_EN_TX_LOBF_SZ 1
+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define CBR_RG_EN_RX_LOBF_SFT 29
+#define CBR_RG_EN_RX_LOBF_HI 29
+#define CBR_RG_EN_RX_LOBF_SZ 1
+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define CBR_RG_SEL_DPLL_CLK_SFT 30
+#define CBR_RG_SEL_DPLL_CLK_HI 30
+#define CBR_RG_SEL_DPLL_CLK_SZ 1
+#define CBR_RG_EN_TX_DPD_MSK 0x00000001
+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define CBR_RG_EN_TX_DPD_SFT 0
+#define CBR_RG_EN_TX_DPD_HI 0
+#define CBR_RG_EN_TX_DPD_SZ 1
+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define CBR_RG_EN_TX_TSSI_SFT 1
+#define CBR_RG_EN_TX_TSSI_HI 1
+#define CBR_RG_EN_TX_TSSI_SZ 1
+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define CBR_RG_EN_RX_IQCAL_SFT 2
+#define CBR_RG_EN_RX_IQCAL_HI 2
+#define CBR_RG_EN_RX_IQCAL_SZ 1
+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define CBR_RG_EN_TX_DAC_CAL_SFT 3
+#define CBR_RG_EN_TX_DAC_CAL_HI 3
+#define CBR_RG_EN_TX_DAC_CAL_SZ 1
+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
+#define CBR_RG_EN_TX_SELF_MIXER_HI 4
+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define CBR_RG_EN_TX_DAC_OUT_SFT 5
+#define CBR_RG_EN_TX_DAC_OUT_HI 5
+#define CBR_RG_EN_TX_DAC_OUT_SZ 1
+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define CBR_RG_EN_LDO_RX_FE_SFT 6
+#define CBR_RG_EN_LDO_RX_FE_HI 6
+#define CBR_RG_EN_LDO_RX_FE_SZ 1
+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define CBR_RG_EN_LDO_ABB_SFT 7
+#define CBR_RG_EN_LDO_ABB_HI 7
+#define CBR_RG_EN_LDO_ABB_SZ 1
+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define CBR_RG_EN_LDO_AFE_SFT 8
+#define CBR_RG_EN_LDO_AFE_HI 8
+#define CBR_RG_EN_LDO_AFE_SZ 1
+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_CHPLDO_SFT 9
+#define CBR_RG_EN_SX_CHPLDO_HI 9
+#define CBR_RG_EN_SX_CHPLDO_SZ 1
+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_LOBFLDO_SFT 10
+#define CBR_RG_EN_SX_LOBFLDO_HI 10
+#define CBR_RG_EN_SX_LOBFLDO_SZ 1
+#define CBR_RG_EN_IREF_RX_MSK 0x00000800
+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define CBR_RG_EN_IREF_RX_SFT 11
+#define CBR_RG_EN_IREF_RX_HI 11
+#define CBR_RG_EN_IREF_RX_SZ 1
+#define CBR_RG_DCDC_MODE_MSK 0x00001000
+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
+#define CBR_RG_DCDC_MODE_SFT 12
+#define CBR_RG_DCDC_MODE_HI 12
+#define CBR_RG_DCDC_MODE_SZ 1
+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define CBR_RG_LDO_LEVEL_ABB_SFT 3
+#define CBR_RG_LDO_LEVEL_ABB_HI 5
+#define CBR_RG_LDO_LEVEL_ABB_SZ 3
+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define CBR_RG_LDO_LEVEL_AFE_SFT 6
+#define CBR_RG_LDO_LEVEL_AFE_HI 8
+#define CBR_RG_LDO_LEVEL_AFE_SZ 3
+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define CBR_RG_DP_LDO_LEVEL_SFT 18
+#define CBR_RG_DP_LDO_LEVEL_HI 20
+#define CBR_RG_DP_LDO_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
+#define CBR_RG_BUCK_LEVEL_SFT 27
+#define CBR_RG_BUCK_LEVEL_HI 29
+#define CBR_RG_BUCK_LEVEL_SZ 3
+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define CBR_RG_EN_RX_PADSW_SFT 0
+#define CBR_RG_EN_RX_PADSW_HI 0
+#define CBR_RG_EN_RX_PADSW_SZ 1
+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define CBR_RG_EN_RX_TESTNODE_SFT 1
+#define CBR_RG_EN_RX_TESTNODE_HI 1
+#define CBR_RG_EN_RX_TESTNODE_SZ 1
+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define CBR_RG_RX_ABBCFIX_SFT 2
+#define CBR_RG_RX_ABBCFIX_HI 2
+#define CBR_RG_RX_ABBCFIX_SZ 1
+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define CBR_RG_RX_ABBCTUNE_SFT 3
+#define CBR_RG_RX_ABBCTUNE_HI 8
+#define CBR_RG_RX_ABBCTUNE_SZ 6
+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define CBR_RG_RX_ABB_N_MODE_SFT 10
+#define CBR_RG_RX_ABB_N_MODE_HI 10
+#define CBR_RG_RX_ABB_N_MODE_SZ 1
+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define CBR_RG_RX_EN_LOOPA_SFT 11
+#define CBR_RG_RX_EN_LOOPA_HI 11
+#define CBR_RG_RX_EN_LOOPA_SZ 1
+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define CBR_RG_RX_FILTERI1ST_SFT 12
+#define CBR_RG_RX_FILTERI1ST_HI 13
+#define CBR_RG_RX_FILTERI1ST_SZ 2
+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define CBR_RG_RX_FILTERI2ND_SFT 14
+#define CBR_RG_RX_FILTERI2ND_HI 15
+#define CBR_RG_RX_FILTERI2ND_SZ 2
+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define CBR_RG_RX_FILTERI3RD_SFT 16
+#define CBR_RG_RX_FILTERI3RD_HI 17
+#define CBR_RG_RX_FILTERI3RD_SZ 2
+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define CBR_RG_RX_FILTERI_COURSE_SFT 18
+#define CBR_RG_RX_FILTERI_COURSE_HI 19
+#define CBR_RG_RX_FILTERI_COURSE_SZ 2
+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define CBR_RG_RX_FILTERVCM_SFT 20
+#define CBR_RG_RX_FILTERVCM_HI 21
+#define CBR_RG_RX_FILTERVCM_SZ 2
+#define CBR_RG_RX_HPF3M_MSK 0x00400000
+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
+#define CBR_RG_RX_HPF3M_SFT 22
+#define CBR_RG_RX_HPF3M_HI 22
+#define CBR_RG_RX_HPF3M_SZ 1
+#define CBR_RG_RX_HPF300K_MSK 0x00800000
+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
+#define CBR_RG_RX_HPF300K_SFT 23
+#define CBR_RG_RX_HPF300K_HI 23
+#define CBR_RG_RX_HPF300K_SZ 1
+#define CBR_RG_RX_HPFI_MSK 0x03000000
+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
+#define CBR_RG_RX_HPFI_SFT 24
+#define CBR_RG_RX_HPFI_HI 25
+#define CBR_RG_RX_HPFI_SZ 2
+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
+#define CBR_RG_RX_HPF_FINALCORNER_HI 27
+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define CBR_RG_RX_HPF_VCMCON2_SFT 6
+#define CBR_RG_RX_HPF_VCMCON2_HI 7
+#define CBR_RG_RX_HPF_VCMCON2_SZ 2
+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define CBR_RG_RX_HPF_VCMCON_SFT 8
+#define CBR_RG_RX_HPF_VCMCON_HI 9
+#define CBR_RG_RX_HPF_VCMCON_SZ 2
+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define CBR_RG_RX_OUTVCM_SFT 10
+#define CBR_RG_RX_OUTVCM_HI 11
+#define CBR_RG_RX_OUTVCM_SZ 2
+#define CBR_RG_RX_TZI_MSK 0x00003000
+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
+#define CBR_RG_RX_TZI_SFT 12
+#define CBR_RG_RX_TZI_HI 13
+#define CBR_RG_RX_TZI_SZ 2
+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define CBR_RG_RX_TZ_VCM_SFT 15
+#define CBR_RG_RX_TZ_VCM_HI 16
+#define CBR_RG_RX_TZ_VCM_SZ 2
+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
+#define CBR_RG_RX_ADCRSSI_VCM_HI 22
+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define CBR_RG_RX_REC_LPFCORNER_SFT 23
+#define CBR_RG_RX_REC_LPFCORNER_HI 24
+#define CBR_RG_RX_REC_LPFCORNER_SZ 2
+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
+#define CBR_RG_RSSI_CLOCK_GATING_HI 25
+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define CBR_RG_TXPGA_CAPSW_SFT 0
+#define CBR_RG_TXPGA_CAPSW_HI 1
+#define CBR_RG_TXPGA_CAPSW_SZ 2
+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define CBR_RG_TXPGA_MAIN_SFT 2
+#define CBR_RG_TXPGA_MAIN_HI 7
+#define CBR_RG_TXPGA_MAIN_SZ 6
+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define CBR_RG_TXPGA_STEER_SFT 8
+#define CBR_RG_TXPGA_STEER_HI 13
+#define CBR_RG_TXPGA_STEER_SZ 6
+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define CBR_RG_TXMOD_GMCELL_SFT 14
+#define CBR_RG_TXMOD_GMCELL_HI 15
+#define CBR_RG_TXMOD_GMCELL_SZ 2
+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define CBR_RG_TXLPF_GMCELL_SFT 16
+#define CBR_RG_TXLPF_GMCELL_HI 17
+#define CBR_RG_TXLPF_GMCELL_SZ 2
+#define CBR_RG_PACELL_EN_MSK 0x001c0000
+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
+#define CBR_RG_PACELL_EN_SFT 18
+#define CBR_RG_PACELL_EN_HI 20
+#define CBR_RG_PACELL_EN_SZ 3
+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define CBR_RG_PABIAS_CTRL_SFT 21
+#define CBR_RG_PABIAS_CTRL_HI 24
+#define CBR_RG_PABIAS_CTRL_SZ 4
+#define CBR_RG_PABIAS_AB_MSK 0x02000000
+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
+#define CBR_RG_PABIAS_AB_SFT 25
+#define CBR_RG_PABIAS_AB_HI 25
+#define CBR_RG_PABIAS_AB_SZ 1
+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define CBR_RG_TX_DIV_VSET_SFT 26
+#define CBR_RG_TX_DIV_VSET_HI 27
+#define CBR_RG_TX_DIV_VSET_SZ 2
+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define CBR_RG_TX_LOBUF_VSET_SFT 28
+#define CBR_RG_TX_LOBUF_VSET_HI 29
+#define CBR_RG_TX_LOBUF_VSET_SZ 2
+#define CBR_RG_RX_SQDC_MSK 0x00000007
+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
+#define CBR_RG_RX_SQDC_SFT 0
+#define CBR_RG_RX_SQDC_HI 2
+#define CBR_RG_RX_SQDC_SZ 3
+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define CBR_RG_RX_DIV2_CORE_SFT 3
+#define CBR_RG_RX_DIV2_CORE_HI 4
+#define CBR_RG_RX_DIV2_CORE_SZ 2
+#define CBR_RG_RX_LOBUF_MSK 0x00000060
+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
+#define CBR_RG_RX_LOBUF_SFT 5
+#define CBR_RG_RX_LOBUF_HI 6
+#define CBR_RG_RX_LOBUF_SZ 2
+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define CBR_RG_TX_DPDGM_BIAS_SFT 7
+#define CBR_RG_TX_DPDGM_BIAS_HI 10
+#define CBR_RG_TX_DPDGM_BIAS_SZ 4
+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define CBR_RG_TX_DPD_DIV_SFT 11
+#define CBR_RG_TX_DPD_DIV_HI 14
+#define CBR_RG_TX_DPD_DIV_SZ 4
+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define CBR_RG_TX_TSSI_BIAS_SFT 15
+#define CBR_RG_TX_TSSI_BIAS_HI 17
+#define CBR_RG_TX_TSSI_BIAS_SZ 3
+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define CBR_RG_TX_TSSI_DIV_SFT 18
+#define CBR_RG_TX_TSSI_DIV_HI 20
+#define CBR_RG_TX_TSSI_DIV_SZ 3
+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
+#define CBR_RG_TX_TSSI_TESTMODE_HI 21
+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define CBR_RG_TX_TSSI_TEST_SFT 22
+#define CBR_RG_TX_TSSI_TEST_HI 23
+#define CBR_RG_TX_TSSI_TEST_SZ 2
+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_HG_LNA_GC_SFT 0
+#define CBR_RG_RX_HG_LNA_GC_HI 1
+#define CBR_RG_RX_HG_LNA_GC_SZ 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_HG_TZ_GC_SFT 14
+#define CBR_RG_RX_HG_TZ_GC_HI 15
+#define CBR_RG_RX_HG_TZ_GC_SZ 2
+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_HG_TZ_CAP_SFT 16
+#define CBR_RG_RX_HG_TZ_CAP_HI 18
+#define CBR_RG_RX_HG_TZ_CAP_SZ 3
+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_MG_LNA_GC_SFT 0
+#define CBR_RG_RX_MG_LNA_GC_HI 1
+#define CBR_RG_RX_MG_LNA_GC_SZ 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_MG_TZ_GC_SFT 14
+#define CBR_RG_RX_MG_TZ_GC_HI 15
+#define CBR_RG_RX_MG_TZ_GC_SZ 2
+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_MG_TZ_CAP_SFT 16
+#define CBR_RG_RX_MG_TZ_CAP_HI 18
+#define CBR_RG_RX_MG_TZ_CAP_SZ 3
+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_LG_LNA_GC_SFT 0
+#define CBR_RG_RX_LG_LNA_GC_HI 1
+#define CBR_RG_RX_LG_LNA_GC_SZ 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_LG_TZ_GC_SFT 14
+#define CBR_RG_RX_LG_TZ_GC_HI 15
+#define CBR_RG_RX_LG_TZ_GC_SZ 2
+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_LG_TZ_CAP_SFT 16
+#define CBR_RG_RX_LG_TZ_CAP_HI 18
+#define CBR_RG_RX_LG_TZ_CAP_SZ 3
+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_ULG_LNA_GC_SFT 0
+#define CBR_RG_RX_ULG_LNA_GC_HI 1
+#define CBR_RG_RX_ULG_LNA_GC_SZ 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_ULG_TZ_GC_SFT 14
+#define CBR_RG_RX_ULG_TZ_GC_HI 15
+#define CBR_RG_RX_ULG_TZ_GC_SZ 2
+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
+#define CBR_RG_RX_ULG_TZ_CAP_HI 18
+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define CBR_RG_HPF1_FAST_SET_X_SFT 0
+#define CBR_RG_HPF1_FAST_SET_X_HI 0
+#define CBR_RG_HPF1_FAST_SET_X_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
+#define CBR_RG_HPF1_FAST_SET_Y_HI 1
+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
+#define CBR_RG_HPF1_FAST_SET_Z_HI 2
+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
+#define CBR_RG_HPF_T1A_MSK 0x00000018
+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
+#define CBR_RG_HPF_T1A_SFT 3
+#define CBR_RG_HPF_T1A_HI 4
+#define CBR_RG_HPF_T1A_SZ 2
+#define CBR_RG_HPF_T1B_MSK 0x00000060
+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
+#define CBR_RG_HPF_T1B_SFT 5
+#define CBR_RG_HPF_T1B_HI 6
+#define CBR_RG_HPF_T1B_SZ 2
+#define CBR_RG_HPF_T1C_MSK 0x00000180
+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
+#define CBR_RG_HPF_T1C_SFT 7
+#define CBR_RG_HPF_T1C_HI 8
+#define CBR_RG_HPF_T1C_SZ 2
+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
+#define CBR_RG_RX_LNA_TRI_SEL_HI 10
+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define CBR_RG_RX_LNA_SETTLE_SFT 11
+#define CBR_RG_RX_LNA_SETTLE_HI 12
+#define CBR_RG_RX_LNA_SETTLE_SZ 2
+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define CBR_RG_ADC_CLKSEL_SFT 0
+#define CBR_RG_ADC_CLKSEL_HI 0
+#define CBR_RG_ADC_CLKSEL_SZ 1
+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define CBR_RG_ADC_DIBIAS_SFT 1
+#define CBR_RG_ADC_DIBIAS_HI 2
+#define CBR_RG_ADC_DIBIAS_SZ 2
+#define CBR_RG_ADC_DIVR_MSK 0x00000008
+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
+#define CBR_RG_ADC_DIVR_SFT 3
+#define CBR_RG_ADC_DIVR_HI 3
+#define CBR_RG_ADC_DIVR_SZ 1
+#define CBR_RG_ADC_DVCMI_MSK 0x00000030
+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define CBR_RG_ADC_DVCMI_SFT 4
+#define CBR_RG_ADC_DVCMI_HI 5
+#define CBR_RG_ADC_DVCMI_SZ 2
+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define CBR_RG_ADC_SAMSEL_SFT 6
+#define CBR_RG_ADC_SAMSEL_HI 9
+#define CBR_RG_ADC_SAMSEL_SZ 4
+#define CBR_RG_ADC_STNBY_MSK 0x00000400
+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
+#define CBR_RG_ADC_STNBY_SFT 10
+#define CBR_RG_ADC_STNBY_HI 10
+#define CBR_RG_ADC_STNBY_SZ 1
+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define CBR_RG_ADC_TESTMODE_SFT 11
+#define CBR_RG_ADC_TESTMODE_HI 11
+#define CBR_RG_ADC_TESTMODE_SZ 1
+#define CBR_RG_ADC_TSEL_MSK 0x0000f000
+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
+#define CBR_RG_ADC_TSEL_SFT 12
+#define CBR_RG_ADC_TSEL_HI 15
+#define CBR_RG_ADC_TSEL_SZ 4
+#define CBR_RG_ADC_VRSEL_MSK 0x00030000
+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define CBR_RG_ADC_VRSEL_SFT 16
+#define CBR_RG_ADC_VRSEL_HI 17
+#define CBR_RG_ADC_VRSEL_SZ 2
+#define CBR_RG_DICMP_MSK 0x000c0000
+#define CBR_RG_DICMP_I_MSK 0xfff3ffff
+#define CBR_RG_DICMP_SFT 18
+#define CBR_RG_DICMP_HI 19
+#define CBR_RG_DICMP_SZ 2
+#define CBR_RG_DIOP_MSK 0x00300000
+#define CBR_RG_DIOP_I_MSK 0xffcfffff
+#define CBR_RG_DIOP_SFT 20
+#define CBR_RG_DIOP_HI 21
+#define CBR_RG_DIOP_SZ 2
+#define CBR_RG_DACI1ST_MSK 0x00000003
+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
+#define CBR_RG_DACI1ST_SFT 0
+#define CBR_RG_DACI1ST_HI 1
+#define CBR_RG_DACI1ST_SZ 2
+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define CBR_RG_TX_DACLPF_IFINE_SFT 4
+#define CBR_RG_TX_DACLPF_IFINE_HI 5
+#define CBR_RG_TX_DACLPF_IFINE_SZ 2
+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define CBR_RG_TX_DACLPF_VCM_SFT 6
+#define CBR_RG_TX_DACLPF_VCM_HI 7
+#define CBR_RG_TX_DACLPF_VCM_SZ 2
+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define CBR_RG_TX_DAC_IBIAS_SFT 9
+#define CBR_RG_TX_DAC_IBIAS_HI 10
+#define CBR_RG_TX_DAC_IBIAS_SZ 2
+#define CBR_RG_TX_DAC_OS_MSK 0x00003800
+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define CBR_RG_TX_DAC_OS_SFT 11
+#define CBR_RG_TX_DAC_OS_HI 13
+#define CBR_RG_TX_DAC_OS_SZ 3
+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define CBR_RG_TX_DAC_RCAL_SFT 14
+#define CBR_RG_TX_DAC_RCAL_HI 15
+#define CBR_RG_TX_DAC_RCAL_SZ 2
+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define CBR_RG_TX_DAC_TSEL_SFT 16
+#define CBR_RG_TX_DAC_TSEL_HI 19
+#define CBR_RG_TX_DAC_TSEL_SZ 4
+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define CBR_RG_TXLPF_BYPASS_SFT 21
+#define CBR_RG_TXLPF_BYPASS_HI 21
+#define CBR_RG_TXLPF_BYPASS_SZ 1
+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define CBR_RG_TXLPF_BOOSTI_SFT 22
+#define CBR_RG_TXLPF_BOOSTI_HI 22
+#define CBR_RG_TXLPF_BOOSTI_SZ 1
+#define CBR_RG_EN_SX_R3_MSK 0x00000001
+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
+#define CBR_RG_EN_SX_R3_SFT 0
+#define CBR_RG_EN_SX_R3_HI 0
+#define CBR_RG_EN_SX_R3_SZ 1
+#define CBR_RG_EN_SX_CH_MSK 0x00000002
+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
+#define CBR_RG_EN_SX_CH_SFT 1
+#define CBR_RG_EN_SX_CH_HI 1
+#define CBR_RG_EN_SX_CH_SZ 1
+#define CBR_RG_EN_SX_CHP_MSK 0x00000004
+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define CBR_RG_EN_SX_CHP_SFT 2
+#define CBR_RG_EN_SX_CHP_HI 2
+#define CBR_RG_EN_SX_CHP_SZ 1
+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define CBR_RG_EN_SX_DIVCK_SFT 3
+#define CBR_RG_EN_SX_DIVCK_HI 3
+#define CBR_RG_EN_SX_DIVCK_SZ 1
+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define CBR_RG_EN_SX_VCOBF_SFT 4
+#define CBR_RG_EN_SX_VCOBF_HI 4
+#define CBR_RG_EN_SX_VCOBF_SZ 1
+#define CBR_RG_EN_SX_VCO_MSK 0x00000020
+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define CBR_RG_EN_SX_VCO_SFT 5
+#define CBR_RG_EN_SX_VCO_HI 5
+#define CBR_RG_EN_SX_VCO_SZ 1
+#define CBR_RG_EN_SX_MOD_MSK 0x00000040
+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define CBR_RG_EN_SX_MOD_SFT 6
+#define CBR_RG_EN_SX_MOD_HI 6
+#define CBR_RG_EN_SX_MOD_SZ 1
+#define CBR_RG_EN_SX_LCK_MSK 0x00000080
+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
+#define CBR_RG_EN_SX_LCK_SFT 7
+#define CBR_RG_EN_SX_LCK_HI 7
+#define CBR_RG_EN_SX_LCK_SZ 1
+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define CBR_RG_EN_SX_DITHER_SFT 8
+#define CBR_RG_EN_SX_DITHER_HI 8
+#define CBR_RG_EN_SX_DITHER_SZ 1
+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_DELCAL_SFT 9
+#define CBR_RG_EN_SX_DELCAL_HI 9
+#define CBR_RG_EN_SX_DELCAL_SZ 1
+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
+#define CBR_RG_EN_SX_PC_BYPASS_HI 10
+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define CBR_RG_EN_SX_VT_MON_SFT 11
+#define CBR_RG_EN_SX_VT_MON_HI 11
+#define CBR_RG_EN_SX_VT_MON_SZ 1
+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
+#define CBR_RG_EN_SX_VT_MON_DG_HI 12
+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
+#define CBR_RG_EN_SX_DIV_MSK 0x00002000
+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define CBR_RG_EN_SX_DIV_SFT 13
+#define CBR_RG_EN_SX_DIV_HI 13
+#define CBR_RG_EN_SX_DIV_SZ 1
+#define CBR_RG_EN_SX_LPF_MSK 0x00004000
+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define CBR_RG_EN_SX_LPF_SFT 14
+#define CBR_RG_EN_SX_LPF_HI 14
+#define CBR_RG_EN_SX_LPF_SZ 1
+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define CBR_RG_SX_RFCTRL_F_SFT 0
+#define CBR_RG_SX_RFCTRL_F_HI 23
+#define CBR_RG_SX_RFCTRL_F_SZ 24
+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define CBR_RG_SX_SEL_CP_SFT 24
+#define CBR_RG_SX_SEL_CP_HI 27
+#define CBR_RG_SX_SEL_CP_SZ 4
+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define CBR_RG_SX_SEL_CS_SFT 28
+#define CBR_RG_SX_SEL_CS_HI 31
+#define CBR_RG_SX_SEL_CS_SZ 4
+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define CBR_RG_SX_RFCTRL_CH_SFT 0
+#define CBR_RG_SX_RFCTRL_CH_HI 10
+#define CBR_RG_SX_RFCTRL_CH_SZ 11
+#define CBR_RG_SX_SEL_C3_MSK 0x00007800
+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define CBR_RG_SX_SEL_C3_SFT 11
+#define CBR_RG_SX_SEL_C3_HI 14
+#define CBR_RG_SX_SEL_C3_SZ 4
+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define CBR_RG_SX_SEL_RS_SFT 15
+#define CBR_RG_SX_SEL_RS_HI 19
+#define CBR_RG_SX_SEL_RS_SZ 5
+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define CBR_RG_SX_SEL_R3_SFT 20
+#define CBR_RG_SX_SEL_R3_HI 24
+#define CBR_RG_SX_SEL_R3_SZ 5
+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define CBR_RG_SX_SEL_ICHP_SFT 0
+#define CBR_RG_SX_SEL_ICHP_HI 4
+#define CBR_RG_SX_SEL_ICHP_SZ 5
+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define CBR_RG_SX_SEL_PCHP_SFT 5
+#define CBR_RG_SX_SEL_PCHP_HI 9
+#define CBR_RG_SX_SEL_PCHP_SZ 5
+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define CBR_RG_SX_CHP_IOST_POL_SFT 18
+#define CBR_RG_SX_CHP_IOST_POL_HI 18
+#define CBR_RG_SX_CHP_IOST_POL_SZ 1
+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define CBR_RG_SX_CHP_IOST_SFT 19
+#define CBR_RG_SX_CHP_IOST_HI 21
+#define CBR_RG_SX_CHP_IOST_SZ 3
+#define CBR_RG_SX_PFDSEL_MSK 0x00400000
+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define CBR_RG_SX_PFDSEL_SFT 22
+#define CBR_RG_SX_PFDSEL_HI 22
+#define CBR_RG_SX_PFDSEL_SZ 1
+#define CBR_RG_SX_PFD_SET_MSK 0x00800000
+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define CBR_RG_SX_PFD_SET_SFT 23
+#define CBR_RG_SX_PFD_SET_HI 23
+#define CBR_RG_SX_PFD_SET_SZ 1
+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define CBR_RG_SX_PFD_SET1_SFT 24
+#define CBR_RG_SX_PFD_SET1_HI 24
+#define CBR_RG_SX_PFD_SET1_SZ 1
+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define CBR_RG_SX_PFD_SET2_SFT 25
+#define CBR_RG_SX_PFD_SET2_HI 25
+#define CBR_RG_SX_PFD_SET2_SZ 1
+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define CBR_RG_SX_VBNCAS_SEL_SFT 26
+#define CBR_RG_SX_VBNCAS_SEL_HI 26
+#define CBR_RG_SX_VBNCAS_SEL_SZ 1
+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define CBR_RG_SX_PFD_RST_H_SFT 27
+#define CBR_RG_SX_PFD_RST_H_HI 27
+#define CBR_RG_SX_PFD_RST_H_SZ 1
+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define CBR_RG_SX_PFD_TRUP_SFT 28
+#define CBR_RG_SX_PFD_TRUP_HI 28
+#define CBR_RG_SX_PFD_TRUP_SZ 1
+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define CBR_RG_SX_PFD_TRDN_SFT 29
+#define CBR_RG_SX_PFD_TRDN_HI 29
+#define CBR_RG_SX_PFD_TRDN_SZ 1
+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define CBR_RG_SX_PFD_TRSEL_SFT 30
+#define CBR_RG_SX_PFD_TRSEL_HI 30
+#define CBR_RG_SX_PFD_TRSEL_SZ 1
+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define CBR_RG_SX_VCOBA_R_SFT 0
+#define CBR_RG_SX_VCOBA_R_HI 2
+#define CBR_RG_SX_VCOBA_R_SZ 3
+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
+#define CBR_RG_SX_VCORSEL_SFT 3
+#define CBR_RG_SX_VCORSEL_HI 7
+#define CBR_RG_SX_VCORSEL_SZ 5
+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define CBR_RG_SX_VCOCUSEL_SFT 8
+#define CBR_RG_SX_VCOCUSEL_HI 11
+#define CBR_RG_SX_VCOCUSEL_SZ 4
+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define CBR_RG_SX_RXBFSEL_SFT 12
+#define CBR_RG_SX_RXBFSEL_HI 15
+#define CBR_RG_SX_RXBFSEL_SZ 4
+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define CBR_RG_SX_TXBFSEL_SFT 16
+#define CBR_RG_SX_TXBFSEL_HI 19
+#define CBR_RG_SX_TXBFSEL_SZ 4
+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define CBR_RG_SX_VCOBFSEL_SFT 20
+#define CBR_RG_SX_VCOBFSEL_HI 23
+#define CBR_RG_SX_VCOBFSEL_SZ 4
+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define CBR_RG_SX_DIVBFSEL_SFT 24
+#define CBR_RG_SX_DIVBFSEL_HI 27
+#define CBR_RG_SX_DIVBFSEL_SZ 4
+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define CBR_RG_SX_GNDR_SEL_SFT 28
+#define CBR_RG_SX_GNDR_SEL_HI 31
+#define CBR_RG_SX_GNDR_SEL_SZ 4
+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
+#define CBR_RG_SX_DITHER_WEIGHT_HI 1
+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
+#define CBR_RG_SX_MOD_ERRCMP_SFT 2
+#define CBR_RG_SX_MOD_ERRCMP_HI 3
+#define CBR_RG_SX_MOD_ERRCMP_SZ 2
+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define CBR_RG_SX_MOD_ORDER_SFT 4
+#define CBR_RG_SX_MOD_ORDER_HI 5
+#define CBR_RG_SX_MOD_ORDER_SZ 2
+#define CBR_RG_SX_SDM_D1_MSK 0x00000040
+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
+#define CBR_RG_SX_SDM_D1_SFT 6
+#define CBR_RG_SX_SDM_D1_HI 6
+#define CBR_RG_SX_SDM_D1_SZ 1
+#define CBR_RG_SX_SDM_D2_MSK 0x00000080
+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
+#define CBR_RG_SX_SDM_D2_SFT 7
+#define CBR_RG_SX_SDM_D2_HI 7
+#define CBR_RG_SX_SDM_D2_SZ 1
+#define CBR_RG_SDM_PASS_MSK 0x00000100
+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
+#define CBR_RG_SDM_PASS_SFT 8
+#define CBR_RG_SDM_PASS_HI 8
+#define CBR_RG_SDM_PASS_SZ 1
+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define CBR_RG_SX_RST_H_DIV_SFT 9
+#define CBR_RG_SX_RST_H_DIV_HI 9
+#define CBR_RG_SX_RST_H_DIV_SZ 1
+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define CBR_RG_SX_SDM_EDGE_SFT 10
+#define CBR_RG_SX_SDM_EDGE_HI 10
+#define CBR_RG_SX_SDM_EDGE_SZ 1
+#define CBR_RG_SX_XO_GM_MSK 0x00001800
+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define CBR_RG_SX_XO_GM_SFT 11
+#define CBR_RG_SX_XO_GM_HI 12
+#define CBR_RG_SX_XO_GM_SZ 2
+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define CBR_RG_SX_REFBYTWO_SFT 13
+#define CBR_RG_SX_REFBYTWO_HI 13
+#define CBR_RG_SX_REFBYTWO_SZ 1
+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_XO_SWCAP_SFT 14
+#define CBR_RG_SX_XO_SWCAP_HI 17
+#define CBR_RG_SX_XO_SWCAP_SZ 4
+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
+#define CBR_RG_SX_SDMLUT_INV_SFT 18
+#define CBR_RG_SX_SDMLUT_INV_HI 18
+#define CBR_RG_SX_SDMLUT_INV_SZ 1
+#define CBR_RG_SX_LCKEN_MSK 0x00080000
+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define CBR_RG_SX_LCKEN_SFT 19
+#define CBR_RG_SX_LCKEN_HI 19
+#define CBR_RG_SX_LCKEN_SZ 1
+#define CBR_RG_SX_PREVDD_MSK 0x00f00000
+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
+#define CBR_RG_SX_PREVDD_SFT 20
+#define CBR_RG_SX_PREVDD_HI 23
+#define CBR_RG_SX_PREVDD_SZ 4
+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define CBR_RG_SX_PSCONTERVDD_SFT 24
+#define CBR_RG_SX_PSCONTERVDD_HI 27
+#define CBR_RG_SX_PSCONTERVDD_SZ 4
+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
+#define CBR_RG_SX_MODDB_MSK 0x40000000
+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
+#define CBR_RG_SX_MODDB_SFT 30
+#define CBR_RG_SX_MODDB_HI 30
+#define CBR_RG_SX_MODDB_SZ 1
+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
+#define CBR_RG_SX_CV_CURVE_SEL_HI 1
+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
+#define CBR_RG_SX_SEL_DELAY_SFT 2
+#define CBR_RG_SX_SEL_DELAY_HI 6
+#define CBR_RG_SX_SEL_DELAY_SZ 5
+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
+#define CBR_RG_SX_REF_CYCLE_SFT 7
+#define CBR_RG_SX_REF_CYCLE_HI 10
+#define CBR_RG_SX_REF_CYCLE_SZ 4
+#define CBR_RG_SX_VCOBY16_MSK 0x00000800
+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
+#define CBR_RG_SX_VCOBY16_SFT 11
+#define CBR_RG_SX_VCOBY16_HI 11
+#define CBR_RG_SX_VCOBY16_SZ 1
+#define CBR_RG_SX_VCOBY32_MSK 0x00001000
+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
+#define CBR_RG_SX_VCOBY32_SFT 12
+#define CBR_RG_SX_VCOBY32_HI 12
+#define CBR_RG_SX_VCOBY32_SZ 1
+#define CBR_RG_SX_PH_MSK 0x00002000
+#define CBR_RG_SX_PH_I_MSK 0xffffdfff
+#define CBR_RG_SX_PH_SFT 13
+#define CBR_RG_SX_PH_HI 13
+#define CBR_RG_SX_PH_SZ 1
+#define CBR_RG_SX_PL_MSK 0x00004000
+#define CBR_RG_SX_PL_I_MSK 0xffffbfff
+#define CBR_RG_SX_PL_SFT 14
+#define CBR_RG_SX_PL_HI 14
+#define CBR_RG_SX_PL_SZ 1
+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define CBR_RG_SX_VT_MON_MODE_SFT 0
+#define CBR_RG_SX_VT_MON_MODE_HI 0
+#define CBR_RG_SX_VT_MON_MODE_SZ 1
+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_SX_VT_TH_HI_SFT 1
+#define CBR_RG_SX_VT_TH_HI_HI 2
+#define CBR_RG_SX_VT_TH_HI_SZ 2
+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_SX_VT_TH_LO_SFT 3
+#define CBR_RG_SX_VT_TH_LO_HI 4
+#define CBR_RG_SX_VT_TH_LO_SZ 2
+#define CBR_RG_SX_VT_SET_MSK 0x00000020
+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
+#define CBR_RG_SX_VT_SET_SFT 5
+#define CBR_RG_SX_VT_SET_HI 5
+#define CBR_RG_SX_VT_SET_SZ 1
+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define CBR_RG_SX_VT_MON_TMR_SFT 6
+#define CBR_RG_SX_VT_MON_TMR_HI 14
+#define CBR_RG_SX_VT_MON_TMR_SZ 9
+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
+#define CBR_RG_IDEAL_CYCLE_SFT 15
+#define CBR_RG_IDEAL_CYCLE_HI 27
+#define CBR_RG_IDEAL_CYCLE_SZ 13
+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define CBR_RG_EN_DP_VT_MON_SFT 0
+#define CBR_RG_EN_DP_VT_MON_HI 0
+#define CBR_RG_EN_DP_VT_MON_SZ 1
+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_DP_VT_TH_HI_SFT 1
+#define CBR_RG_DP_VT_TH_HI_HI 2
+#define CBR_RG_DP_VT_TH_HI_SZ 2
+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_DP_VT_TH_LO_SFT 3
+#define CBR_RG_DP_VT_TH_LO_HI 4
+#define CBR_RG_DP_VT_TH_LO_SZ 2
+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
+#define CBR_RG_DP_VT_MON_TMR_SFT 5
+#define CBR_RG_DP_VT_MON_TMR_HI 13
+#define CBR_RG_DP_VT_MON_TMR_SZ 9
+#define CBR_RG_DP_CK320BY2_MSK 0x00004000
+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define CBR_RG_DP_CK320BY2_SFT 14
+#define CBR_RG_DP_CK320BY2_HI 14
+#define CBR_RG_DP_CK320BY2_SZ 1
+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
+#define CBR_RG_SX_DELCTRL_SFT 15
+#define CBR_RG_SX_DELCTRL_HI 20
+#define CBR_RG_SX_DELCTRL_SZ 6
+#define CBR_RG_DP_OD_TEST_MSK 0x00200000
+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define CBR_RG_DP_OD_TEST_SFT 21
+#define CBR_RG_DP_OD_TEST_HI 21
+#define CBR_RG_DP_OD_TEST_SZ 1
+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define CBR_RG_DP_BBPLL_BP_SFT 0
+#define CBR_RG_DP_BBPLL_BP_HI 0
+#define CBR_RG_DP_BBPLL_BP_SZ 1
+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define CBR_RG_DP_BBPLL_ICP_SFT 1
+#define CBR_RG_DP_BBPLL_ICP_HI 2
+#define CBR_RG_DP_BBPLL_ICP_SZ 2
+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
+#define CBR_RG_DP_BBPLL_IDUAL_HI 4
+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define CBR_RG_DP_BBPLL_PD_SFT 9
+#define CBR_RG_DP_BBPLL_PD_HI 9
+#define CBR_RG_DP_BBPLL_PD_SZ 1
+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
+#define CBR_RG_DP_RP_MSK 0x00038000
+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
+#define CBR_RG_DP_RP_SFT 15
+#define CBR_RG_DP_RP_HI 17
+#define CBR_RG_DP_RP_SZ 3
+#define CBR_RG_DP_RHP_MSK 0x000c0000
+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
+#define CBR_RG_DP_RHP_SFT 18
+#define CBR_RG_DP_RHP_HI 19
+#define CBR_RG_DP_RHP_SZ 2
+#define CBR_RG_DP_DR3_MSK 0x00700000
+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
+#define CBR_RG_DP_DR3_SFT 20
+#define CBR_RG_DP_DR3_HI 22
+#define CBR_RG_DP_DR3_SZ 3
+#define CBR_RG_DP_DCP_MSK 0x07800000
+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
+#define CBR_RG_DP_DCP_SFT 23
+#define CBR_RG_DP_DCP_HI 26
+#define CBR_RG_DP_DCP_SZ 4
+#define CBR_RG_DP_DCS_MSK 0x78000000
+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
+#define CBR_RG_DP_DCS_SFT 27
+#define CBR_RG_DP_DCS_HI 30
+#define CBR_RG_DP_DCS_SZ 4
+#define CBR_RG_DP_FBDIV_MSK 0x00000fff
+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
+#define CBR_RG_DP_FBDIV_SFT 0
+#define CBR_RG_DP_FBDIV_HI 11
+#define CBR_RG_DP_FBDIV_SZ 12
+#define CBR_RG_DP_FODIV_MSK 0x003ff000
+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
+#define CBR_RG_DP_FODIV_SFT 12
+#define CBR_RG_DP_FODIV_HI 21
+#define CBR_RG_DP_FODIV_SZ 10
+#define CBR_RG_DP_REFDIV_MSK 0xffc00000
+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
+#define CBR_RG_DP_REFDIV_SFT 22
+#define CBR_RG_DP_REFDIV_HI 31
+#define CBR_RG_DP_REFDIV_SZ 10
+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG15_SFT 0
+#define CBR_RG_IDACAI_PGAG15_HI 5
+#define CBR_RG_IDACAI_PGAG15_SZ 6
+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG15_SFT 6
+#define CBR_RG_IDACAQ_PGAG15_HI 11
+#define CBR_RG_IDACAQ_PGAG15_SZ 6
+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG14_SFT 12
+#define CBR_RG_IDACAI_PGAG14_HI 17
+#define CBR_RG_IDACAI_PGAG14_SZ 6
+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG14_SFT 18
+#define CBR_RG_IDACAQ_PGAG14_HI 23
+#define CBR_RG_IDACAQ_PGAG14_SZ 6
+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG13_SFT 0
+#define CBR_RG_IDACAI_PGAG13_HI 5
+#define CBR_RG_IDACAI_PGAG13_SZ 6
+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG13_SFT 6
+#define CBR_RG_IDACAQ_PGAG13_HI 11
+#define CBR_RG_IDACAQ_PGAG13_SZ 6
+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG12_SFT 12
+#define CBR_RG_IDACAI_PGAG12_HI 17
+#define CBR_RG_IDACAI_PGAG12_SZ 6
+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG12_SFT 18
+#define CBR_RG_IDACAQ_PGAG12_HI 23
+#define CBR_RG_IDACAQ_PGAG12_SZ 6
+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG11_SFT 0
+#define CBR_RG_IDACAI_PGAG11_HI 5
+#define CBR_RG_IDACAI_PGAG11_SZ 6
+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG11_SFT 6
+#define CBR_RG_IDACAQ_PGAG11_HI 11
+#define CBR_RG_IDACAQ_PGAG11_SZ 6
+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG10_SFT 12
+#define CBR_RG_IDACAI_PGAG10_HI 17
+#define CBR_RG_IDACAI_PGAG10_SZ 6
+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG10_SFT 18
+#define CBR_RG_IDACAQ_PGAG10_HI 23
+#define CBR_RG_IDACAQ_PGAG10_SZ 6
+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG9_SFT 0
+#define CBR_RG_IDACAI_PGAG9_HI 5
+#define CBR_RG_IDACAI_PGAG9_SZ 6
+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG9_SFT 6
+#define CBR_RG_IDACAQ_PGAG9_HI 11
+#define CBR_RG_IDACAQ_PGAG9_SZ 6
+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG8_SFT 12
+#define CBR_RG_IDACAI_PGAG8_HI 17
+#define CBR_RG_IDACAI_PGAG8_SZ 6
+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG8_SFT 18
+#define CBR_RG_IDACAQ_PGAG8_HI 23
+#define CBR_RG_IDACAQ_PGAG8_SZ 6
+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG7_SFT 0
+#define CBR_RG_IDACAI_PGAG7_HI 5
+#define CBR_RG_IDACAI_PGAG7_SZ 6
+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG7_SFT 6
+#define CBR_RG_IDACAQ_PGAG7_HI 11
+#define CBR_RG_IDACAQ_PGAG7_SZ 6
+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG6_SFT 12
+#define CBR_RG_IDACAI_PGAG6_HI 17
+#define CBR_RG_IDACAI_PGAG6_SZ 6
+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG6_SFT 18
+#define CBR_RG_IDACAQ_PGAG6_HI 23
+#define CBR_RG_IDACAQ_PGAG6_SZ 6
+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG5_SFT 0
+#define CBR_RG_IDACAI_PGAG5_HI 5
+#define CBR_RG_IDACAI_PGAG5_SZ 6
+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG5_SFT 6
+#define CBR_RG_IDACAQ_PGAG5_HI 11
+#define CBR_RG_IDACAQ_PGAG5_SZ 6
+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG4_SFT 12
+#define CBR_RG_IDACAI_PGAG4_HI 17
+#define CBR_RG_IDACAI_PGAG4_SZ 6
+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG4_SFT 18
+#define CBR_RG_IDACAQ_PGAG4_HI 23
+#define CBR_RG_IDACAQ_PGAG4_SZ 6
+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG3_SFT 0
+#define CBR_RG_IDACAI_PGAG3_HI 5
+#define CBR_RG_IDACAI_PGAG3_SZ 6
+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG3_SFT 6
+#define CBR_RG_IDACAQ_PGAG3_HI 11
+#define CBR_RG_IDACAQ_PGAG3_SZ 6
+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG2_SFT 12
+#define CBR_RG_IDACAI_PGAG2_HI 17
+#define CBR_RG_IDACAI_PGAG2_SZ 6
+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG2_SFT 18
+#define CBR_RG_IDACAQ_PGAG2_HI 23
+#define CBR_RG_IDACAQ_PGAG2_SZ 6
+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG1_SFT 0
+#define CBR_RG_IDACAI_PGAG1_HI 5
+#define CBR_RG_IDACAI_PGAG1_SZ 6
+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG1_SFT 6
+#define CBR_RG_IDACAQ_PGAG1_HI 11
+#define CBR_RG_IDACAQ_PGAG1_SZ 6
+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG0_SFT 12
+#define CBR_RG_IDACAI_PGAG0_HI 17
+#define CBR_RG_IDACAI_PGAG0_SZ 6
+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG0_SFT 18
+#define CBR_RG_IDACAQ_PGAG0_HI 23
+#define CBR_RG_IDACAQ_PGAG0_SZ 6
+#define CBR_RG_EN_RCAL_MSK 0x00000001
+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_RCAL_SFT 0
+#define CBR_RG_EN_RCAL_HI 0
+#define CBR_RG_EN_RCAL_SZ 1
+#define CBR_RG_RCAL_SPD_MSK 0x00000002
+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
+#define CBR_RG_RCAL_SPD_SFT 1
+#define CBR_RG_RCAL_SPD_HI 1
+#define CBR_RG_RCAL_SPD_SZ 1
+#define CBR_RG_RCAL_TMR_MSK 0x000001fc
+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
+#define CBR_RG_RCAL_TMR_SFT 2
+#define CBR_RG_RCAL_TMR_HI 8
+#define CBR_RG_RCAL_TMR_SZ 7
+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define CBR_RG_RCAL_CODE_CWR_SFT 9
+#define CBR_RG_RCAL_CODE_CWR_HI 9
+#define CBR_RG_RCAL_CODE_CWR_SZ 1
+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define CBR_RG_RCAL_CODE_CWD_SFT 10
+#define CBR_RG_RCAL_CODE_CWD_HI 14
+#define CBR_RG_RCAL_CODE_CWD_SZ 5
+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
+#define CBR_RG_SX_SUB_SEL_CWR_HI 0
+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
+#define CBR_RG_SX_SUB_SEL_CWD_HI 7
+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
+#define CBR_RCAL_RDY_MSK 0x00000001
+#define CBR_RCAL_RDY_I_MSK 0xfffffffe
+#define CBR_RCAL_RDY_SFT 0
+#define CBR_RCAL_RDY_HI 0
+#define CBR_RCAL_RDY_SZ 1
+#define CBR_DA_LCK_RDY_MSK 0x00000002
+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
+#define CBR_DA_LCK_RDY_SFT 1
+#define CBR_DA_LCK_RDY_HI 1
+#define CBR_DA_LCK_RDY_SZ 1
+#define CBR_VT_MON_RDY_MSK 0x00000004
+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
+#define CBR_VT_MON_RDY_SFT 2
+#define CBR_VT_MON_RDY_HI 2
+#define CBR_VT_MON_RDY_SZ 1
+#define CBR_DP_VT_MON_RDY_MSK 0x00000008
+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
+#define CBR_DP_VT_MON_RDY_SFT 3
+#define CBR_DP_VT_MON_RDY_HI 3
+#define CBR_DP_VT_MON_RDY_SZ 1
+#define CBR_CH_RDY_MSK 0x00000010
+#define CBR_CH_RDY_I_MSK 0xffffffef
+#define CBR_CH_RDY_SFT 4
+#define CBR_CH_RDY_HI 4
+#define CBR_CH_RDY_SZ 1
+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define CBR_DA_R_CODE_LUT_SFT 6
+#define CBR_DA_R_CODE_LUT_HI 10
+#define CBR_DA_R_CODE_LUT_SZ 5
+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define CBR_AD_SX_VT_MON_Q_SFT 11
+#define CBR_AD_SX_VT_MON_Q_HI 12
+#define CBR_AD_SX_VT_MON_Q_SZ 2
+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define CBR_AD_DP_VT_MON_Q_SFT 13
+#define CBR_AD_DP_VT_MON_Q_HI 14
+#define CBR_AD_DP_VT_MON_Q_SZ 2
+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define CBR_DA_R_CAL_CODE_SFT 0
+#define CBR_DA_R_CAL_CODE_HI 4
+#define CBR_DA_R_CAL_CODE_SZ 5
+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define CBR_DA_SX_SUB_SEL_SFT 5
+#define CBR_DA_SX_SUB_SEL_HI 11
+#define CBR_DA_SX_SUB_SEL_SZ 7
+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
+#define CBR_DA_DP_BBPLL_BS_SFT 12
+#define CBR_DA_DP_BBPLL_BS_HI 17
+#define CBR_DA_DP_BBPLL_BS_SZ 6
+#define CBR_TX_EN_MSK 0x00000001
+#define CBR_TX_EN_I_MSK 0xfffffffe
+#define CBR_TX_EN_SFT 0
+#define CBR_TX_EN_HI 0
+#define CBR_TX_EN_SZ 1
+#define CBR_TX_CNT_RST_MSK 0x00000002
+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
+#define CBR_TX_CNT_RST_SFT 1
+#define CBR_TX_CNT_RST_HI 1
+#define CBR_TX_CNT_RST_SZ 1
+#define CBR_IFS_TIME_MSK 0x000000fc
+#define CBR_IFS_TIME_I_MSK 0xffffff03
+#define CBR_IFS_TIME_SFT 2
+#define CBR_IFS_TIME_HI 7
+#define CBR_IFS_TIME_SZ 6
+#define CBR_LENGTH_TARGET_MSK 0x000fff00
+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
+#define CBR_LENGTH_TARGET_SFT 8
+#define CBR_LENGTH_TARGET_HI 19
+#define CBR_LENGTH_TARGET_SZ 12
+#define CBR_TX_CNT_TARGET_MSK 0xff000000
+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
+#define CBR_TX_CNT_TARGET_SFT 24
+#define CBR_TX_CNT_TARGET_HI 31
+#define CBR_TX_CNT_TARGET_SZ 8
+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
+#define CBR_TC_CNT_TARGET_SFT 0
+#define CBR_TC_CNT_TARGET_HI 23
+#define CBR_TC_CNT_TARGET_SZ 24
+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
+#define CBR_PLCP_PSDU_DATA_MEM_HI 7
+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
+#define CBR_PLCP_BYTE_LENGTH_SFT 9
+#define CBR_PLCP_BYTE_LENGTH_HI 20
+#define CBR_PLCP_BYTE_LENGTH_SZ 12
+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
+#define CBR_PLCP_PSDU_RATE_SFT 21
+#define CBR_PLCP_PSDU_RATE_HI 22
+#define CBR_PLCP_PSDU_RATE_SZ 2
+#define CBR_TAIL_TIME_MSK 0x1f800000
+#define CBR_TAIL_TIME_I_MSK 0xe07fffff
+#define CBR_TAIL_TIME_SFT 23
+#define CBR_TAIL_TIME_HI 28
+#define CBR_TAIL_TIME_SZ 6
+#define CBR_RG_O_PAD_PD_MSK 0x00000001
+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
+#define CBR_RG_O_PAD_PD_SFT 0
+#define CBR_RG_O_PAD_PD_HI 0
+#define CBR_RG_O_PAD_PD_SZ 1
+#define CBR_RG_I_PAD_PD_MSK 0x00000002
+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
+#define CBR_RG_I_PAD_PD_SFT 1
+#define CBR_RG_I_PAD_PD_HI 1
+#define CBR_RG_I_PAD_PD_SZ 1
+#define CBR_SEL_ADCKP_INV_MSK 0x00000004
+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
+#define CBR_SEL_ADCKP_INV_SFT 2
+#define CBR_SEL_ADCKP_INV_HI 2
+#define CBR_SEL_ADCKP_INV_SZ 1
+#define CBR_RG_PAD_DS_MSK 0x00000008
+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
+#define CBR_RG_PAD_DS_SFT 3
+#define CBR_RG_PAD_DS_HI 3
+#define CBR_RG_PAD_DS_SZ 1
+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
+#define CBR_SEL_ADCKP_MUX_SFT 4
+#define CBR_SEL_ADCKP_MUX_HI 4
+#define CBR_SEL_ADCKP_MUX_SZ 1
+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
+#define CBR_RG_PAD_DS_CLK_SFT 5
+#define CBR_RG_PAD_DS_CLK_HI 5
+#define CBR_RG_PAD_DS_CLK_SZ 1
+#define CBR_INTP_SEL_MSK 0x00000200
+#define CBR_INTP_SEL_I_MSK 0xfffffdff
+#define CBR_INTP_SEL_SFT 9
+#define CBR_INTP_SEL_HI 9
+#define CBR_INTP_SEL_SZ 1
+#define CBR_IQ_SWP_MSK 0x00000400
+#define CBR_IQ_SWP_I_MSK 0xfffffbff
+#define CBR_IQ_SWP_SFT 10
+#define CBR_IQ_SWP_HI 10
+#define CBR_IQ_SWP_SZ 1
+#define CBR_RG_EN_EXT_DA_MSK 0x00000800
+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
+#define CBR_RG_EN_EXT_DA_SFT 11
+#define CBR_RG_EN_EXT_DA_HI 11
+#define CBR_RG_EN_EXT_DA_SZ 1
+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
+#define CBR_RG_DIS_DA_OFFSET_SFT 12
+#define CBR_RG_DIS_DA_OFFSET_HI 12
+#define CBR_RG_DIS_DA_OFFSET_SZ 1
+#define CBR_DBG_SEL_MSK 0x000f0000
+#define CBR_DBG_SEL_I_MSK 0xfff0ffff
+#define CBR_DBG_SEL_SFT 16
+#define CBR_DBG_SEL_HI 19
+#define CBR_DBG_SEL_SZ 4
+#define CBR_DBG_EN_MSK 0x00100000
+#define CBR_DBG_EN_I_MSK 0xffefffff
+#define CBR_DBG_EN_SFT 20
+#define CBR_DBG_EN_HI 20
+#define CBR_DBG_EN_SZ 1
+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
+#define CBR_RG_PKT_GEN_TX_CNT_HI 31
+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
+#define CBR_TP_SEL_MSK 0x0000001f
+#define CBR_TP_SEL_I_MSK 0xffffffe0
+#define CBR_TP_SEL_SFT 0
+#define CBR_TP_SEL_HI 4
+#define CBR_TP_SEL_SZ 5
+#define CBR_IDEAL_IQ_EN_MSK 0x00000020
+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
+#define CBR_IDEAL_IQ_EN_SFT 5
+#define CBR_IDEAL_IQ_EN_HI 5
+#define CBR_IDEAL_IQ_EN_SZ 1
+#define CBR_DATA_OUT_SEL_MSK 0x000001c0
+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
+#define CBR_DATA_OUT_SEL_SFT 6
+#define CBR_DATA_OUT_SEL_HI 8
+#define CBR_DATA_OUT_SEL_SZ 3
+#define CBR_TWO_TONE_EN_MSK 0x00000200
+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
+#define CBR_TWO_TONE_EN_SFT 9
+#define CBR_TWO_TONE_EN_HI 9
+#define CBR_TWO_TONE_EN_SZ 1
+#define CBR_FREQ_SEL_MSK 0x00ff0000
+#define CBR_FREQ_SEL_I_MSK 0xff00ffff
+#define CBR_FREQ_SEL_SFT 16
+#define CBR_FREQ_SEL_HI 23
+#define CBR_FREQ_SEL_SZ 8
+#define CBR_IQ_SCALE_MSK 0xff000000
+#define CBR_IQ_SCALE_I_MSK 0x00ffffff
+#define CBR_IQ_SCALE_SFT 24
+#define CBR_IQ_SCALE_HI 31
+#define CBR_IQ_SCALE_SZ 8
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000600
+#define FF13_CNT_I_MSK 0xfffff9ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 10
+#define FF13_CNT_SZ 2
+#define FF14_CNT_MSK 0x00001800
+#define FF14_CNT_I_MSK 0xffffe7ff
+#define FF14_CNT_SFT 11
+#define FF14_CNT_HI 12
+#define FF14_CNT_SZ 2
+#define FF15_CNT_MSK 0x00006000
+#define FF15_CNT_I_MSK 0xffff9fff
+#define FF15_CNT_SFT 13
+#define FF15_CNT_HI 14
+#define FF15_CNT_SZ 2
+#define FF4_CNT_MSK 0x000f8000
+#define FF4_CNT_I_MSK 0xfff07fff
+#define FF4_CNT_SFT 15
+#define FF4_CNT_HI 19
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x00700000
+#define FF2_CNT_I_MSK 0xff8fffff
+#define FF2_CNT_SFT 20
+#define FF2_CNT_HI 22
+#define FF2_CNT_SZ 3
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_MSK 0x00000004
+#define CH2_FULL_I_MSK 0xfffffffb
+#define CH2_FULL_SFT 2
+#define CH2_FULL_HI 2
+#define CH2_FULL_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HALT_CH0_MSK 0x00000001
+#define HALT_CH0_I_MSK 0xfffffffe
+#define HALT_CH0_SFT 0
+#define HALT_CH0_HI 0
+#define HALT_CH0_SZ 1
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH2_MSK 0x00000004
+#define HALT_CH2_I_MSK 0xfffffffb
+#define HALT_CH2_SFT 2
+#define HALT_CH2_HI 2
+#define HALT_CH2_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define HALT_CH15_MSK 0x00008000
+#define HALT_CH15_I_MSK 0xffff7fff
+#define HALT_CH15_SFT 15
+#define HALT_CH15_HI 15
+#define HALT_CH15_SZ 1
+#define STOP_MBOX_MSK 0x00010000
+#define STOP_MBOX_I_MSK 0xfffeffff
+#define STOP_MBOX_SFT 16
+#define STOP_MBOX_HI 16
+#define STOP_MBOX_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define CH0_QUEUE_FLUSH_MSK 0x00000001
+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
+#define CH0_QUEUE_FLUSH_SFT 0
+#define CH0_QUEUE_FLUSH_HI 0
+#define CH0_QUEUE_FLUSH_SZ 1
+#define CH1_QUEUE_FLUSH_MSK 0x00000002
+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
+#define CH1_QUEUE_FLUSH_SFT 1
+#define CH1_QUEUE_FLUSH_HI 1
+#define CH1_QUEUE_FLUSH_SZ 1
+#define CH2_QUEUE_FLUSH_MSK 0x00000004
+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
+#define CH2_QUEUE_FLUSH_SFT 2
+#define CH2_QUEUE_FLUSH_HI 2
+#define CH2_QUEUE_FLUSH_SZ 1
+#define CH3_QUEUE_FLUSH_MSK 0x00000008
+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
+#define CH3_QUEUE_FLUSH_SFT 3
+#define CH3_QUEUE_FLUSH_HI 3
+#define CH3_QUEUE_FLUSH_SZ 1
+#define CH4_QUEUE_FLUSH_MSK 0x00000010
+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
+#define CH4_QUEUE_FLUSH_SFT 4
+#define CH4_QUEUE_FLUSH_HI 4
+#define CH4_QUEUE_FLUSH_SZ 1
+#define CH5_QUEUE_FLUSH_MSK 0x00000020
+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
+#define CH5_QUEUE_FLUSH_SFT 5
+#define CH5_QUEUE_FLUSH_HI 5
+#define CH5_QUEUE_FLUSH_SZ 1
+#define CH6_QUEUE_FLUSH_MSK 0x00000040
+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
+#define CH6_QUEUE_FLUSH_SFT 6
+#define CH6_QUEUE_FLUSH_HI 6
+#define CH6_QUEUE_FLUSH_SZ 1
+#define CH7_QUEUE_FLUSH_MSK 0x00000080
+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
+#define CH7_QUEUE_FLUSH_SFT 7
+#define CH7_QUEUE_FLUSH_HI 7
+#define CH7_QUEUE_FLUSH_SZ 1
+#define CH8_QUEUE_FLUSH_MSK 0x00000100
+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
+#define CH8_QUEUE_FLUSH_SFT 8
+#define CH8_QUEUE_FLUSH_HI 8
+#define CH8_QUEUE_FLUSH_SZ 1
+#define CH9_QUEUE_FLUSH_MSK 0x00000200
+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
+#define CH9_QUEUE_FLUSH_SFT 9
+#define CH9_QUEUE_FLUSH_HI 9
+#define CH9_QUEUE_FLUSH_SZ 1
+#define CH10_QUEUE_FLUSH_MSK 0x00000400
+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
+#define CH10_QUEUE_FLUSH_SFT 10
+#define CH10_QUEUE_FLUSH_HI 10
+#define CH10_QUEUE_FLUSH_SZ 1
+#define CH11_QUEUE_FLUSH_MSK 0x00000800
+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
+#define CH11_QUEUE_FLUSH_SFT 11
+#define CH11_QUEUE_FLUSH_HI 11
+#define CH11_QUEUE_FLUSH_SZ 1
+#define CH12_QUEUE_FLUSH_MSK 0x00001000
+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
+#define CH12_QUEUE_FLUSH_SFT 12
+#define CH12_QUEUE_FLUSH_HI 12
+#define CH12_QUEUE_FLUSH_SZ 1
+#define CH13_QUEUE_FLUSH_MSK 0x00002000
+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
+#define CH13_QUEUE_FLUSH_SFT 13
+#define CH13_QUEUE_FLUSH_HI 13
+#define CH13_QUEUE_FLUSH_SZ 1
+#define CH14_QUEUE_FLUSH_MSK 0x00004000
+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
+#define CH14_QUEUE_FLUSH_SFT 14
+#define CH14_QUEUE_FLUSH_HI 14
+#define CH14_QUEUE_FLUSH_SZ 1
+#define CH15_QUEUE_FLUSH_MSK 0x00008000
+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
+#define CH15_QUEUE_FLUSH_SFT 15
+#define CH15_QUEUE_FLUSH_HI 15
+#define CH15_QUEUE_FLUSH_SZ 1
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00000c00
+#define FFO2_CNT_I_MSK 0xfffff3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 11
+#define FFO2_CNT_SZ 2
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00000c00
+#define FFO14_CNT_I_MSK 0xfffff3ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 11
+#define FFO14_CNT_SZ 2
+#define FFO15_CNT_MSK 0x001f8000
+#define FFO15_CNT_I_MSK 0xffe07fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 20
+#define FFO15_CNT_SZ 6
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define CH0_WRFF_FLUSH_MSK 0x00000001
+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
+#define CH0_WRFF_FLUSH_SFT 0
+#define CH0_WRFF_FLUSH_HI 0
+#define CH0_WRFF_FLUSH_SZ 1
+#define CH1_WRFF_FLUSH_MSK 0x00000002
+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
+#define CH1_WRFF_FLUSH_SFT 1
+#define CH1_WRFF_FLUSH_HI 1
+#define CH1_WRFF_FLUSH_SZ 1
+#define CH2_WRFF_FLUSH_MSK 0x00000004
+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
+#define CH2_WRFF_FLUSH_SFT 2
+#define CH2_WRFF_FLUSH_HI 2
+#define CH2_WRFF_FLUSH_SZ 1
+#define CH3_WRFF_FLUSH_MSK 0x00000008
+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
+#define CH3_WRFF_FLUSH_SFT 3
+#define CH3_WRFF_FLUSH_HI 3
+#define CH3_WRFF_FLUSH_SZ 1
+#define CH4_WRFF_FLUSH_MSK 0x00000010
+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
+#define CH4_WRFF_FLUSH_SFT 4
+#define CH4_WRFF_FLUSH_HI 4
+#define CH4_WRFF_FLUSH_SZ 1
+#define CH5_WRFF_FLUSH_MSK 0x00000020
+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
+#define CH5_WRFF_FLUSH_SFT 5
+#define CH5_WRFF_FLUSH_HI 5
+#define CH5_WRFF_FLUSH_SZ 1
+#define CH6_WRFF_FLUSH_MSK 0x00000040
+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
+#define CH6_WRFF_FLUSH_SFT 6
+#define CH6_WRFF_FLUSH_HI 6
+#define CH6_WRFF_FLUSH_SZ 1
+#define CH7_WRFF_FLUSH_MSK 0x00000080
+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
+#define CH7_WRFF_FLUSH_SFT 7
+#define CH7_WRFF_FLUSH_HI 7
+#define CH7_WRFF_FLUSH_SZ 1
+#define CH8_WRFF_FLUSH_MSK 0x00000100
+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
+#define CH8_WRFF_FLUSH_SFT 8
+#define CH8_WRFF_FLUSH_HI 8
+#define CH8_WRFF_FLUSH_SZ 1
+#define CH9_WRFF_FLUSH_MSK 0x00000200
+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
+#define CH9_WRFF_FLUSH_SFT 9
+#define CH9_WRFF_FLUSH_HI 9
+#define CH9_WRFF_FLUSH_SZ 1
+#define CH10_WRFF_FLUSH_MSK 0x00000400
+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
+#define CH10_WRFF_FLUSH_SFT 10
+#define CH10_WRFF_FLUSH_HI 10
+#define CH10_WRFF_FLUSH_SZ 1
+#define CH11_WRFF_FLUSH_MSK 0x00000800
+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
+#define CH11_WRFF_FLUSH_SFT 11
+#define CH11_WRFF_FLUSH_HI 11
+#define CH11_WRFF_FLUSH_SZ 1
+#define CH12_WRFF_FLUSH_MSK 0x00001000
+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
+#define CH12_WRFF_FLUSH_SFT 12
+#define CH12_WRFF_FLUSH_HI 12
+#define CH12_WRFF_FLUSH_SZ 1
+#define CH13_WRFF_FLUSH_MSK 0x00002000
+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
+#define CH13_WRFF_FLUSH_SFT 13
+#define CH13_WRFF_FLUSH_HI 13
+#define CH13_WRFF_FLUSH_SZ 1
+#define CH14_WRFF_FLUSH_MSK 0x00004000
+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
+#define CH14_WRFF_FLUSH_SFT 14
+#define CH14_WRFF_FLUSH_HI 14
+#define CH14_WRFF_FLUSH_SZ 1
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define GPIO_STOP_EN_MSK 0x00000010
+#define GPIO_STOP_EN_I_MSK 0xffffffef
+#define GPIO_STOP_EN_SFT 4
+#define GPIO_STOP_EN_HI 4
+#define GPIO_STOP_EN_SZ 1
+#define GPIO_STOP_POL_MSK 0x00000020
+#define GPIO_STOP_POL_I_MSK 0xffffffdf
+#define GPIO_STOP_POL_SFT 5
+#define GPIO_STOP_POL_HI 5
+#define GPIO_STOP_POL_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x03e00000
+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
+#define EDCA1_FFO_CNT2_SFT 21
+#define EDCA1_FFO_CNT2_HI 25
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x3c000000
+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
+#define EDCA4_FFO_CNT2_SFT 26
+#define EDCA4_FFO_CNT2_HI 29
+#define EDCA4_FFO_CNT2_SZ 4
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_RDYACK_SEL_MSK 0x00000006
+#define RG_RDYACK_SEL_I_MSK 0xfffffff9
+#define RG_RDYACK_SEL_SFT 1
+#define RG_RDYACK_SEL_HI 2
+#define RG_RDYACK_SEL_SZ 2
+#define RG_ADEDGE_SEL_MSK 0x00000008
+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
+#define RG_ADEDGE_SEL_SFT 3
+#define RG_ADEDGE_SEL_HI 3
+#define RG_ADEDGE_SEL_SZ 1
+#define RG_SIGN_SWAP_MSK 0x00000010
+#define RG_SIGN_SWAP_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_SFT 4
+#define RG_SIGN_SWAP_HI 4
+#define RG_SIGN_SWAP_SZ 1
+#define RG_IQ_SWAP_MSK 0x00000020
+#define RG_IQ_SWAP_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_SFT 5
+#define RG_IQ_SWAP_HI 5
+#define RG_IQ_SWAP_SZ 1
+#define RG_Q_INV_MSK 0x00000040
+#define RG_Q_INV_I_MSK 0xffffffbf
+#define RG_Q_INV_SFT 6
+#define RG_Q_INV_HI 6
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x00000080
+#define RG_I_INV_I_MSK 0xffffff7f
+#define RG_I_INV_SFT 7
+#define RG_I_INV_HI 7
+#define RG_I_INV_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x00003000
+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
+#define RG_SPECTRUM_BW_SFT 12
+#define RG_SPECTRUM_BW_HI 13
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
+#define RG_SPECTRUM_FREQ_MANUAL_HI 14
+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
+#define RG_SPECTRUM_EN_MSK 0x00008000
+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
+#define RG_SPECTRUM_EN_SFT 15
+#define RG_SPECTRUM_EN_HI 15
+#define RG_SPECTRUM_EN_SZ 1
+#define RG_TXPWRLVL_SET_MSK 0x00ff0000
+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
+#define RG_TXPWRLVL_SET_SFT 16
+#define RG_TXPWRLVL_SET_HI 23
+#define RG_TXPWRLVL_SET_SZ 8
+#define RG_TXPWRLVL_SEL_MSK 0x01000000
+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
+#define RG_TXPWRLVL_SEL_SFT 24
+#define RG_TXPWRLVL_SEL_HI 24
+#define RG_TXPWRLVL_SEL_SZ 1
+#define RG_RF_BB_CLK_SEL_MSK 0x80000000
+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_RF_BB_CLK_SEL_SFT 31
+#define RG_RF_BB_CLK_SEL_HI 31
+#define RG_RF_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
+#define RG_FFT_MEM_CLK_EN_RX_SFT 14
+#define RG_FFT_MEM_CLK_EN_RX_HI 14
+#define RG_FFT_MEM_CLK_EN_RX_SZ 1
+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
+#define RG_FFT_MEM_CLK_EN_TX_SFT 15
+#define RG_FFT_MEM_CLK_EN_TX_HI 15
+#define RG_FFT_MEM_CLK_EN_TX_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
+#define RG_SPECTRUM_FREQ_SFT 20
+#define RG_SPECTRUM_FREQ_HI 29
+#define RG_SPECTRUM_FREQ_SZ 10
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x0000ff00
+#define RG_TXPWRLVL_I_MSK 0xffff00ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 15
+#define RG_TXPWRLVL_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_FFT_IFFT_MODE_MSK 0x000000c0
+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
+#define RG_FFT_IFFT_MODE_SFT 6
+#define RG_FFT_IFFT_MODE_HI 7
+#define RG_FFT_IFFT_MODE_SZ 2
+#define RG_DAC_DBG_MODE_MSK 0x00000100
+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
+#define RG_DAC_DBG_MODE_SFT 8
+#define RG_DAC_DBG_MODE_HI 8
+#define RG_DAC_DBG_MODE_SZ 1
+#define RG_DAC_SGN_SWAP_MSK 0x00000200
+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
+#define RG_DAC_SGN_SWAP_SFT 9
+#define RG_DAC_SGN_SWAP_HI 9
+#define RG_DAC_SGN_SWAP_SZ 1
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_UP8X_MSK 0x00ff0000
+#define RG_UP8X_I_MSK 0xff00ffff
+#define RG_UP8X_SFT 16
+#define RG_UP8X_HI 23
+#define RG_UP8X_SZ 8
+#define RG_IQ_DC_BYP_MSK 0x01000000
+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
+#define RG_IQ_DC_BYP_SFT 24
+#define RG_IQ_DC_BYP_HI 24
+#define RG_IQ_DC_BYP_SZ 1
+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
+#define RG_IQ_DC_LEAKY_FACTOR_HI 29
+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
+#define RG_DAC_DCEN_MSK 0x00000001
+#define RG_DAC_DCEN_I_MSK 0xfffffffe
+#define RG_DAC_DCEN_SFT 0
+#define RG_DAC_DCEN_HI 0
+#define RG_DAC_DCEN_SZ 1
+#define RG_DAC_DCQ_MSK 0x00003ff0
+#define RG_DAC_DCQ_I_MSK 0xffffc00f
+#define RG_DAC_DCQ_SFT 4
+#define RG_DAC_DCQ_HI 13
+#define RG_DAC_DCQ_SZ 10
+#define RG_DAC_DCI_MSK 0x03ff0000
+#define RG_DAC_DCI_I_MSK 0xfc00ffff
+#define RG_DAC_DCI_SFT 16
+#define RG_DAC_DCI_HI 25
+#define RG_DAC_DCI_SZ 10
+#define RG_PGA_REFDB_SAT_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_SFT 0
+#define RG_PGA_REFDB_SAT_HI 6
+#define RG_PGA_REFDB_SAT_SZ 7
+#define RG_PGA_REFDB_TOP_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_SFT 8
+#define RG_PGA_REFDB_TOP_HI 14
+#define RG_PGA_REFDB_TOP_SZ 7
+#define RG_PGA_REF_UND_MSK 0x03ff0000
+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_SFT 16
+#define RG_PGA_REF_UND_HI 25
+#define RG_PGA_REF_UND_SZ 10
+#define RG_RF_REF_SAT_MSK 0xf0000000
+#define RG_RF_REF_SAT_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_SFT 28
+#define RG_RF_REF_SAT_HI 31
+#define RG_RF_REF_SAT_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
+#define RG_WR_RFGC_INIT_SET_SFT 21
+#define RG_WR_RFGC_INIT_SET_HI 22
+#define RG_WR_RFGC_INIT_SET_SZ 2
+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
+#define RG_WR_RFGC_INIT_EN_SFT 23
+#define RG_WR_RFGC_INIT_EN_HI 23
+#define RG_WR_RFGC_INIT_EN_SZ 1
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
+#define RG_WR_ACI_GAIN_SEL_11B_HI 15
+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_WR_ACI_GAIN_OW_11B_SFT 31
+#define RG_WR_ACI_GAIN_OW_11B_HI 31
+#define RG_WR_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HI 31
+#define RG_ACI_GAIN_OW_11GN_SZ 1
+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_SFT 0
+#define RO_CCA_PWR_MA_11GN_HI 6
+#define RO_CCA_PWR_MA_11GN_SZ 7
+#define RO_ED_STATE_MSK 0x00008000
+#define RO_ED_STATE_I_MSK 0xffff7fff
+#define RO_ED_STATE_SFT 15
+#define RO_ED_STATE_HI 15
+#define RO_ED_STATE_SZ 1
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_TX_DES_RATE_MSK 0x0000001f
+#define RG_TX_DES_RATE_I_MSK 0xffffffe0
+#define RG_TX_DES_RATE_SFT 0
+#define RG_TX_DES_RATE_HI 4
+#define RG_TX_DES_RATE_SZ 5
+#define RG_TX_DES_MODE_MSK 0x00001f00
+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
+#define RG_TX_DES_MODE_SFT 8
+#define RG_TX_DES_MODE_HI 12
+#define RG_TX_DES_MODE_SZ 5
+#define RG_TX_DES_LEN_LO_MSK 0x001f0000
+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
+#define RG_TX_DES_LEN_LO_SFT 16
+#define RG_TX_DES_LEN_LO_HI 20
+#define RG_TX_DES_LEN_LO_SZ 5
+#define RG_TX_DES_LEN_UP_MSK 0x1f000000
+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
+#define RG_TX_DES_LEN_UP_SFT 24
+#define RG_TX_DES_LEN_UP_HI 28
+#define RG_TX_DES_LEN_UP_SZ 5
+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
+#define RG_TX_DES_SRVC_UP_SFT 0
+#define RG_TX_DES_SRVC_UP_HI 4
+#define RG_TX_DES_SRVC_UP_SZ 5
+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
+#define RG_TX_DES_L_LEN_LO_SFT 8
+#define RG_TX_DES_L_LEN_LO_HI 12
+#define RG_TX_DES_L_LEN_LO_SZ 5
+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
+#define RG_TX_DES_L_LEN_UP_SFT 16
+#define RG_TX_DES_L_LEN_UP_HI 20
+#define RG_TX_DES_L_LEN_UP_SZ 5
+#define RG_TX_DES_TYPE_MSK 0x1f000000
+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
+#define RG_TX_DES_TYPE_SFT 24
+#define RG_TX_DES_TYPE_HI 28
+#define RG_TX_DES_TYPE_SZ 5
+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_TX_DES_L_LEN_UP_COMB_HI 0
+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_TX_DES_TYPE_COMB_SFT 4
+#define RG_TX_DES_TYPE_COMB_HI 4
+#define RG_TX_DES_TYPE_COMB_SZ 1
+#define RG_TX_DES_RATE_COMB_MSK 0x00000100
+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_TX_DES_RATE_COMB_SFT 8
+#define RG_TX_DES_RATE_COMB_HI 8
+#define RG_TX_DES_RATE_COMB_SZ 1
+#define RG_TX_DES_MODE_COMB_MSK 0x00001000
+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_TX_DES_MODE_COMB_SFT 12
+#define RG_TX_DES_MODE_COMB_HI 12
+#define RG_TX_DES_MODE_COMB_SZ 1
+#define RG_TX_DES_PWRLVL_MSK 0x001f0000
+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
+#define RG_TX_DES_PWRLVL_SFT 16
+#define RG_TX_DES_PWRLVL_HI 20
+#define RG_TX_DES_PWRLVL_SZ 5
+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
+#define RG_TX_DES_SRVC_LO_SFT 24
+#define RG_TX_DES_SRVC_LO_HI 28
+#define RG_TX_DES_SRVC_LO_SZ 5
+#define RG_RX_DES_RATE_MSK 0x0000003f
+#define RG_RX_DES_RATE_I_MSK 0xffffffc0
+#define RG_RX_DES_RATE_SFT 0
+#define RG_RX_DES_RATE_HI 5
+#define RG_RX_DES_RATE_SZ 6
+#define RG_RX_DES_MODE_MSK 0x00003f00
+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
+#define RG_RX_DES_MODE_SFT 8
+#define RG_RX_DES_MODE_HI 13
+#define RG_RX_DES_MODE_SZ 6
+#define RG_RX_DES_LEN_LO_MSK 0x003f0000
+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
+#define RG_RX_DES_LEN_LO_SFT 16
+#define RG_RX_DES_LEN_LO_HI 21
+#define RG_RX_DES_LEN_LO_SZ 6
+#define RG_RX_DES_LEN_UP_MSK 0x3f000000
+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
+#define RG_RX_DES_LEN_UP_SFT 24
+#define RG_RX_DES_LEN_UP_HI 29
+#define RG_RX_DES_LEN_UP_SZ 6
+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
+#define RG_RX_DES_SRVC_UP_SFT 0
+#define RG_RX_DES_SRVC_UP_HI 5
+#define RG_RX_DES_SRVC_UP_SZ 6
+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
+#define RG_RX_DES_L_LEN_LO_SFT 8
+#define RG_RX_DES_L_LEN_LO_HI 13
+#define RG_RX_DES_L_LEN_LO_SZ 6
+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
+#define RG_RX_DES_L_LEN_UP_SFT 16
+#define RG_RX_DES_L_LEN_UP_HI 21
+#define RG_RX_DES_L_LEN_UP_SZ 6
+#define RG_RX_DES_TYPE_MSK 0x3f000000
+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
+#define RG_RX_DES_TYPE_SFT 24
+#define RG_RX_DES_TYPE_HI 29
+#define RG_RX_DES_TYPE_SZ 6
+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_RX_DES_L_LEN_UP_COMB_HI 0
+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_RX_DES_TYPE_COMB_SFT 4
+#define RG_RX_DES_TYPE_COMB_HI 4
+#define RG_RX_DES_TYPE_COMB_SZ 1
+#define RG_RX_DES_RATE_COMB_MSK 0x00000100
+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_RX_DES_RATE_COMB_SFT 8
+#define RG_RX_DES_RATE_COMB_HI 8
+#define RG_RX_DES_RATE_COMB_SZ 1
+#define RG_RX_DES_MODE_COMB_MSK 0x00001000
+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_RX_DES_MODE_COMB_SFT 12
+#define RG_RX_DES_MODE_COMB_HI 12
+#define RG_RX_DES_MODE_COMB_SZ 1
+#define RG_RX_DES_SNR_MSK 0x000f0000
+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
+#define RG_RX_DES_SNR_SFT 16
+#define RG_RX_DES_SNR_HI 19
+#define RG_RX_DES_SNR_SZ 4
+#define RG_RX_DES_RCPI_MSK 0x00f00000
+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
+#define RG_RX_DES_RCPI_SFT 20
+#define RG_RX_DES_RCPI_HI 23
+#define RG_RX_DES_RCPI_SZ 4
+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
+#define RG_RX_DES_SRVC_LO_SFT 24
+#define RG_RX_DES_SRVC_LO_HI 29
+#define RG_RX_DES_SRVC_LO_SZ 6
+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
+#define RO_TX_DES_EXCP_RATE_CNT_HI 7
+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
+#define RO_TX_DES_EXCP_MODE_CNT_HI 23
+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
+#define RG_TX_DES_EXCP_CLR_SFT 31
+#define RG_TX_DES_EXCP_CLR_HI 31
+#define RG_TX_DES_EXCP_CLR_SZ 1
+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
+#define RG_TX_DES_ACK_WIDTH_SFT 0
+#define RG_TX_DES_ACK_WIDTH_HI 0
+#define RG_TX_DES_ACK_WIDTH_SZ 1
+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
+#define RG_TX_DES_ACK_PRD_SFT 1
+#define RG_TX_DES_ACK_PRD_HI 3
+#define RG_TX_DES_ACK_PRD_SZ 3
+#define RG_RX_DES_SNR_GN_MSK 0x003f0000
+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
+#define RG_RX_DES_SNR_GN_SFT 16
+#define RG_RX_DES_SNR_GN_HI 21
+#define RG_RX_DES_SNR_GN_SZ 6
+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
+#define RG_RX_DES_RCPI_GN_SFT 24
+#define RG_RX_DES_RCPI_GN_HI 29
+#define RG_RX_DES_RCPI_GN_SZ 6
+#define RG_TST_TBUS_SEL_MSK 0x0000000f
+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TST_TBUS_SEL_SFT 0
+#define RG_TST_TBUS_SEL_HI 3
+#define RG_TST_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RG_TST_ADC_ON_MSK 0x40000000
+#define RG_TST_ADC_ON_I_MSK 0xbfffffff
+#define RG_TST_ADC_ON_SFT 30
+#define RG_TST_ADC_ON_HI 30
+#define RG_TST_ADC_ON_SZ 1
+#define RG_TST_EXT_GAIN_MSK 0x80000000
+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
+#define RG_TST_EXT_GAIN_SFT 31
+#define RG_TST_EXT_GAIN_HI 31
+#define RG_TST_EXT_GAIN_SZ 1
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_I_SET_MSK 0x003ff000
+#define RG_DAC_I_SET_I_MSK 0xffc00fff
+#define RG_DAC_I_SET_SFT 12
+#define RG_DAC_I_SET_HI 21
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_EN_MAN_MSK 0x10000000
+#define RG_DAC_EN_MAN_I_MSK 0xefffffff
+#define RG_DAC_EN_MAN_SFT 28
+#define RG_DAC_EN_MAN_HI 28
+#define RG_DAC_EN_MAN_SZ 1
+#define RG_IQC_FFT_EN_MSK 0x20000000
+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
+#define RG_IQC_FFT_EN_SFT 29
+#define RG_IQC_FFT_EN_HI 29
+#define RG_IQC_FFT_EN_SZ 1
+#define RG_DAC_MAN_Q_EN_MSK 0x40000000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
+#define RG_DAC_MAN_Q_EN_SFT 30
+#define RG_DAC_MAN_Q_EN_HI 30
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_MAN_I_EN_MSK 0x80000000
+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
+#define RG_DAC_MAN_I_EN_SFT 31
+#define RG_DAC_MAN_I_EN_HI 31
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_PA_RISE_TIME_MSK 0x000000ff
+#define RG_PA_RISE_TIME_I_MSK 0xffffff00
+#define RG_PA_RISE_TIME_SFT 0
+#define RG_PA_RISE_TIME_HI 7
+#define RG_PA_RISE_TIME_SZ 8
+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_RISE_TIME_SFT 8
+#define RG_RFTX_RISE_TIME_HI 15
+#define RG_RFTX_RISE_TIME_SZ 8
+#define RG_DAC_RISE_TIME_MSK 0x00ff0000
+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
+#define RG_DAC_RISE_TIME_SFT 16
+#define RG_DAC_RISE_TIME_HI 23
+#define RG_DAC_RISE_TIME_SZ 8
+#define RG_SW_RISE_TIME_MSK 0xff000000
+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
+#define RG_SW_RISE_TIME_SFT 24
+#define RG_SW_RISE_TIME_HI 31
+#define RG_SW_RISE_TIME_SZ 8
+#define RG_PA_FALL_TIME_MSK 0x000000ff
+#define RG_PA_FALL_TIME_I_MSK 0xffffff00
+#define RG_PA_FALL_TIME_SFT 0
+#define RG_PA_FALL_TIME_HI 7
+#define RG_PA_FALL_TIME_SZ 8
+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_FALL_TIME_SFT 8
+#define RG_RFTX_FALL_TIME_HI 15
+#define RG_RFTX_FALL_TIME_SZ 8
+#define RG_DAC_FALL_TIME_MSK 0x00ff0000
+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
+#define RG_DAC_FALL_TIME_SFT 16
+#define RG_DAC_FALL_TIME_HI 23
+#define RG_DAC_FALL_TIME_SZ 8
+#define RG_SW_FALL_TIME_MSK 0xff000000
+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
+#define RG_SW_FALL_TIME_SFT 24
+#define RG_SW_FALL_TIME_HI 31
+#define RG_SW_FALL_TIME_SZ 8
+#define RG_ANT_SW_0_MSK 0x00000007
+#define RG_ANT_SW_0_I_MSK 0xfffffff8
+#define RG_ANT_SW_0_SFT 0
+#define RG_ANT_SW_0_HI 2
+#define RG_ANT_SW_0_SZ 3
+#define RG_ANT_SW_1_MSK 0x00000038
+#define RG_ANT_SW_1_I_MSK 0xffffffc7
+#define RG_ANT_SW_1_SFT 3
+#define RG_ANT_SW_1_HI 5
+#define RG_ANT_SW_1_SZ 3
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 12
+#define RG_MTX_LEN_LOWER_TH_0_SZ 13
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 28
+#define RG_MTX_LEN_UPPER_TH_0_SZ 13
+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_0_SFT 31
+#define RG_MTX_LEN_CNT_EN_0_HI 31
+#define RG_MTX_LEN_CNT_EN_0_SZ 1
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 12
+#define RG_MTX_LEN_LOWER_TH_1_SZ 13
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 28
+#define RG_MTX_LEN_UPPER_TH_1_SZ 13
+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_1_SFT 31
+#define RG_MTX_LEN_CNT_EN_1_HI 31
+#define RG_MTX_LEN_CNT_EN_1_SZ 1
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 12
+#define RG_MRX_LEN_LOWER_TH_0_SZ 13
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 28
+#define RG_MRX_LEN_UPPER_TH_0_SZ 13
+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_0_SFT 31
+#define RG_MRX_LEN_CNT_EN_0_HI 31
+#define RG_MRX_LEN_CNT_EN_0_SZ 1
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 12
+#define RG_MRX_LEN_LOWER_TH_1_SZ 13
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 28
+#define RG_MRX_LEN_UPPER_TH_1_SZ 13
+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_1_SFT 31
+#define RG_MRX_LEN_CNT_EN_1_HI 31
+#define RG_MRX_LEN_CNT_EN_1_SZ 1
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MODE_REG_IN_16_MSK 0x0000ffff
+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_16_SFT 0
+#define RG_MODE_REG_IN_16_HI 15
+#define RG_MODE_REG_IN_16_SZ 16
+#define RG_PARALLEL_DR_16_MSK 0x00100000
+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_16_SFT 20
+#define RG_PARALLEL_DR_16_HI 20
+#define RG_PARALLEL_DR_16_SZ 1
+#define RG_MBRUN_16_MSK 0x01000000
+#define RG_MBRUN_16_I_MSK 0xfeffffff
+#define RG_MBRUN_16_SFT 24
+#define RG_MBRUN_16_HI 24
+#define RG_MBRUN_16_SZ 1
+#define RG_SHIFT_DR_16_MSK 0x10000000
+#define RG_SHIFT_DR_16_I_MSK 0xefffffff
+#define RG_SHIFT_DR_16_SFT 28
+#define RG_SHIFT_DR_16_HI 28
+#define RG_SHIFT_DR_16_SZ 1
+#define RG_MODE_REG_SI_16_MSK 0x20000000
+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_16_SFT 29
+#define RG_MODE_REG_SI_16_HI 29
+#define RG_MODE_REG_SI_16_SZ 1
+#define RG_SIMULATION_MODE_16_MSK 0x40000000
+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_16_SFT 30
+#define RG_SIMULATION_MODE_16_HI 30
+#define RG_SIMULATION_MODE_16_SZ 1
+#define RG_DBIST_MODE_16_MSK 0x80000000
+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_16_SFT 31
+#define RG_DBIST_MODE_16_HI 31
+#define RG_DBIST_MODE_16_SZ 1
+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_16_SFT 0
+#define RO_MODE_REG_OUT_16_HI 15
+#define RO_MODE_REG_OUT_16_SZ 16
+#define RO_MODE_REG_SO_16_MSK 0x01000000
+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_16_SFT 24
+#define RO_MODE_REG_SO_16_HI 24
+#define RO_MODE_REG_SO_16_SZ 1
+#define RO_MONITOR_BUS_16_MSK 0x0007ffff
+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_16_SFT 0
+#define RO_MONITOR_BUS_16_HI 18
+#define RO_MONITOR_BUS_16_SZ 19
+#define RG_MRX_TYPE_1_MSK 0x000000ff
+#define RG_MRX_TYPE_1_I_MSK 0xffffff00
+#define RG_MRX_TYPE_1_SFT 0
+#define RG_MRX_TYPE_1_HI 7
+#define RG_MRX_TYPE_1_SZ 8
+#define RG_MRX_TYPE_0_MSK 0x0000ff00
+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
+#define RG_MRX_TYPE_0_SFT 8
+#define RG_MRX_TYPE_0_HI 15
+#define RG_MRX_TYPE_0_SZ 8
+#define RG_MTX_TYPE_1_MSK 0x00ff0000
+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_1_SFT 16
+#define RG_MTX_TYPE_1_HI 23
+#define RG_MTX_TYPE_1_SZ 8
+#define RG_MTX_TYPE_0_MSK 0xff000000
+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
+#define RG_MTX_TYPE_0_SFT 24
+#define RG_MTX_TYPE_0_HI 31
+#define RG_MTX_TYPE_0_SZ 8
+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_1_SFT 0
+#define RO_MTX_TYPE_CNT_1_HI 15
+#define RO_MTX_TYPE_CNT_1_SZ 16
+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_0_SFT 16
+#define RO_MTX_TYPE_CNT_0_HI 31
+#define RO_MTX_TYPE_CNT_0_SZ 16
+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_1_SFT 0
+#define RO_MRX_TYPE_CNT_1_HI 15
+#define RO_MRX_TYPE_CNT_1_SZ 16
+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_0_SFT 16
+#define RO_MRX_TYPE_CNT_0_HI 31
+#define RO_MRX_TYPE_CNT_0_SZ 16
+#define RG_HB_COEF0_MSK 0x00000fff
+#define RG_HB_COEF0_I_MSK 0xfffff000
+#define RG_HB_COEF0_SFT 0
+#define RG_HB_COEF0_HI 11
+#define RG_HB_COEF0_SZ 12
+#define RG_HB_COEF1_MSK 0x0fff0000
+#define RG_HB_COEF1_I_MSK 0xf000ffff
+#define RG_HB_COEF1_SFT 16
+#define RG_HB_COEF1_HI 27
+#define RG_HB_COEF1_SZ 12
+#define RG_HB_COEF2_MSK 0x00000fff
+#define RG_HB_COEF2_I_MSK 0xfffff000
+#define RG_HB_COEF2_SFT 0
+#define RG_HB_COEF2_HI 11
+#define RG_HB_COEF2_SZ 12
+#define RG_HB_COEF3_MSK 0x0fff0000
+#define RG_HB_COEF3_I_MSK 0xf000ffff
+#define RG_HB_COEF3_SFT 16
+#define RG_HB_COEF3_HI 27
+#define RG_HB_COEF3_SZ 12
+#define RG_HB_COEF4_MSK 0x00000fff
+#define RG_HB_COEF4_I_MSK 0xfffff000
+#define RG_HB_COEF4_SFT 0
+#define RG_HB_COEF4_HI 11
+#define RG_HB_COEF4_SZ 12
+#define RO_TBUS_O_MSK 0x000fffff
+#define RO_TBUS_O_I_MSK 0xfff00000
+#define RO_TBUS_O_SFT 0
+#define RO_TBUS_O_HI 19
+#define RO_TBUS_O_SZ 20
+#define RG_LPF4_00_MSK 0x00001fff
+#define RG_LPF4_00_I_MSK 0xffffe000
+#define RG_LPF4_00_SFT 0
+#define RG_LPF4_00_HI 12
+#define RG_LPF4_00_SZ 13
+#define RG_LPF4_01_MSK 0x00001fff
+#define RG_LPF4_01_I_MSK 0xffffe000
+#define RG_LPF4_01_SFT 0
+#define RG_LPF4_01_HI 12
+#define RG_LPF4_01_SZ 13
+#define RG_LPF4_02_MSK 0x00001fff
+#define RG_LPF4_02_I_MSK 0xffffe000
+#define RG_LPF4_02_SFT 0
+#define RG_LPF4_02_HI 12
+#define RG_LPF4_02_SZ 13
+#define RG_LPF4_03_MSK 0x00001fff
+#define RG_LPF4_03_I_MSK 0xffffe000
+#define RG_LPF4_03_SFT 0
+#define RG_LPF4_03_HI 12
+#define RG_LPF4_03_SZ 13
+#define RG_LPF4_04_MSK 0x00001fff
+#define RG_LPF4_04_I_MSK 0xffffe000
+#define RG_LPF4_04_SFT 0
+#define RG_LPF4_04_HI 12
+#define RG_LPF4_04_SZ 13
+#define RG_LPF4_05_MSK 0x00001fff
+#define RG_LPF4_05_I_MSK 0xffffe000
+#define RG_LPF4_05_SFT 0
+#define RG_LPF4_05_HI 12
+#define RG_LPF4_05_SZ 13
+#define RG_LPF4_06_MSK 0x00001fff
+#define RG_LPF4_06_I_MSK 0xffffe000
+#define RG_LPF4_06_SFT 0
+#define RG_LPF4_06_HI 12
+#define RG_LPF4_06_SZ 13
+#define RG_LPF4_07_MSK 0x00001fff
+#define RG_LPF4_07_I_MSK 0xffffe000
+#define RG_LPF4_07_SFT 0
+#define RG_LPF4_07_HI 12
+#define RG_LPF4_07_SZ 13
+#define RG_LPF4_08_MSK 0x00001fff
+#define RG_LPF4_08_I_MSK 0xffffe000
+#define RG_LPF4_08_SFT 0
+#define RG_LPF4_08_HI 12
+#define RG_LPF4_08_SZ 13
+#define RG_LPF4_09_MSK 0x00001fff
+#define RG_LPF4_09_I_MSK 0xffffe000
+#define RG_LPF4_09_SFT 0
+#define RG_LPF4_09_HI 12
+#define RG_LPF4_09_SZ 13
+#define RG_LPF4_10_MSK 0x00001fff
+#define RG_LPF4_10_I_MSK 0xffffe000
+#define RG_LPF4_10_SFT 0
+#define RG_LPF4_10_HI 12
+#define RG_LPF4_10_SZ 13
+#define RG_LPF4_11_MSK 0x00001fff
+#define RG_LPF4_11_I_MSK 0xffffe000
+#define RG_LPF4_11_SFT 0
+#define RG_LPF4_11_HI 12
+#define RG_LPF4_11_SZ 13
+#define RG_LPF4_12_MSK 0x00001fff
+#define RG_LPF4_12_I_MSK 0xffffe000
+#define RG_LPF4_12_SFT 0
+#define RG_LPF4_12_HI 12
+#define RG_LPF4_12_SZ 13
+#define RG_LPF4_13_MSK 0x00001fff
+#define RG_LPF4_13_I_MSK 0xffffe000
+#define RG_LPF4_13_SFT 0
+#define RG_LPF4_13_HI 12
+#define RG_LPF4_13_SZ 13
+#define RG_LPF4_14_MSK 0x00001fff
+#define RG_LPF4_14_I_MSK 0xffffe000
+#define RG_LPF4_14_SFT 0
+#define RG_LPF4_14_HI 12
+#define RG_LPF4_14_SZ 13
+#define RG_LPF4_15_MSK 0x00001fff
+#define RG_LPF4_15_I_MSK 0xffffe000
+#define RG_LPF4_15_SFT 0
+#define RG_LPF4_15_HI 12
+#define RG_LPF4_15_SZ 13
+#define RG_LPF4_16_MSK 0x00001fff
+#define RG_LPF4_16_I_MSK 0xffffe000
+#define RG_LPF4_16_SFT 0
+#define RG_LPF4_16_HI 12
+#define RG_LPF4_16_SZ 13
+#define RG_LPF4_17_MSK 0x00001fff
+#define RG_LPF4_17_I_MSK 0xffffe000
+#define RG_LPF4_17_SFT 0
+#define RG_LPF4_17_HI 12
+#define RG_LPF4_17_SZ 13
+#define RG_LPF4_18_MSK 0x00001fff
+#define RG_LPF4_18_I_MSK 0xffffe000
+#define RG_LPF4_18_SFT 0
+#define RG_LPF4_18_HI 12
+#define RG_LPF4_18_SZ 13
+#define RG_LPF4_19_MSK 0x00001fff
+#define RG_LPF4_19_I_MSK 0xffffe000
+#define RG_LPF4_19_SFT 0
+#define RG_LPF4_19_HI 12
+#define RG_LPF4_19_SZ 13
+#define RG_LPF4_20_MSK 0x00001fff
+#define RG_LPF4_20_I_MSK 0xffffe000
+#define RG_LPF4_20_SFT 0
+#define RG_LPF4_20_HI 12
+#define RG_LPF4_20_SZ 13
+#define RG_LPF4_21_MSK 0x00001fff
+#define RG_LPF4_21_I_MSK 0xffffe000
+#define RG_LPF4_21_SFT 0
+#define RG_LPF4_21_HI 12
+#define RG_LPF4_21_SZ 13
+#define RG_LPF4_22_MSK 0x00001fff
+#define RG_LPF4_22_I_MSK 0xffffe000
+#define RG_LPF4_22_SFT 0
+#define RG_LPF4_22_HI 12
+#define RG_LPF4_22_SZ 13
+#define RG_LPF4_23_MSK 0x00001fff
+#define RG_LPF4_23_I_MSK 0xffffe000
+#define RG_LPF4_23_SFT 0
+#define RG_LPF4_23_HI 12
+#define RG_LPF4_23_SZ 13
+#define RG_LPF4_24_MSK 0x00001fff
+#define RG_LPF4_24_I_MSK 0xffffe000
+#define RG_LPF4_24_SFT 0
+#define RG_LPF4_24_HI 12
+#define RG_LPF4_24_SZ 13
+#define RG_LPF4_25_MSK 0x00001fff
+#define RG_LPF4_25_I_MSK 0xffffe000
+#define RG_LPF4_25_SFT 0
+#define RG_LPF4_25_HI 12
+#define RG_LPF4_25_SZ 13
+#define RG_LPF4_26_MSK 0x00001fff
+#define RG_LPF4_26_I_MSK 0xffffe000
+#define RG_LPF4_26_SFT 0
+#define RG_LPF4_26_HI 12
+#define RG_LPF4_26_SZ 13
+#define RG_LPF4_27_MSK 0x00001fff
+#define RG_LPF4_27_I_MSK 0xffffe000
+#define RG_LPF4_27_SFT 0
+#define RG_LPF4_27_HI 12
+#define RG_LPF4_27_SZ 13
+#define RG_LPF4_28_MSK 0x00001fff
+#define RG_LPF4_28_I_MSK 0xffffe000
+#define RG_LPF4_28_SFT 0
+#define RG_LPF4_28_HI 12
+#define RG_LPF4_28_SZ 13
+#define RG_LPF4_29_MSK 0x00001fff
+#define RG_LPF4_29_I_MSK 0xffffe000
+#define RG_LPF4_29_SFT 0
+#define RG_LPF4_29_HI 12
+#define RG_LPF4_29_SZ 13
+#define RG_LPF4_30_MSK 0x00001fff
+#define RG_LPF4_30_I_MSK 0xffffe000
+#define RG_LPF4_30_SFT 0
+#define RG_LPF4_30_HI 12
+#define RG_LPF4_30_SZ 13
+#define RG_LPF4_31_MSK 0x00001fff
+#define RG_LPF4_31_I_MSK 0xffffe000
+#define RG_LPF4_31_SFT 0
+#define RG_LPF4_31_HI 12
+#define RG_LPF4_31_SZ 13
+#define RG_LPF4_32_MSK 0x00001fff
+#define RG_LPF4_32_I_MSK 0xffffe000
+#define RG_LPF4_32_SFT 0
+#define RG_LPF4_32_HI 12
+#define RG_LPF4_32_SZ 13
+#define RG_LPF4_33_MSK 0x00001fff
+#define RG_LPF4_33_I_MSK 0xffffe000
+#define RG_LPF4_33_SFT 0
+#define RG_LPF4_33_HI 12
+#define RG_LPF4_33_SZ 13
+#define RG_LPF4_34_MSK 0x00001fff
+#define RG_LPF4_34_I_MSK 0xffffe000
+#define RG_LPF4_34_SFT 0
+#define RG_LPF4_34_HI 12
+#define RG_LPF4_34_SZ 13
+#define RG_LPF4_35_MSK 0x00001fff
+#define RG_LPF4_35_I_MSK 0xffffe000
+#define RG_LPF4_35_SFT 0
+#define RG_LPF4_35_HI 12
+#define RG_LPF4_35_SZ 13
+#define RG_LPF4_36_MSK 0x00001fff
+#define RG_LPF4_36_I_MSK 0xffffe000
+#define RG_LPF4_36_SFT 0
+#define RG_LPF4_36_HI 12
+#define RG_LPF4_36_SZ 13
+#define RG_LPF4_37_MSK 0x00001fff
+#define RG_LPF4_37_I_MSK 0xffffe000
+#define RG_LPF4_37_SFT 0
+#define RG_LPF4_37_HI 12
+#define RG_LPF4_37_SZ 13
+#define RG_LPF4_38_MSK 0x00001fff
+#define RG_LPF4_38_I_MSK 0xffffe000
+#define RG_LPF4_38_SFT 0
+#define RG_LPF4_38_HI 12
+#define RG_LPF4_38_SZ 13
+#define RG_LPF4_39_MSK 0x00001fff
+#define RG_LPF4_39_I_MSK 0xffffe000
+#define RG_LPF4_39_SFT 0
+#define RG_LPF4_39_HI 12
+#define RG_LPF4_39_SZ 13
+#define RG_LPF4_40_MSK 0x00001fff
+#define RG_LPF4_40_I_MSK 0xffffe000
+#define RG_LPF4_40_SFT 0
+#define RG_LPF4_40_HI 12
+#define RG_LPF4_40_SZ 13
+#define RG_BP_SMB_MSK 0x00002000
+#define RG_BP_SMB_I_MSK 0xffffdfff
+#define RG_BP_SMB_SFT 13
+#define RG_BP_SMB_HI 13
+#define RG_BP_SMB_SZ 1
+#define RG_EN_SRVC_MSK 0x00004000
+#define RG_EN_SRVC_I_MSK 0xffffbfff
+#define RG_EN_SRVC_SFT 14
+#define RG_EN_SRVC_HI 14
+#define RG_EN_SRVC_SZ 1
+#define RG_DES_SPD_MSK 0x00030000
+#define RG_DES_SPD_I_MSK 0xfffcffff
+#define RG_DES_SPD_SFT 16
+#define RG_DES_SPD_HI 17
+#define RG_DES_SPD_SZ 2
+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11B_RISE_TIME_SFT 0
+#define RG_BB_11B_RISE_TIME_HI 7
+#define RG_BB_11B_RISE_TIME_SZ 8
+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11B_FALL_TIME_SFT 8
+#define RG_BB_11B_FALL_TIME_HI 15
+#define RG_BB_11B_FALL_TIME_SZ 8
+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
+#define RG_WR_TX_EN_CNT_RST_N_SFT 0
+#define RG_WR_TX_EN_CNT_RST_N_HI 0
+#define RG_WR_TX_EN_CNT_RST_N_SZ 1
+#define RO_TX_EN_CNT_MSK 0x0000ffff
+#define RO_TX_EN_CNT_I_MSK 0xffff0000
+#define RO_TX_EN_CNT_SFT 0
+#define RO_TX_EN_CNT_HI 15
+#define RO_TX_EN_CNT_SZ 16
+#define RO_TX_CNT_MSK 0xffffffff
+#define RO_TX_CNT_I_MSK 0x00000000
+#define RO_TX_CNT_SFT 0
+#define RO_TX_CNT_HI 31
+#define RO_TX_CNT_SZ 32
+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11B_L_EXT_SFT 0
+#define RG_POS_DES_11B_L_EXT_HI 3
+#define RG_POS_DES_11B_L_EXT_SZ 4
+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11B_DLY_SFT 4
+#define RG_PRE_DES_11B_DLY_HI 7
+#define RG_PRE_DES_11B_DLY_SZ 4
+#define RG_CNT_CCA_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_LMT_SFT 16
+#define RG_CNT_CCA_LMT_HI 19
+#define RG_CNT_CCA_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_BYPASS_AGC_MSK 0x80000000
+#define RG_BYPASS_AGC_I_MSK 0x7fffffff
+#define RG_BYPASS_AGC_SFT 31
+#define RG_BYPASS_AGC_HI 31
+#define RG_BYPASS_AGC_SZ 1
+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
+#define RG_CCA_BIT_CNT_LMT_RX_HI 7
+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
+#define RG_CE_T4_CNT_LMT_SFT 8
+#define RG_CE_T4_CNT_LMT_HI 15
+#define RG_CE_T4_CNT_LMT_SZ 8
+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
+#define RG_CE_T3_CNT_LMT_SFT 16
+#define RG_CE_T3_CNT_LMT_HI 23
+#define RG_CE_T3_CNT_LMT_SZ 8
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T8_MSK 0x00000007
+#define RG_CE_MU_T8_I_MSK 0xfffffff8
+#define RG_CE_MU_T8_SFT 0
+#define RG_CE_MU_T8_HI 2
+#define RG_CE_MU_T8_SZ 3
+#define RG_CE_MU_T7_MSK 0x00000070
+#define RG_CE_MU_T7_I_MSK 0xffffff8f
+#define RG_CE_MU_T7_SFT 4
+#define RG_CE_MU_T7_HI 6
+#define RG_CE_MU_T7_SZ 3
+#define RG_CE_MU_T6_MSK 0x00000700
+#define RG_CE_MU_T6_I_MSK 0xfffff8ff
+#define RG_CE_MU_T6_SFT 8
+#define RG_CE_MU_T6_HI 10
+#define RG_CE_MU_T6_SZ 3
+#define RG_CE_MU_T5_MSK 0x00007000
+#define RG_CE_MU_T5_I_MSK 0xffff8fff
+#define RG_CE_MU_T5_SFT 12
+#define RG_CE_MU_T5_HI 14
+#define RG_CE_MU_T5_SZ 3
+#define RG_CE_MU_T4_MSK 0x00070000
+#define RG_CE_MU_T4_I_MSK 0xfff8ffff
+#define RG_CE_MU_T4_SFT 16
+#define RG_CE_MU_T4_HI 18
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00700000
+#define RG_CE_MU_T3_I_MSK 0xff8fffff
+#define RG_CE_MU_T3_SFT 20
+#define RG_CE_MU_T3_HI 22
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_SFT 0
+#define RG_PWRON_DLY_TH_11B_HI 7
+#define RG_PWRON_DLY_TH_11B_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
+#define RG_CCA_PWR_TH_RX_SFT 0
+#define RG_CCA_PWR_TH_RX_HI 14
+#define RG_CCA_PWR_TH_RX_SZ 15
+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_CCA_PWR_CNT_TH_SFT 16
+#define RG_CCA_PWR_CNT_TH_HI 20
+#define RG_CCA_PWR_CNT_TH_SZ 5
+#define B_FREQ_OS_MSK 0x000007ff
+#define B_FREQ_OS_I_MSK 0xfffff800
+#define B_FREQ_OS_SFT 0
+#define B_FREQ_OS_HI 10
+#define B_FREQ_OS_SZ 11
+#define B_SNR_MSK 0x0000007f
+#define B_SNR_I_MSK 0xffffff80
+#define B_SNR_SFT 0
+#define B_SNR_HI 6
+#define B_SNR_SZ 7
+#define B_RCPI_MSK 0x007f0000
+#define B_RCPI_I_MSK 0xff80ffff
+#define B_RCPI_SFT 16
+#define B_RCPI_HI 22
+#define B_RCPI_SZ 7
+#define CRC_CNT_MSK 0x0000ffff
+#define CRC_CNT_I_MSK 0xffff0000
+#define CRC_CNT_SFT 0
+#define CRC_CNT_HI 15
+#define CRC_CNT_SZ 16
+#define SFD_CNT_MSK 0xffff0000
+#define SFD_CNT_I_MSK 0x0000ffff
+#define SFD_CNT_SFT 16
+#define SFD_CNT_HI 31
+#define SFD_CNT_SZ 16
+#define B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define B_PACKET_ERR_CNT_SFT 0
+#define B_PACKET_ERR_CNT_HI 15
+#define B_PACKET_ERR_CNT_SZ 16
+#define PACKET_ERR_MSK 0x00010000
+#define PACKET_ERR_I_MSK 0xfffeffff
+#define PACKET_ERR_SFT 16
+#define PACKET_ERR_HI 16
+#define PACKET_ERR_SZ 1
+#define B_PACKET_CNT_MSK 0x0000ffff
+#define B_PACKET_CNT_I_MSK 0xffff0000
+#define B_PACKET_CNT_SFT 0
+#define B_PACKET_CNT_HI 15
+#define B_PACKET_CNT_SZ 16
+#define B_CCA_CNT_MSK 0xffff0000
+#define B_CCA_CNT_I_MSK 0x0000ffff
+#define B_CCA_CNT_SFT 16
+#define B_CCA_CNT_HI 31
+#define B_CCA_CNT_SZ 16
+#define B_LENGTH_FIELD_MSK 0x0000ffff
+#define B_LENGTH_FIELD_I_MSK 0xffff0000
+#define B_LENGTH_FIELD_SFT 0
+#define B_LENGTH_FIELD_HI 15
+#define B_LENGTH_FIELD_SZ 16
+#define SFD_FIELD_MSK 0xffff0000
+#define SFD_FIELD_I_MSK 0x0000ffff
+#define SFD_FIELD_SFT 16
+#define SFD_FIELD_HI 31
+#define SFD_FIELD_SZ 16
+#define SIGNAL_FIELD_MSK 0x000000ff
+#define SIGNAL_FIELD_I_MSK 0xffffff00
+#define SIGNAL_FIELD_SFT 0
+#define SIGNAL_FIELD_HI 7
+#define SIGNAL_FIELD_SZ 8
+#define B_SERVICE_FIELD_MSK 0x0000ff00
+#define B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define B_SERVICE_FIELD_SFT 8
+#define B_SERVICE_FIELD_HI 15
+#define B_SERVICE_FIELD_SZ 8
+#define CRC_CORRECT_MSK 0x00010000
+#define CRC_CORRECT_I_MSK 0xfffeffff
+#define CRC_CORRECT_SFT 16
+#define CRC_CORRECT_HI 16
+#define CRC_CORRECT_SZ 1
+#define DEBUG_SEL_MSK 0x0000000f
+#define DEBUG_SEL_I_MSK 0xfffffff0
+#define DEBUG_SEL_SFT 0
+#define DEBUG_SEL_HI 3
+#define DEBUG_SEL_SZ 4
+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_SFT 20
+#define RG_PACKET_STAT_EN_11B_HI 20
+#define RG_PACKET_STAT_EN_11B_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11B_SOFT_RST_N_SFT 0
+#define RX_PHY_11B_SOFT_RST_N_HI 0
+#define RX_PHY_11B_SOFT_RST_N_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11GN_RISE_TIME_SFT 0
+#define RG_BB_11GN_RISE_TIME_HI 7
+#define RG_BB_11GN_RISE_TIME_SZ 8
+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11GN_FALL_TIME_SFT 8
+#define RG_BB_11GN_FALL_TIME_HI 15
+#define RG_BB_11GN_FALL_TIME_SZ 8
+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HTCARR52_FFT_SCALE_SFT 0
+#define RG_HTCARR52_FFT_SCALE_HI 9
+#define RG_HTCARR52_FFT_SCALE_SZ 10
+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
+#define RG_HTCARR56_FFT_SCALE_SFT 12
+#define RG_HTCARR56_FFT_SCALE_HI 21
+#define RG_HTCARR56_FFT_SCALE_SZ 10
+#define RG_PACKET_STAT_EN_MSK 0x00800000
+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
+#define RG_PACKET_STAT_EN_SFT 23
+#define RG_PACKET_STAT_EN_HI 23
+#define RG_PACKET_STAT_EN_SZ 1
+#define RG_SMB_DEF_MSK 0x7f000000
+#define RG_SMB_DEF_I_MSK 0x80ffffff
+#define RG_SMB_DEF_SFT 24
+#define RG_SMB_DEF_HI 30
+#define RG_SMB_DEF_SZ 7
+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
+#define RG_CONTINUOUS_DATA_11GN_SFT 31
+#define RG_CONTINUOUS_DATA_11GN_HI 31
+#define RG_CONTINUOUS_DATA_11GN_SZ 1
+#define RO_TX_CNT_R_MSK 0xffffffff
+#define RO_TX_CNT_R_I_MSK 0x00000000
+#define RO_TX_CNT_R_SFT 0
+#define RO_TX_CNT_R_HI 31
+#define RO_TX_CNT_R_SZ 32
+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_PACKET_ERR_CNT_SFT 0
+#define RO_PACKET_ERR_CNT_HI 15
+#define RO_PACKET_ERR_CNT_SZ 16
+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11GN_L_EXT_SFT 0
+#define RG_POS_DES_11GN_L_EXT_HI 3
+#define RG_POS_DES_11GN_L_EXT_SZ 4
+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11GN_DLY_SFT 4
+#define RG_PRE_DES_11GN_DLY_HI 7
+#define RG_PRE_DES_11GN_DLY_SZ 4
+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T1_SFT 0
+#define RG_TR_LPF_KI_G_T1_HI 3
+#define RG_TR_LPF_KI_G_T1_SZ 4
+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T1_SFT 4
+#define RG_TR_LPF_KP_G_T1_HI 7
+#define RG_TR_LPF_KP_G_T1_SZ 4
+#define RG_TR_CNT_T1_MSK 0x0000ff00
+#define RG_TR_CNT_T1_I_MSK 0xffff00ff
+#define RG_TR_CNT_T1_SFT 8
+#define RG_TR_CNT_T1_HI 15
+#define RG_TR_CNT_T1_SZ 8
+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
+#define RG_TR_LPF_KI_G_T0_SFT 16
+#define RG_TR_LPF_KI_G_T0_HI 19
+#define RG_TR_LPF_KI_G_T0_SZ 4
+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
+#define RG_TR_LPF_KP_G_T0_SFT 20
+#define RG_TR_LPF_KP_G_T0_HI 23
+#define RG_TR_LPF_KP_G_T0_SZ 4
+#define RG_TR_CNT_T0_MSK 0xff000000
+#define RG_TR_CNT_T0_I_MSK 0x00ffffff
+#define RG_TR_CNT_T0_SFT 24
+#define RG_TR_CNT_T0_HI 31
+#define RG_TR_CNT_T0_SZ 8
+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T2_SFT 0
+#define RG_TR_LPF_KI_G_T2_HI 3
+#define RG_TR_LPF_KI_G_T2_SZ 4
+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T2_SFT 4
+#define RG_TR_LPF_KP_G_T2_HI 7
+#define RG_TR_LPF_KP_G_T2_SZ 4
+#define RG_TR_CNT_T2_MSK 0x0000ff00
+#define RG_TR_CNT_T2_I_MSK 0xffff00ff
+#define RG_TR_CNT_T2_SFT 8
+#define RG_TR_CNT_T2_HI 15
+#define RG_TR_CNT_T2_SZ 8
+#define RG_TR_LPF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_SFT 0
+#define RG_TR_LPF_KI_G_HI 3
+#define RG_TR_LPF_KI_G_SZ 4
+#define RG_TR_LPF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_SFT 4
+#define RG_TR_LPF_KP_G_HI 7
+#define RG_TR_LPF_KP_G_SZ 4
+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_G_SFT 8
+#define RG_TR_LPF_RATE_G_HI 29
+#define RG_TR_LPF_RATE_G_SZ 22
+#define RG_CR_LPF_KI_G_MSK 0x00000007
+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_G_SFT 0
+#define RG_CR_LPF_KI_G_HI 2
+#define RG_CR_LPF_KI_G_SZ 3
+#define RG_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_SYM_BOUND_CNT_SFT 8
+#define RG_SYM_BOUND_CNT_HI 14
+#define RG_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_RX_FFT_SCALE_SFT 0
+#define RG_RX_FFT_SCALE_HI 9
+#define RG_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_SFT 0
+#define RG_PWRON_DLY_TH_11GN_HI 7
+#define RG_PWRON_DLY_TH_11GN_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0x7f000000
+#define RG_POW16_TH_L_I_MSK 0x80ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 30
+#define RG_POW16_TH_L_SZ 7
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_MSK 0x000000ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 7
+#define RG_CR_CNT_UPDATE_SZ 8
+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 23
+#define RG_TR_CNT_UPDATE_SZ 8
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
+#define RG_PILOT_BNDRY_SHIFT_SFT 8
+#define RG_PILOT_BNDRY_SHIFT_HI 10
+#define RG_PILOT_BNDRY_SHIFT_SZ 3
+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
+#define RG_EQ_SHORT_GI_SHIFT_SFT 12
+#define RG_EQ_SHORT_GI_SHIFT_HI 14
+#define RG_EQ_SHORT_GI_SHIFT_SZ 3
+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
+#define RG_FFT_WDW_SHORT_SHIFT_HI 18
+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
+#define RG_FMT_DET_LENGTH_TH_SFT 0
+#define RG_FMT_DET_LENGTH_TH_HI 15
+#define RG_FMT_DET_LENGTH_TH_SZ 16
+#define RG_L_LENGTH_MAX_MSK 0xffff0000
+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 31
+#define RG_L_LENGTH_MAX_SZ 16
+#define RG_TX_TIME_EXT_MSK 0x000000ff
+#define RG_TX_TIME_EXT_I_MSK 0xffffff00
+#define RG_TX_TIME_EXT_SFT 0
+#define RG_TX_TIME_EXT_HI 7
+#define RG_TX_TIME_EXT_SZ 8
+#define RG_MAC_DES_SPACE_MSK 0x00f00000
+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
+#define RG_MAC_DES_SPACE_SFT 20
+#define RG_MAC_DES_SPACE_HI 23
+#define RG_MAC_DES_SPACE_SZ 4
+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
+#define RG_TR_LPF_STBC_GF_KI_G_HI 3
+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
+#define RG_TR_LPF_STBC_GF_KP_G_HI 7
+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
+#define RG_TR_LPF_STBC_MF_KI_G_HI 11
+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
+#define RG_TR_LPF_STBC_MF_KP_G_HI 15
+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
+#define RG_MODE_REG_IN_80_MSK 0x0001ffff
+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
+#define RG_MODE_REG_IN_80_SFT 0
+#define RG_MODE_REG_IN_80_HI 16
+#define RG_MODE_REG_IN_80_SZ 17
+#define RG_PARALLEL_DR_80_MSK 0x00100000
+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_80_SFT 20
+#define RG_PARALLEL_DR_80_HI 20
+#define RG_PARALLEL_DR_80_SZ 1
+#define RG_MBRUN_80_MSK 0x01000000
+#define RG_MBRUN_80_I_MSK 0xfeffffff
+#define RG_MBRUN_80_SFT 24
+#define RG_MBRUN_80_HI 24
+#define RG_MBRUN_80_SZ 1
+#define RG_SHIFT_DR_80_MSK 0x10000000
+#define RG_SHIFT_DR_80_I_MSK 0xefffffff
+#define RG_SHIFT_DR_80_SFT 28
+#define RG_SHIFT_DR_80_HI 28
+#define RG_SHIFT_DR_80_SZ 1
+#define RG_MODE_REG_SI_80_MSK 0x20000000
+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_80_SFT 29
+#define RG_MODE_REG_SI_80_HI 29
+#define RG_MODE_REG_SI_80_SZ 1
+#define RG_SIMULATION_MODE_80_MSK 0x40000000
+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_80_SFT 30
+#define RG_SIMULATION_MODE_80_HI 30
+#define RG_SIMULATION_MODE_80_SZ 1
+#define RG_DBIST_MODE_80_MSK 0x80000000
+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_80_SFT 31
+#define RG_DBIST_MODE_80_HI 31
+#define RG_DBIST_MODE_80_SZ 1
+#define RG_MODE_REG_IN_64_MSK 0x0000ffff
+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_64_SFT 0
+#define RG_MODE_REG_IN_64_HI 15
+#define RG_MODE_REG_IN_64_SZ 16
+#define RG_PARALLEL_DR_64_MSK 0x00100000
+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_64_SFT 20
+#define RG_PARALLEL_DR_64_HI 20
+#define RG_PARALLEL_DR_64_SZ 1
+#define RG_MBRUN_64_MSK 0x01000000
+#define RG_MBRUN_64_I_MSK 0xfeffffff
+#define RG_MBRUN_64_SFT 24
+#define RG_MBRUN_64_HI 24
+#define RG_MBRUN_64_SZ 1
+#define RG_SHIFT_DR_64_MSK 0x10000000
+#define RG_SHIFT_DR_64_I_MSK 0xefffffff
+#define RG_SHIFT_DR_64_SFT 28
+#define RG_SHIFT_DR_64_HI 28
+#define RG_SHIFT_DR_64_SZ 1
+#define RG_MODE_REG_SI_64_MSK 0x20000000
+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_64_SFT 29
+#define RG_MODE_REG_SI_64_HI 29
+#define RG_MODE_REG_SI_64_SZ 1
+#define RG_SIMULATION_MODE_64_MSK 0x40000000
+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_64_SFT 30
+#define RG_SIMULATION_MODE_64_HI 30
+#define RG_SIMULATION_MODE_64_SZ 1
+#define RG_DBIST_MODE_64_MSK 0x80000000
+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_64_SFT 31
+#define RG_DBIST_MODE_64_HI 31
+#define RG_DBIST_MODE_64_SZ 1
+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
+#define RO_MODE_REG_OUT_80_SFT 0
+#define RO_MODE_REG_OUT_80_HI 16
+#define RO_MODE_REG_OUT_80_SZ 17
+#define RO_MODE_REG_SO_80_MSK 0x01000000
+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_80_SFT 24
+#define RO_MODE_REG_SO_80_HI 24
+#define RO_MODE_REG_SO_80_SZ 1
+#define RO_MONITOR_BUS_80_MSK 0x003fffff
+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
+#define RO_MONITOR_BUS_80_SFT 0
+#define RO_MONITOR_BUS_80_HI 21
+#define RO_MONITOR_BUS_80_SZ 22
+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_64_SFT 0
+#define RO_MODE_REG_OUT_64_HI 15
+#define RO_MODE_REG_OUT_64_SZ 16
+#define RO_MODE_REG_SO_64_MSK 0x01000000
+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_64_SFT 24
+#define RO_MODE_REG_SO_64_HI 24
+#define RO_MODE_REG_SO_64_SZ 1
+#define RO_MONITOR_BUS_64_MSK 0x0007ffff
+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_64_SFT 0
+#define RO_MONITOR_BUS_64_HI 18
+#define RO_MONITOR_BUS_64_SZ 19
+#define RO_SPECTRUM_DATA_MSK 0xffffffff
+#define RO_SPECTRUM_DATA_I_MSK 0x00000000
+#define RO_SPECTRUM_DATA_SFT 0
+#define RO_SPECTRUM_DATA_HI 31
+#define RO_SPECTRUM_DATA_SZ 32
+#define GN_SNR_MSK 0x0000007f
+#define GN_SNR_I_MSK 0xffffff80
+#define GN_SNR_SFT 0
+#define GN_SNR_HI 6
+#define GN_SNR_SZ 7
+#define GN_NOISE_PWR_MSK 0x00007f00
+#define GN_NOISE_PWR_I_MSK 0xffff80ff
+#define GN_NOISE_PWR_SFT 8
+#define GN_NOISE_PWR_HI 14
+#define GN_NOISE_PWR_SZ 7
+#define GN_RCPI_MSK 0x007f0000
+#define GN_RCPI_I_MSK 0xff80ffff
+#define GN_RCPI_SFT 16
+#define GN_RCPI_HI 22
+#define GN_RCPI_SZ 7
+#define GN_SIGNAL_PWR_MSK 0x7f000000
+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define GN_SIGNAL_PWR_SFT 24
+#define GN_SIGNAL_PWR_HI 30
+#define GN_SIGNAL_PWR_SZ 7
+#define RO_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_FREQ_OS_LTS_SFT 0
+#define RO_FREQ_OS_LTS_HI 14
+#define RO_FREQ_OS_LTS_SZ 15
+#define CSTATE_MSK 0x000f0000
+#define CSTATE_I_MSK 0xfff0ffff
+#define CSTATE_SFT 16
+#define CSTATE_HI 19
+#define CSTATE_SZ 4
+#define SIGNAL_FIELD0_MSK 0x00ffffff
+#define SIGNAL_FIELD0_I_MSK 0xff000000
+#define SIGNAL_FIELD0_SFT 0
+#define SIGNAL_FIELD0_HI 23
+#define SIGNAL_FIELD0_SZ 24
+#define SIGNAL_FIELD1_MSK 0x00ffffff
+#define SIGNAL_FIELD1_I_MSK 0xff000000
+#define SIGNAL_FIELD1_SFT 0
+#define SIGNAL_FIELD1_HI 23
+#define SIGNAL_FIELD1_SZ 24
+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define GN_PACKET_ERR_CNT_SFT 0
+#define GN_PACKET_ERR_CNT_HI 15
+#define GN_PACKET_ERR_CNT_SZ 16
+#define GN_PACKET_CNT_MSK 0x0000ffff
+#define GN_PACKET_CNT_I_MSK 0xffff0000
+#define GN_PACKET_CNT_SFT 0
+#define GN_PACKET_CNT_HI 15
+#define GN_PACKET_CNT_SZ 16
+#define GN_CCA_CNT_MSK 0xffff0000
+#define GN_CCA_CNT_I_MSK 0x0000ffff
+#define GN_CCA_CNT_SFT 16
+#define GN_CCA_CNT_HI 31
+#define GN_CCA_CNT_SZ 16
+#define GN_LENGTH_FIELD_MSK 0x0000ffff
+#define GN_LENGTH_FIELD_I_MSK 0xffff0000
+#define GN_LENGTH_FIELD_SFT 0
+#define GN_LENGTH_FIELD_HI 15
+#define GN_LENGTH_FIELD_SZ 16
+#define GN_SERVICE_FIELD_MSK 0xffff0000
+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define GN_SERVICE_FIELD_SFT 16
+#define GN_SERVICE_FIELD_HI 31
+#define GN_SERVICE_FIELD_SZ 16
+#define RO_HT_MCS_40M_MSK 0x0000007f
+#define RO_HT_MCS_40M_I_MSK 0xffffff80
+#define RO_HT_MCS_40M_SFT 0
+#define RO_HT_MCS_40M_HI 6
+#define RO_HT_MCS_40M_SZ 7
+#define RO_L_RATE_40M_MSK 0x00003f00
+#define RO_L_RATE_40M_I_MSK 0xffffc0ff
+#define RO_L_RATE_40M_SFT 8
+#define RO_L_RATE_40M_HI 13
+#define RO_L_RATE_40M_SZ 6
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_SFT 20
+#define RG_PACKET_STAT_EN_11GN_HI 20
+#define RG_PACKET_STAT_EN_11GN_SZ 1
+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11GN_SOFT_RST_N_SFT 0
+#define RX_PHY_11GN_SOFT_RST_N_HI 0
+#define RX_PHY_11GN_SOFT_RST_N_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
+#define RG_HT_LTF_SEL_EQ_SFT 6
+#define RG_HT_LTF_SEL_EQ_HI 6
+#define RG_HT_LTF_SEL_EQ_SZ 1
+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
+#define RG_HT_LTF_SEL_PILOT_SFT 7
+#define RG_HT_LTF_SEL_PILOT_HI 7
+#define RG_HT_LTF_SEL_PILOT_SZ 1
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_MSK 0x0000f000
+#define RG_DEBUG_SEL_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_SFT 12
+#define RG_DEBUG_SEL_HI 15
+#define RG_DEBUG_SEL_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define IQCAL_RF_TX_EN_MSK 0x00000001
+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
+#define IQCAL_RF_TX_EN_SFT 0
+#define IQCAL_RF_TX_EN_HI 0
+#define IQCAL_RF_TX_EN_SZ 1
+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
+#define IQCAL_RF_TX_PA_EN_SFT 1
+#define IQCAL_RF_TX_PA_EN_HI 1
+#define IQCAL_RF_TX_PA_EN_SZ 1
+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
+#define IQCAL_RF_TX_DAC_EN_SFT 2
+#define IQCAL_RF_TX_DAC_EN_HI 2
+#define IQCAL_RF_TX_DAC_EN_SZ 1
+#define IQCAL_RF_RX_AGC_MSK 0x00000008
+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
+#define IQCAL_RF_RX_AGC_SFT 3
+#define IQCAL_RF_RX_AGC_HI 3
+#define IQCAL_RF_RX_AGC_SZ 1
+#define IQCAL_RF_PGAG_MSK 0x00000f00
+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
+#define IQCAL_RF_PGAG_SFT 8
+#define IQCAL_RF_PGAG_HI 11
+#define IQCAL_RF_PGAG_SZ 4
+#define IQCAL_RF_RFG_MSK 0x00003000
+#define IQCAL_RF_RFG_I_MSK 0xffffcfff
+#define IQCAL_RF_RFG_SFT 12
+#define IQCAL_RF_RFG_HI 13
+#define IQCAL_RF_RFG_SZ 2
+#define RG_TONEGEN_FREQ_MSK 0x007f0000
+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
+#define RG_TONEGEN_FREQ_SFT 16
+#define RG_TONEGEN_FREQ_HI 22
+#define RG_TONEGEN_FREQ_SZ 7
+#define RG_TONEGEN_EN_MSK 0x00800000
+#define RG_TONEGEN_EN_I_MSK 0xff7fffff
+#define RG_TONEGEN_EN_SFT 23
+#define RG_TONEGEN_EN_HI 23
+#define RG_TONEGEN_EN_SZ 1
+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
+#define RG_TONEGEN_INIT_PH_SFT 24
+#define RG_TONEGEN_INIT_PH_HI 30
+#define RG_TONEGEN_INIT_PH_SZ 7
+#define RG_TONEGEN2_FREQ_MSK 0x0000007f
+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
+#define RG_TONEGEN2_FREQ_SFT 0
+#define RG_TONEGEN2_FREQ_HI 6
+#define RG_TONEGEN2_FREQ_SZ 7
+#define RG_TONEGEN2_EN_MSK 0x00000080
+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
+#define RG_TONEGEN2_EN_SFT 7
+#define RG_TONEGEN2_EN_HI 7
+#define RG_TONEGEN2_EN_SZ 1
+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
+#define RG_TONEGEN2_SCALE_SFT 8
+#define RG_TONEGEN2_SCALE_HI 15
+#define RG_TONEGEN2_SCALE_SZ 8
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_I_SCALE_MSK 0x000000ff
+#define RG_TX_I_SCALE_I_MSK 0xffffff00
+#define RG_TX_I_SCALE_SFT 0
+#define RG_TX_I_SCALE_HI 7
+#define RG_TX_I_SCALE_SZ 8
+#define RG_TX_Q_SCALE_MSK 0x0000ff00
+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_TX_Q_SCALE_SFT 8
+#define RG_TX_Q_SCALE_HI 15
+#define RG_TX_Q_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_SGN_OUT_MSK 0x00020000
+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
+#define RG_TX_SGN_OUT_SFT 17
+#define RG_TX_SGN_OUT_HI 17
+#define RG_TX_SGN_OUT_SZ 1
+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
+#define RG_TXIQ_EMU_IDX_SFT 18
+#define RG_TXIQ_EMU_IDX_HI 21
+#define RG_TXIQ_EMU_IDX_SZ 4
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_IQ_THETA_MSK 0x0000001f
+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_TX_IQ_THETA_SFT 0
+#define RG_TX_IQ_THETA_HI 4
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_ALPHA_MSK 0x00001f00
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_ALPHA_SFT 8
+#define RG_TX_IQ_ALPHA_HI 12
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TXIQ_NOSHRINK_MSK 0x00002000
+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_TXIQ_NOSHRINK_SFT 13
+#define RG_TXIQ_NOSHRINK_HI 13
+#define RG_TXIQ_NOSHRINK_SZ 1
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_THETA_MSK 0x0000001f
+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_RX_IQ_THETA_SFT 0
+#define RG_RX_IQ_THETA_HI 4
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_ALPHA_MSK 0x00001f00
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_ALPHA_SFT 8
+#define RG_RX_IQ_ALPHA_HI 12
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RXIQ_NOSHRINK_MSK 0x00002000
+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_RXIQ_NOSHRINK_SFT 13
+#define RG_RXIQ_NOSHRINK_HI 13
+#define RG_RXIQ_NOSHRINK_SZ 1
+#define RG_MA_DPTH_MSK 0x0000000f
+#define RG_MA_DPTH_I_MSK 0xfffffff0
+#define RG_MA_DPTH_SFT 0
+#define RG_MA_DPTH_HI 3
+#define RG_MA_DPTH_SZ 4
+#define RG_INTG_PH_MSK 0x000003f0
+#define RG_INTG_PH_I_MSK 0xfffffc0f
+#define RG_INTG_PH_SFT 4
+#define RG_INTG_PH_HI 9
+#define RG_INTG_PH_SZ 6
+#define RG_INTG_PRD_MSK 0x00001c00
+#define RG_INTG_PRD_I_MSK 0xffffe3ff
+#define RG_INTG_PRD_SFT 10
+#define RG_INTG_PRD_HI 12
+#define RG_INTG_PRD_SZ 3
+#define RG_INTG_MU_MSK 0x00006000
+#define RG_INTG_MU_I_MSK 0xffff9fff
+#define RG_INTG_MU_SFT 13
+#define RG_INTG_MU_HI 14
+#define RG_INTG_MU_SZ 2
+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
+#define RG_IQCAL_SPRM_SELQ_SFT 16
+#define RG_IQCAL_SPRM_SELQ_HI 16
+#define RG_IQCAL_SPRM_SELQ_SZ 1
+#define RG_IQCAL_SPRM_EN_MSK 0x00020000
+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
+#define RG_IQCAL_SPRM_EN_SFT 17
+#define RG_IQCAL_SPRM_EN_HI 17
+#define RG_IQCAL_SPRM_EN_SZ 1
+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
+#define RG_IQCAL_SPRM_FREQ_SFT 18
+#define RG_IQCAL_SPRM_FREQ_HI 23
+#define RG_IQCAL_SPRM_FREQ_SZ 6
+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
+#define RG_IQCAL_IQCOL_EN_SFT 24
+#define RG_IQCAL_IQCOL_EN_HI 24
+#define RG_IQCAL_IQCOL_EN_SZ 1
+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
+#define RG_IQCAL_DC_EN_MSK 0x04000000
+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
+#define RG_IQCAL_DC_EN_SFT 26
+#define RG_IQCAL_DC_EN_HI 26
+#define RG_IQCAL_DC_EN_SZ 1
+#define RG_PHEST_STBY_MSK 0x08000000
+#define RG_PHEST_STBY_I_MSK 0xf7ffffff
+#define RG_PHEST_STBY_SFT 27
+#define RG_PHEST_STBY_HI 27
+#define RG_PHEST_STBY_SZ 1
+#define RG_PHEST_EN_MSK 0x10000000
+#define RG_PHEST_EN_I_MSK 0xefffffff
+#define RG_PHEST_EN_SFT 28
+#define RG_PHEST_EN_HI 28
+#define RG_PHEST_EN_SZ 1
+#define RG_GP_DIV_EN_MSK 0x20000000
+#define RG_GP_DIV_EN_I_MSK 0xdfffffff
+#define RG_GP_DIV_EN_SFT 29
+#define RG_GP_DIV_EN_HI 29
+#define RG_GP_DIV_EN_SZ 1
+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
+#define RG_DPD_GAIN_EST_EN_SFT 30
+#define RG_DPD_GAIN_EST_EN_HI 30
+#define RG_DPD_GAIN_EST_EN_SZ 1
+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
+#define RG_IQCAL_MULT_OP0_SFT 0
+#define RG_IQCAL_MULT_OP0_HI 9
+#define RG_IQCAL_MULT_OP0_SZ 10
+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
+#define RG_IQCAL_MULT_OP1_SFT 16
+#define RG_IQCAL_MULT_OP1_HI 25
+#define RG_IQCAL_MULT_OP1_SZ 10
+#define RO_IQCAL_O_MSK 0x000fffff
+#define RO_IQCAL_O_I_MSK 0xfff00000
+#define RO_IQCAL_O_SFT 0
+#define RO_IQCAL_O_HI 19
+#define RO_IQCAL_O_SZ 20
+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
+#define RO_IQCAL_SPRM_RDY_SFT 20
+#define RO_IQCAL_SPRM_RDY_HI 20
+#define RO_IQCAL_SPRM_RDY_SZ 1
+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
+#define RO_IQCAL_IQCOL_RDY_SFT 21
+#define RO_IQCAL_IQCOL_RDY_HI 21
+#define RO_IQCAL_IQCOL_RDY_SZ 1
+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
+#define RO_IQCAL_DC_RDY_MSK 0x00800000
+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
+#define RO_IQCAL_DC_RDY_SFT 23
+#define RO_IQCAL_DC_RDY_HI 23
+#define RO_IQCAL_DC_RDY_SZ 1
+#define RO_IQCAL_MULT_RDY_MSK 0x01000000
+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
+#define RO_IQCAL_MULT_RDY_SFT 24
+#define RO_IQCAL_MULT_RDY_HI 24
+#define RO_IQCAL_MULT_RDY_SZ 1
+#define RO_FFT_ENRG_RDY_MSK 0x02000000
+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
+#define RO_FFT_ENRG_RDY_SFT 25
+#define RO_FFT_ENRG_RDY_HI 25
+#define RO_FFT_ENRG_RDY_SZ 1
+#define RO_PHEST_RDY_MSK 0x04000000
+#define RO_PHEST_RDY_I_MSK 0xfbffffff
+#define RO_PHEST_RDY_SFT 26
+#define RO_PHEST_RDY_HI 26
+#define RO_PHEST_RDY_SZ 1
+#define RO_GP_DIV_RDY_MSK 0x08000000
+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
+#define RO_GP_DIV_RDY_SFT 27
+#define RO_GP_DIV_RDY_HI 27
+#define RO_GP_DIV_RDY_SZ 1
+#define RO_GAIN_EST_RDY_MSK 0x10000000
+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
+#define RO_GAIN_EST_RDY_SFT 28
+#define RO_GAIN_EST_RDY_HI 28
+#define RO_GAIN_EST_RDY_SZ 1
+#define RO_AMP_O_MSK 0x000001ff
+#define RO_AMP_O_I_MSK 0xfffffe00
+#define RO_AMP_O_SFT 0
+#define RO_AMP_O_HI 8
+#define RO_AMP_O_SZ 9
+#define RG_RX_I_SCALE_MSK 0x000000ff
+#define RG_RX_I_SCALE_I_MSK 0xffffff00
+#define RG_RX_I_SCALE_SFT 0
+#define RG_RX_I_SCALE_HI 7
+#define RG_RX_I_SCALE_SZ 8
+#define RG_RX_Q_SCALE_MSK 0x0000ff00
+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_RX_Q_SCALE_SFT 8
+#define RG_RX_Q_SCALE_HI 15
+#define RG_RX_Q_SCALE_SZ 8
+#define RG_RX_I_OFFSET_MSK 0x00ff0000
+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_RX_I_OFFSET_SFT 16
+#define RG_RX_I_OFFSET_HI 23
+#define RG_RX_I_OFFSET_SZ 8
+#define RG_RX_Q_OFFSET_MSK 0xff000000
+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_RX_Q_OFFSET_SFT 24
+#define RG_RX_Q_OFFSET_HI 31
+#define RG_RX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_SWP_MSK 0x00000001
+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
+#define RG_RX_IQ_SWP_SFT 0
+#define RG_RX_IQ_SWP_HI 0
+#define RG_RX_IQ_SWP_SZ 1
+#define RG_RX_SGN_IN_MSK 0x00000002
+#define RG_RX_SGN_IN_I_MSK 0xfffffffd
+#define RG_RX_SGN_IN_SFT 1
+#define RG_RX_SGN_IN_HI 1
+#define RG_RX_SGN_IN_SZ 1
+#define RG_RX_IQ_SRC_MSK 0x0000000c
+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
+#define RG_RX_IQ_SRC_SFT 2
+#define RG_RX_IQ_SRC_HI 3
+#define RG_RX_IQ_SRC_SZ 2
+#define RG_ACI_GAIN_MSK 0x00000ff0
+#define RG_ACI_GAIN_I_MSK 0xfffff00f
+#define RG_ACI_GAIN_SFT 4
+#define RG_ACI_GAIN_HI 11
+#define RG_ACI_GAIN_SZ 8
+#define RG_FFT_EN_MSK 0x00001000
+#define RG_FFT_EN_I_MSK 0xffffefff
+#define RG_FFT_EN_SFT 12
+#define RG_FFT_EN_HI 12
+#define RG_FFT_EN_SZ 1
+#define RG_FFT_MOD_MSK 0x00002000
+#define RG_FFT_MOD_I_MSK 0xffffdfff
+#define RG_FFT_MOD_SFT 13
+#define RG_FFT_MOD_HI 13
+#define RG_FFT_MOD_SZ 1
+#define RG_FFT_SCALE_MSK 0x00ffc000
+#define RG_FFT_SCALE_I_MSK 0xff003fff
+#define RG_FFT_SCALE_SFT 14
+#define RG_FFT_SCALE_HI 23
+#define RG_FFT_SCALE_SZ 10
+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
+#define RG_FFT_ENRG_FREQ_SFT 24
+#define RG_FFT_ENRG_FREQ_HI 29
+#define RG_FFT_ENRG_FREQ_SZ 6
+#define RG_FPGA_80M_PH_UP_MSK 0x40000000
+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
+#define RG_FPGA_80M_PH_UP_SFT 30
+#define RG_FPGA_80M_PH_UP_HI 30
+#define RG_FPGA_80M_PH_UP_SZ 1
+#define RG_FPGA_80M_PH_STP_MSK 0x80000000
+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
+#define RG_FPGA_80M_PH_STP_SFT 31
+#define RG_FPGA_80M_PH_STP_HI 31
+#define RG_FPGA_80M_PH_STP_SZ 1
+#define RG_ADC2LA_SEL_MSK 0x00000001
+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
+#define RG_ADC2LA_SEL_SFT 0
+#define RG_ADC2LA_SEL_HI 0
+#define RG_ADC2LA_SEL_SZ 1
+#define RG_ADC2LA_CLKPH_MSK 0x00000002
+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
+#define RG_ADC2LA_CLKPH_SFT 1
+#define RG_ADC2LA_CLKPH_HI 1
+#define RG_ADC2LA_CLKPH_SZ 1
+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
+#define RG_RXIQ_EMU_IDX_SFT 0
+#define RG_RXIQ_EMU_IDX_HI 3
+#define RG_RXIQ_EMU_IDX_SZ 4
+#define RG_IQCAL_BP_ACI_MSK 0x00000010
+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
+#define RG_IQCAL_BP_ACI_SFT 4
+#define RG_IQCAL_BP_ACI_HI 4
+#define RG_IQCAL_BP_ACI_SZ 1
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_Y0_SFT 0
+#define RG_DPD_GAIN_EST_Y0_HI 8
+#define RG_DPD_GAIN_EST_Y0_SZ 9
+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
+#define RG_DPD_GAIN_EST_Y1_SFT 16
+#define RG_DPD_GAIN_EST_Y1_HI 24
+#define RG_DPD_GAIN_EST_Y1_SZ 9
+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_LOOP_GAIN_SFT 0
+#define RG_DPD_LOOP_GAIN_HI 9
+#define RG_DPD_LOOP_GAIN_SZ 10
+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_X0_SFT 0
+#define RG_DPD_GAIN_EST_X0_HI 8
+#define RG_DPD_GAIN_EST_X0_SZ 9
+#define RO_DPD_GAIN_MSK 0x03ff0000
+#define RO_DPD_GAIN_I_MSK 0xfc00ffff
+#define RO_DPD_GAIN_SFT 16
+#define RO_DPD_GAIN_HI 25
+#define RO_DPD_GAIN_SZ 10
+#define TX_SCALE_11B_MSK 0x000000ff
+#define TX_SCALE_11B_I_MSK 0xffffff00
+#define TX_SCALE_11B_SFT 0
+#define TX_SCALE_11B_HI 7
+#define TX_SCALE_11B_SZ 8
+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define TX_SCALE_11B_P0D5_SFT 8
+#define TX_SCALE_11B_P0D5_HI 15
+#define TX_SCALE_11B_P0D5_SZ 8
+#define TX_SCALE_11G_MSK 0x00ff0000
+#define TX_SCALE_11G_I_MSK 0xff00ffff
+#define TX_SCALE_11G_SFT 16
+#define TX_SCALE_11G_HI 23
+#define TX_SCALE_11G_SZ 8
+#define TX_SCALE_11G_P0D5_MSK 0xff000000
+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define TX_SCALE_11G_P0D5_SFT 24
+#define TX_SCALE_11G_P0D5_HI 31
+#define TX_SCALE_11G_P0D5_SZ 8
+#define RG_EN_MANUAL_MSK 0x00000001
+#define RG_EN_MANUAL_I_MSK 0xfffffffe
+#define RG_EN_MANUAL_SFT 0
+#define RG_EN_MANUAL_HI 0
+#define RG_EN_MANUAL_SZ 1
+#define RG_TX_EN_MSK 0x00000002
+#define RG_TX_EN_I_MSK 0xfffffffd
+#define RG_TX_EN_SFT 1
+#define RG_TX_EN_HI 1
+#define RG_TX_EN_SZ 1
+#define RG_TX_PA_EN_MSK 0x00000004
+#define RG_TX_PA_EN_I_MSK 0xfffffffb
+#define RG_TX_PA_EN_SFT 2
+#define RG_TX_PA_EN_HI 2
+#define RG_TX_PA_EN_SZ 1
+#define RG_TX_DAC_EN_MSK 0x00000008
+#define RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define RG_TX_DAC_EN_SFT 3
+#define RG_TX_DAC_EN_HI 3
+#define RG_TX_DAC_EN_SZ 1
+#define RG_RX_AGC_MSK 0x00000010
+#define RG_RX_AGC_I_MSK 0xffffffef
+#define RG_RX_AGC_SFT 4
+#define RG_RX_AGC_HI 4
+#define RG_RX_AGC_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_GAIN_MANUAL_SFT 5
+#define RG_RX_GAIN_MANUAL_HI 5
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_RFG_MSK 0x000000c0
+#define RG_RFG_I_MSK 0xffffff3f
+#define RG_RFG_SFT 6
+#define RG_RFG_HI 7
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x00000f00
+#define RG_PGAG_I_MSK 0xfffff0ff
+#define RG_PGAG_SFT 8
+#define RG_PGAG_HI 11
+#define RG_PGAG_SZ 4
+#define RG_MODE_MSK 0x00003000
+#define RG_MODE_I_MSK 0xffffcfff
+#define RG_MODE_SFT 12
+#define RG_MODE_HI 13
+#define RG_MODE_SZ 2
+#define RG_EN_TX_TRSW_MSK 0x00004000
+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define RG_EN_TX_TRSW_SFT 14
+#define RG_EN_TX_TRSW_HI 14
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_EN_SX_MSK 0x00008000
+#define RG_EN_SX_I_MSK 0xffff7fff
+#define RG_EN_SX_SFT 15
+#define RG_EN_SX_HI 15
+#define RG_EN_SX_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00010000
+#define RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define RG_EN_RX_LNA_SFT 16
+#define RG_EN_RX_LNA_HI 16
+#define RG_EN_RX_LNA_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00020000
+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define RG_EN_RX_MIXER_SFT 17
+#define RG_EN_RX_MIXER_HI 17
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00040000
+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define RG_EN_RX_DIV2_SFT 18
+#define RG_EN_RX_DIV2_HI 18
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00080000
+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define RG_EN_RX_LOBUF_SFT 19
+#define RG_EN_RX_LOBUF_HI 19
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00100000
+#define RG_EN_RX_TZ_I_MSK 0xffefffff
+#define RG_EN_RX_TZ_SFT 20
+#define RG_EN_RX_TZ_HI 20
+#define RG_EN_RX_TZ_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00200000
+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define RG_EN_RX_FILTER_SFT 21
+#define RG_EN_RX_FILTER_HI 21
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_EN_RX_HPF_MSK 0x00400000
+#define RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define RG_EN_RX_HPF_SFT 22
+#define RG_EN_RX_HPF_HI 22
+#define RG_EN_RX_HPF_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00800000
+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define RG_EN_RX_RSSI_SFT 23
+#define RG_EN_RX_RSSI_HI 23
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_EN_ADC_MSK 0x01000000
+#define RG_EN_ADC_I_MSK 0xfeffffff
+#define RG_EN_ADC_SFT 24
+#define RG_EN_ADC_HI 24
+#define RG_EN_ADC_SZ 1
+#define RG_EN_TX_MOD_MSK 0x02000000
+#define RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define RG_EN_TX_MOD_SFT 25
+#define RG_EN_TX_MOD_HI 25
+#define RG_EN_TX_MOD_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x04000000
+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define RG_EN_TX_DIV2_SFT 26
+#define RG_EN_TX_DIV2_HI 26
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_EN_TX_LOBF_MSK 0x10000000
+#define RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define RG_EN_TX_LOBF_SFT 28
+#define RG_EN_TX_LOBF_HI 28
+#define RG_EN_TX_LOBF_SZ 1
+#define RG_EN_RX_LOBF_MSK 0x20000000
+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define RG_EN_RX_LOBF_SFT 29
+#define RG_EN_RX_LOBF_HI 29
+#define RG_EN_RX_LOBF_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x40000000
+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define RG_SEL_DPLL_CLK_SFT 30
+#define RG_SEL_DPLL_CLK_HI 30
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
+#define RG_EN_CLK_960MBY13_UART_SFT 31
+#define RG_EN_CLK_960MBY13_UART_HI 31
+#define RG_EN_CLK_960MBY13_UART_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00000001
+#define RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define RG_EN_TX_DPD_SFT 0
+#define RG_EN_TX_DPD_HI 0
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00000002
+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define RG_EN_TX_TSSI_SFT 1
+#define RG_EN_TX_TSSI_HI 1
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000004
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define RG_EN_RX_IQCAL_SFT 2
+#define RG_EN_RX_IQCAL_HI 2
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define RG_EN_TX_DAC_CAL_SFT 3
+#define RG_EN_TX_DAC_CAL_HI 3
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define RG_EN_TX_SELF_MIXER_SFT 4
+#define RG_EN_TX_SELF_MIXER_HI 4
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define RG_EN_TX_DAC_OUT_SFT 5
+#define RG_EN_TX_DAC_OUT_HI 5
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000040
+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define RG_EN_LDO_RX_FE_SFT 6
+#define RG_EN_LDO_RX_FE_HI 6
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_ABB_MSK 0x00000080
+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define RG_EN_LDO_ABB_SFT 7
+#define RG_EN_LDO_ABB_HI 7
+#define RG_EN_LDO_ABB_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000100
+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define RG_EN_LDO_AFE_SFT 8
+#define RG_EN_LDO_AFE_HI 8
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_SX_CHPLDO_MSK 0x00000200
+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define RG_EN_SX_CHPLDO_SFT 9
+#define RG_EN_SX_CHPLDO_HI 9
+#define RG_EN_SX_CHPLDO_SZ 1
+#define RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define RG_EN_SX_LOBFLDO_SFT 10
+#define RG_EN_SX_LOBFLDO_HI 10
+#define RG_EN_SX_LOBFLDO_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000800
+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define RG_EN_IREF_RX_SFT 11
+#define RG_EN_IREF_RX_HI 11
+#define RG_EN_IREF_RX_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
+#define RG_EN_TX_DAC_VOUT_SFT 13
+#define RG_EN_TX_DAC_VOUT_HI 13
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_EN_SX_LCK_BIN_MSK 0x00004000
+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
+#define RG_EN_SX_LCK_BIN_SFT 14
+#define RG_EN_SX_LCK_BIN_HI 14
+#define RG_EN_SX_LCK_BIN_SZ 1
+#define RG_RTC_CAL_MODE_MSK 0x00010000
+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
+#define RG_RTC_CAL_MODE_SFT 16
+#define RG_RTC_CAL_MODE_HI 16
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_EN_IQPAD_IOSW_MSK 0x00020000
+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
+#define RG_EN_IQPAD_IOSW_SFT 17
+#define RG_EN_IQPAD_IOSW_HI 17
+#define RG_EN_IQPAD_IOSW_SZ 1
+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
+#define RG_EN_TESTPAD_IOSW_SFT 18
+#define RG_EN_TESTPAD_IOSW_HI 18
+#define RG_EN_TESTPAD_IOSW_SZ 1
+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
+#define RG_EN_TRXBF_BYPASS_SFT 19
+#define RG_EN_TRXBF_BYPASS_HI 19
+#define RG_EN_TRXBF_BYPASS_SZ 1
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_LDO_LEVEL_ABB_SFT 3
+#define RG_LDO_LEVEL_ABB_HI 5
+#define RG_LDO_LEVEL_ABB_SZ 3
+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define RG_LDO_LEVEL_AFE_SFT 6
+#define RG_LDO_LEVEL_AFE_HI 8
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define RG_SX_LDO_CHP_LEVEL_SFT 9
+#define RG_SX_LDO_CHP_LEVEL_HI 11
+#define RG_SX_LDO_CHP_LEVEL_SZ 3
+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define RG_SX_LDO_LOBF_LEVEL_HI 14
+#define RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define RG_SX_LDO_XOSC_LEVEL_HI 17
+#define RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define RG_DP_LDO_LEVEL_SFT 18
+#define RG_DP_LDO_LEVEL_HI 20
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 21
+#define RG_SX_LDO_VCO_LEVEL_HI 23
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define RG_TX_LDO_TX_LEVEL_SFT 24
+#define RG_TX_LDO_TX_LEVEL_HI 26
+#define RG_TX_LDO_TX_LEVEL_SZ 3
+#define RG_EN_RX_PADSW_MSK 0x00000001
+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define RG_EN_RX_PADSW_SFT 0
+#define RG_EN_RX_PADSW_HI 0
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00000002
+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define RG_EN_RX_TESTNODE_SFT 1
+#define RG_EN_RX_TESTNODE_HI 1
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_RX_ABBCFIX_MSK 0x00000004
+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define RG_RX_ABBCFIX_SFT 2
+#define RG_RX_ABBCFIX_HI 2
+#define RG_RX_ABBCFIX_SZ 1
+#define RG_RX_ABBCTUNE_MSK 0x000001f8
+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define RG_RX_ABBCTUNE_SFT 3
+#define RG_RX_ABBCTUNE_HI 8
+#define RG_RX_ABBCTUNE_SZ 6
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define RG_RX_ABBOUT_TRI_STATE_HI 9
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_RX_ABB_N_MODE_MSK 0x00000400
+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define RG_RX_ABB_N_MODE_SFT 10
+#define RG_RX_ABB_N_MODE_HI 10
+#define RG_RX_ABB_N_MODE_SZ 1
+#define RG_RX_EN_LOOPA_MSK 0x00000800
+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define RG_RX_EN_LOOPA_SFT 11
+#define RG_RX_EN_LOOPA_HI 11
+#define RG_RX_EN_LOOPA_SZ 1
+#define RG_RX_FILTERI1ST_MSK 0x00003000
+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define RG_RX_FILTERI1ST_SFT 12
+#define RG_RX_FILTERI1ST_HI 13
+#define RG_RX_FILTERI1ST_SZ 2
+#define RG_RX_FILTERI2ND_MSK 0x0000c000
+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define RG_RX_FILTERI2ND_SFT 14
+#define RG_RX_FILTERI2ND_HI 15
+#define RG_RX_FILTERI2ND_SZ 2
+#define RG_RX_FILTERI3RD_MSK 0x00030000
+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define RG_RX_FILTERI3RD_SFT 16
+#define RG_RX_FILTERI3RD_HI 17
+#define RG_RX_FILTERI3RD_SZ 2
+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define RG_RX_FILTERI_COURSE_SFT 18
+#define RG_RX_FILTERI_COURSE_HI 19
+#define RG_RX_FILTERI_COURSE_SZ 2
+#define RG_RX_FILTERVCM_MSK 0x00300000
+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define RG_RX_FILTERVCM_SFT 20
+#define RG_RX_FILTERVCM_HI 21
+#define RG_RX_FILTERVCM_SZ 2
+#define RG_RX_HPF3M_MSK 0x00400000
+#define RG_RX_HPF3M_I_MSK 0xffbfffff
+#define RG_RX_HPF3M_SFT 22
+#define RG_RX_HPF3M_HI 22
+#define RG_RX_HPF3M_SZ 1
+#define RG_RX_HPF300K_MSK 0x00800000
+#define RG_RX_HPF300K_I_MSK 0xff7fffff
+#define RG_RX_HPF300K_SFT 23
+#define RG_RX_HPF300K_HI 23
+#define RG_RX_HPF300K_SZ 1
+#define RG_RX_HPFI_MSK 0x03000000
+#define RG_RX_HPFI_I_MSK 0xfcffffff
+#define RG_RX_HPFI_SFT 24
+#define RG_RX_HPFI_HI 25
+#define RG_RX_HPFI_SZ 2
+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define RG_RX_HPF_FINALCORNER_SFT 26
+#define RG_RX_HPF_FINALCORNER_HI 27
+#define RG_RX_HPF_FINALCORNER_SZ 2
+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define RG_RX_HPF_SETTLE1_C_SFT 28
+#define RG_RX_HPF_SETTLE1_C_HI 29
+#define RG_RX_HPF_SETTLE1_C_SZ 2
+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define RG_RX_HPF_SETTLE1_R_SFT 0
+#define RG_RX_HPF_SETTLE1_R_HI 1
+#define RG_RX_HPF_SETTLE1_R_SZ 2
+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define RG_RX_HPF_SETTLE2_C_SFT 2
+#define RG_RX_HPF_SETTLE2_C_HI 3
+#define RG_RX_HPF_SETTLE2_C_SZ 2
+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define RG_RX_HPF_SETTLE2_R_SFT 4
+#define RG_RX_HPF_SETTLE2_R_HI 5
+#define RG_RX_HPF_SETTLE2_R_SZ 2
+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define RG_RX_HPF_VCMCON2_SFT 6
+#define RG_RX_HPF_VCMCON2_HI 7
+#define RG_RX_HPF_VCMCON2_SZ 2
+#define RG_RX_HPF_VCMCON_MSK 0x00000300
+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define RG_RX_HPF_VCMCON_SFT 8
+#define RG_RX_HPF_VCMCON_HI 9
+#define RG_RX_HPF_VCMCON_SZ 2
+#define RG_RX_OUTVCM_MSK 0x00000c00
+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define RG_RX_OUTVCM_SFT 10
+#define RG_RX_OUTVCM_HI 11
+#define RG_RX_OUTVCM_SZ 2
+#define RG_RX_TZI_MSK 0x00003000
+#define RG_RX_TZI_I_MSK 0xffffcfff
+#define RG_RX_TZI_SFT 12
+#define RG_RX_TZI_HI 13
+#define RG_RX_TZI_SZ 2
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define RG_RX_TZ_OUT_TRISTATE_HI 14
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_RX_TZ_VCM_MSK 0x00018000
+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define RG_RX_TZ_VCM_SFT 15
+#define RG_RX_TZ_VCM_HI 16
+#define RG_RX_TZ_VCM_SZ 2
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define RG_EN_RX_RSSI_TESTNODE_HI 19
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define RG_RX_ADCRSSI_CLKSEL_HI 20
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define RG_RX_ADCRSSI_VCM_SFT 21
+#define RG_RX_ADCRSSI_VCM_HI 22
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define RG_RX_REC_LPFCORNER_SFT 23
+#define RG_RX_REC_LPFCORNER_HI 24
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define RG_RSSI_CLOCK_GATING_SFT 25
+#define RG_RSSI_CLOCK_GATING_HI 25
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TXPGA_CAPSW_SFT 0
+#define RG_TXPGA_CAPSW_HI 1
+#define RG_TXPGA_CAPSW_SZ 2
+#define RG_TXPGA_MAIN_MSK 0x000000fc
+#define RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define RG_TXPGA_MAIN_SFT 2
+#define RG_TXPGA_MAIN_HI 7
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00003f00
+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define RG_TXPGA_STEER_SFT 8
+#define RG_TXPGA_STEER_HI 13
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x0000c000
+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define RG_TXMOD_GMCELL_SFT 14
+#define RG_TXMOD_GMCELL_HI 15
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x00030000
+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define RG_TXLPF_GMCELL_SFT 16
+#define RG_TXLPF_GMCELL_HI 17
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_PACELL_EN_MSK 0x001c0000
+#define RG_PACELL_EN_I_MSK 0xffe3ffff
+#define RG_PACELL_EN_SFT 18
+#define RG_PACELL_EN_HI 20
+#define RG_PACELL_EN_SZ 3
+#define RG_PABIAS_CTRL_MSK 0x01e00000
+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define RG_PABIAS_CTRL_SFT 21
+#define RG_PABIAS_CTRL_HI 24
+#define RG_PABIAS_CTRL_SZ 4
+#define RG_TX_DIV_VSET_MSK 0x0c000000
+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define RG_TX_DIV_VSET_SFT 26
+#define RG_TX_DIV_VSET_HI 27
+#define RG_TX_DIV_VSET_SZ 2
+#define RG_TX_LOBUF_VSET_MSK 0x30000000
+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define RG_TX_LOBUF_VSET_SFT 28
+#define RG_TX_LOBUF_VSET_HI 29
+#define RG_TX_LOBUF_VSET_SZ 2
+#define RG_RX_SQDC_MSK 0x00000007
+#define RG_RX_SQDC_I_MSK 0xfffffff8
+#define RG_RX_SQDC_SFT 0
+#define RG_RX_SQDC_HI 2
+#define RG_RX_SQDC_SZ 3
+#define RG_RX_DIV2_CORE_MSK 0x00000018
+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define RG_RX_DIV2_CORE_SFT 3
+#define RG_RX_DIV2_CORE_HI 4
+#define RG_RX_DIV2_CORE_SZ 2
+#define RG_RX_LOBUF_MSK 0x00000060
+#define RG_RX_LOBUF_I_MSK 0xffffff9f
+#define RG_RX_LOBUF_SFT 5
+#define RG_RX_LOBUF_HI 6
+#define RG_RX_LOBUF_SZ 2
+#define RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define RG_TX_DPDGM_BIAS_SFT 7
+#define RG_TX_DPDGM_BIAS_HI 10
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x00007800
+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define RG_TX_DPD_DIV_SFT 11
+#define RG_TX_DPD_DIV_HI 14
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00038000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define RG_TX_TSSI_BIAS_SFT 15
+#define RG_TX_TSSI_BIAS_HI 17
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x001c0000
+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define RG_TX_TSSI_DIV_SFT 18
+#define RG_TX_TSSI_DIV_HI 20
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define RG_TX_TSSI_TESTMODE_SFT 21
+#define RG_TX_TSSI_TESTMODE_HI 21
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_PACASCODE_CTRL_MSK 0x07000000
+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
+#define RG_PACASCODE_CTRL_SFT 24
+#define RG_PACASCODE_CTRL_HI 26
+#define RG_PACASCODE_CTRL_SZ 3
+#define RG_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_HG_LNA_GC_SFT 0
+#define RG_RX_HG_LNA_GC_HI 1
+#define RG_RX_HG_LNA_GC_SZ 2
+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define RG_RX_HG_LNAHGN_BIAS_HI 5
+#define RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define RG_RX_HG_LNAHGP_BIAS_HI 9
+#define RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_HG_LNALG_BIAS_SFT 10
+#define RG_RX_HG_LNALG_BIAS_HI 13
+#define RG_RX_HG_LNALG_BIAS_SZ 4
+#define RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_HG_TZ_GC_SFT 14
+#define RG_RX_HG_TZ_GC_HI 15
+#define RG_RX_HG_TZ_GC_SZ 2
+#define RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_HG_TZ_CAP_SFT 16
+#define RG_RX_HG_TZ_CAP_HI 18
+#define RG_RX_HG_TZ_CAP_SZ 3
+#define RG_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_MG_LNA_GC_SFT 0
+#define RG_RX_MG_LNA_GC_HI 1
+#define RG_RX_MG_LNA_GC_SZ 2
+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define RG_RX_MG_LNAHGN_BIAS_HI 5
+#define RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define RG_RX_MG_LNAHGP_BIAS_HI 9
+#define RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_MG_LNALG_BIAS_SFT 10
+#define RG_RX_MG_LNALG_BIAS_HI 13
+#define RG_RX_MG_LNALG_BIAS_SZ 4
+#define RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_MG_TZ_GC_SFT 14
+#define RG_RX_MG_TZ_GC_HI 15
+#define RG_RX_MG_TZ_GC_SZ 2
+#define RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_MG_TZ_CAP_SFT 16
+#define RG_RX_MG_TZ_CAP_HI 18
+#define RG_RX_MG_TZ_CAP_SZ 3
+#define RG_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_LG_LNA_GC_SFT 0
+#define RG_RX_LG_LNA_GC_HI 1
+#define RG_RX_LG_LNA_GC_SZ 2
+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define RG_RX_LG_LNAHGN_BIAS_HI 5
+#define RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define RG_RX_LG_LNAHGP_BIAS_HI 9
+#define RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_LG_LNALG_BIAS_SFT 10
+#define RG_RX_LG_LNALG_BIAS_HI 13
+#define RG_RX_LG_LNALG_BIAS_SZ 4
+#define RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_LG_TZ_GC_SFT 14
+#define RG_RX_LG_TZ_GC_HI 15
+#define RG_RX_LG_TZ_GC_SZ 2
+#define RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_LG_TZ_CAP_SFT 16
+#define RG_RX_LG_TZ_CAP_HI 18
+#define RG_RX_LG_TZ_CAP_SZ 3
+#define RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_ULG_LNA_GC_SFT 0
+#define RG_RX_ULG_LNA_GC_HI 1
+#define RG_RX_ULG_LNA_GC_SZ 2
+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_ULG_LNALG_BIAS_SFT 10
+#define RG_RX_ULG_LNALG_BIAS_HI 13
+#define RG_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_ULG_TZ_GC_SFT 14
+#define RG_RX_ULG_TZ_GC_HI 15
+#define RG_RX_ULG_TZ_GC_SZ 2
+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_ULG_TZ_CAP_SFT 16
+#define RG_RX_ULG_TZ_CAP_HI 18
+#define RG_RX_ULG_TZ_CAP_SZ 3
+#define RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define RG_HPF1_FAST_SET_X_SFT 0
+#define RG_HPF1_FAST_SET_X_HI 0
+#define RG_HPF1_FAST_SET_X_SZ 1
+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define RG_HPF1_FAST_SET_Y_SFT 1
+#define RG_HPF1_FAST_SET_Y_HI 1
+#define RG_HPF1_FAST_SET_Y_SZ 1
+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define RG_HPF1_FAST_SET_Z_SFT 2
+#define RG_HPF1_FAST_SET_Z_HI 2
+#define RG_HPF1_FAST_SET_Z_SZ 1
+#define RG_HPF_T1A_MSK 0x00000018
+#define RG_HPF_T1A_I_MSK 0xffffffe7
+#define RG_HPF_T1A_SFT 3
+#define RG_HPF_T1A_HI 4
+#define RG_HPF_T1A_SZ 2
+#define RG_HPF_T1B_MSK 0x00000060
+#define RG_HPF_T1B_I_MSK 0xffffff9f
+#define RG_HPF_T1B_SFT 5
+#define RG_HPF_T1B_HI 6
+#define RG_HPF_T1B_SZ 2
+#define RG_HPF_T1C_MSK 0x00000180
+#define RG_HPF_T1C_I_MSK 0xfffffe7f
+#define RG_HPF_T1C_SFT 7
+#define RG_HPF_T1C_HI 8
+#define RG_HPF_T1C_SZ 2
+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define RG_RX_LNA_TRI_SEL_SFT 9
+#define RG_RX_LNA_TRI_SEL_HI 10
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0x00001800
+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define RG_RX_LNA_SETTLE_SFT 11
+#define RG_RX_LNA_SETTLE_HI 12
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
+#define RG_TXGAIN_PHYCTRL_SFT 13
+#define RG_TXGAIN_PHYCTRL_HI 13
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_TX_GAIN_MSK 0x003fc000
+#define RG_TX_GAIN_I_MSK 0xffc03fff
+#define RG_TX_GAIN_SFT 14
+#define RG_TX_GAIN_HI 21
+#define RG_TX_GAIN_SZ 8
+#define RG_TXGAIN_MANUAL_MSK 0x00400000
+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
+#define RG_TXGAIN_MANUAL_SFT 22
+#define RG_TXGAIN_MANUAL_HI 22
+#define RG_TXGAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_OFFSET_MSK 0x07800000
+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
+#define RG_TX_GAIN_OFFSET_SFT 23
+#define RG_TX_GAIN_OFFSET_HI 26
+#define RG_TX_GAIN_OFFSET_SZ 4
+#define RG_ADC_CLKSEL_MSK 0x00000001
+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_ADC_CLKSEL_SFT 0
+#define RG_ADC_CLKSEL_HI 0
+#define RG_ADC_CLKSEL_SZ 1
+#define RG_ADC_DIBIAS_MSK 0x00000006
+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define RG_ADC_DIBIAS_SFT 1
+#define RG_ADC_DIBIAS_HI 2
+#define RG_ADC_DIBIAS_SZ 2
+#define RG_ADC_DIVR_MSK 0x00000008
+#define RG_ADC_DIVR_I_MSK 0xfffffff7
+#define RG_ADC_DIVR_SFT 3
+#define RG_ADC_DIVR_HI 3
+#define RG_ADC_DIVR_SZ 1
+#define RG_ADC_DVCMI_MSK 0x00000030
+#define RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define RG_ADC_DVCMI_SFT 4
+#define RG_ADC_DVCMI_HI 5
+#define RG_ADC_DVCMI_SZ 2
+#define RG_ADC_SAMSEL_MSK 0x000003c0
+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define RG_ADC_SAMSEL_SFT 6
+#define RG_ADC_SAMSEL_HI 9
+#define RG_ADC_SAMSEL_SZ 4
+#define RG_ADC_STNBY_MSK 0x00000400
+#define RG_ADC_STNBY_I_MSK 0xfffffbff
+#define RG_ADC_STNBY_SFT 10
+#define RG_ADC_STNBY_HI 10
+#define RG_ADC_STNBY_SZ 1
+#define RG_ADC_TESTMODE_MSK 0x00000800
+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define RG_ADC_TESTMODE_SFT 11
+#define RG_ADC_TESTMODE_HI 11
+#define RG_ADC_TESTMODE_SZ 1
+#define RG_ADC_TSEL_MSK 0x0000f000
+#define RG_ADC_TSEL_I_MSK 0xffff0fff
+#define RG_ADC_TSEL_SFT 12
+#define RG_ADC_TSEL_HI 15
+#define RG_ADC_TSEL_SZ 4
+#define RG_ADC_VRSEL_MSK 0x00030000
+#define RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define RG_ADC_VRSEL_SFT 16
+#define RG_ADC_VRSEL_HI 17
+#define RG_ADC_VRSEL_SZ 2
+#define RG_DICMP_MSK 0x000c0000
+#define RG_DICMP_I_MSK 0xfff3ffff
+#define RG_DICMP_SFT 18
+#define RG_DICMP_HI 19
+#define RG_DICMP_SZ 2
+#define RG_DIOP_MSK 0x00300000
+#define RG_DIOP_I_MSK 0xffcfffff
+#define RG_DIOP_SFT 20
+#define RG_DIOP_HI 21
+#define RG_DIOP_SZ 2
+#define RG_SARADC_VRSEL_MSK 0x00c00000
+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
+#define RG_SARADC_VRSEL_SFT 22
+#define RG_SARADC_VRSEL_HI 23
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x03000000
+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
+#define RG_EN_SAR_TEST_SFT 24
+#define RG_EN_SAR_TEST_HI 25
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x04000000
+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
+#define RG_SARADC_THERMAL_SFT 26
+#define RG_SARADC_THERMAL_HI 26
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x08000000
+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
+#define RG_SARADC_TSSI_SFT 27
+#define RG_SARADC_TSSI_HI 27
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0x30000000
+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
+#define RG_CLK_SAR_SEL_SFT 28
+#define RG_CLK_SAR_SEL_HI 29
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_EN_SARADC_MSK 0x40000000
+#define RG_EN_SARADC_I_MSK 0xbfffffff
+#define RG_EN_SARADC_SFT 30
+#define RG_EN_SARADC_HI 30
+#define RG_EN_SARADC_SZ 1
+#define RG_DACI1ST_MSK 0x00000003
+#define RG_DACI1ST_I_MSK 0xfffffffc
+#define RG_DACI1ST_SFT 0
+#define RG_DACI1ST_HI 1
+#define RG_DACI1ST_SZ 2
+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define RG_TX_DACLPF_ICOURSE_SFT 2
+#define RG_TX_DACLPF_ICOURSE_HI 3
+#define RG_TX_DACLPF_ICOURSE_SZ 2
+#define RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TX_DACLPF_IFINE_SFT 4
+#define RG_TX_DACLPF_IFINE_HI 5
+#define RG_TX_DACLPF_IFINE_SZ 2
+#define RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TX_DACLPF_VCM_SFT 6
+#define RG_TX_DACLPF_VCM_HI 7
+#define RG_TX_DACLPF_VCM_SZ 2
+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define RG_TX_DAC_CKEDGE_SEL_HI 8
+#define RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TX_DAC_IBIAS_MSK 0x00000600
+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define RG_TX_DAC_IBIAS_SFT 9
+#define RG_TX_DAC_IBIAS_HI 10
+#define RG_TX_DAC_IBIAS_SZ 2
+#define RG_TX_DAC_OS_MSK 0x00003800
+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define RG_TX_DAC_OS_SFT 11
+#define RG_TX_DAC_OS_HI 13
+#define RG_TX_DAC_OS_SZ 3
+#define RG_TX_DAC_RCAL_MSK 0x0000c000
+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define RG_TX_DAC_RCAL_SFT 14
+#define RG_TX_DAC_RCAL_HI 15
+#define RG_TX_DAC_RCAL_SZ 2
+#define RG_TX_DAC_TSEL_MSK 0x000f0000
+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define RG_TX_DAC_TSEL_SFT 16
+#define RG_TX_DAC_TSEL_HI 19
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 20
+#define RG_TX_EN_VOLTAGE_IN_HI 20
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00200000
+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define RG_TXLPF_BYPASS_SFT 21
+#define RG_TXLPF_BYPASS_HI 21
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TXLPF_BOOSTI_MSK 0x00400000
+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define RG_TXLPF_BOOSTI_SFT 22
+#define RG_TXLPF_BOOSTI_HI 22
+#define RG_TXLPF_BOOSTI_SZ 1
+#define RG_TX_DAC_IOFFSET_MSK 0x07800000
+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
+#define RG_TX_DAC_IOFFSET_SFT 23
+#define RG_TX_DAC_IOFFSET_HI 26
+#define RG_TX_DAC_IOFFSET_SZ 4
+#define RG_TX_DAC_QOFFSET_MSK 0x78000000
+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
+#define RG_TX_DAC_QOFFSET_SFT 27
+#define RG_TX_DAC_QOFFSET_HI 30
+#define RG_TX_DAC_QOFFSET_SZ 4
+#define RG_EN_SX_R3_MSK 0x00000001
+#define RG_EN_SX_R3_I_MSK 0xfffffffe
+#define RG_EN_SX_R3_SFT 0
+#define RG_EN_SX_R3_HI 0
+#define RG_EN_SX_R3_SZ 1
+#define RG_EN_SX_CH_MSK 0x00000002
+#define RG_EN_SX_CH_I_MSK 0xfffffffd
+#define RG_EN_SX_CH_SFT 1
+#define RG_EN_SX_CH_HI 1
+#define RG_EN_SX_CH_SZ 1
+#define RG_EN_SX_CHP_MSK 0x00000004
+#define RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define RG_EN_SX_CHP_SFT 2
+#define RG_EN_SX_CHP_HI 2
+#define RG_EN_SX_CHP_SZ 1
+#define RG_EN_SX_DIVCK_MSK 0x00000008
+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define RG_EN_SX_DIVCK_SFT 3
+#define RG_EN_SX_DIVCK_HI 3
+#define RG_EN_SX_DIVCK_SZ 1
+#define RG_EN_SX_VCOBF_MSK 0x00000010
+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define RG_EN_SX_VCOBF_SFT 4
+#define RG_EN_SX_VCOBF_HI 4
+#define RG_EN_SX_VCOBF_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000020
+#define RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define RG_EN_SX_VCO_SFT 5
+#define RG_EN_SX_VCO_HI 5
+#define RG_EN_SX_VCO_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00000040
+#define RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define RG_EN_SX_MOD_SFT 6
+#define RG_EN_SX_MOD_HI 6
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00000100
+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define RG_EN_SX_DITHER_SFT 8
+#define RG_EN_SX_DITHER_HI 8
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_EN_SX_VT_MON_MSK 0x00000800
+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define RG_EN_SX_VT_MON_SFT 11
+#define RG_EN_SX_VT_MON_HI 11
+#define RG_EN_SX_VT_MON_SZ 1
+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define RG_EN_SX_VT_MON_DG_SFT 12
+#define RG_EN_SX_VT_MON_DG_HI 12
+#define RG_EN_SX_VT_MON_DG_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00002000
+#define RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define RG_EN_SX_DIV_SFT 13
+#define RG_EN_SX_DIV_HI 13
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_LPF_MSK 0x00004000
+#define RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define RG_EN_SX_LPF_SFT 14
+#define RG_EN_SX_LPF_HI 14
+#define RG_EN_SX_LPF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00008000
+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
+#define RG_EN_DPL_MOD_SFT 15
+#define RG_EN_DPL_MOD_HI 15
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00030000
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
+#define RG_DPL_MOD_ORDER_SFT 16
+#define RG_DPL_MOD_ORDER_HI 17
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_SEL_CP_MSK 0x0f000000
+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define RG_SX_SEL_CP_SFT 24
+#define RG_SX_SEL_CP_HI 27
+#define RG_SX_SEL_CP_SZ 4
+#define RG_SX_SEL_CS_MSK 0xf0000000
+#define RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define RG_SX_SEL_CS_SFT 28
+#define RG_SX_SEL_CS_HI 31
+#define RG_SX_SEL_CS_SZ 4
+#define RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_SX_RFCTRL_CH_SFT 0
+#define RG_SX_RFCTRL_CH_HI 10
+#define RG_SX_RFCTRL_CH_SZ 11
+#define RG_SX_SEL_C3_MSK 0x00007800
+#define RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define RG_SX_SEL_C3_SFT 11
+#define RG_SX_SEL_C3_HI 14
+#define RG_SX_SEL_C3_SZ 4
+#define RG_SX_SEL_RS_MSK 0x000f8000
+#define RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define RG_SX_SEL_RS_SFT 15
+#define RG_SX_SEL_RS_HI 19
+#define RG_SX_SEL_RS_SZ 5
+#define RG_SX_SEL_R3_MSK 0x01f00000
+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define RG_SX_SEL_R3_SFT 20
+#define RG_SX_SEL_R3_HI 24
+#define RG_SX_SEL_R3_SZ 5
+#define RG_SX_SEL_ICHP_MSK 0x0000001f
+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define RG_SX_SEL_ICHP_SFT 0
+#define RG_SX_SEL_ICHP_HI 4
+#define RG_SX_SEL_ICHP_SZ 5
+#define RG_SX_SEL_PCHP_MSK 0x000003e0
+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define RG_SX_SEL_PCHP_SFT 5
+#define RG_SX_SEL_PCHP_HI 9
+#define RG_SX_SEL_PCHP_SZ 5
+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define RG_SX_SEL_CHP_REGOP_SFT 10
+#define RG_SX_SEL_CHP_REGOP_HI 13
+#define RG_SX_SEL_CHP_REGOP_SZ 4
+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define RG_SX_SEL_CHP_UNIOP_SFT 14
+#define RG_SX_SEL_CHP_UNIOP_HI 17
+#define RG_SX_SEL_CHP_UNIOP_SZ 4
+#define RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define RG_SX_CHP_IOST_POL_SFT 18
+#define RG_SX_CHP_IOST_POL_HI 18
+#define RG_SX_CHP_IOST_POL_SZ 1
+#define RG_SX_CHP_IOST_MSK 0x00380000
+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define RG_SX_CHP_IOST_SFT 19
+#define RG_SX_CHP_IOST_HI 21
+#define RG_SX_CHP_IOST_SZ 3
+#define RG_SX_PFDSEL_MSK 0x00400000
+#define RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define RG_SX_PFDSEL_SFT 22
+#define RG_SX_PFDSEL_HI 22
+#define RG_SX_PFDSEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define RG_SX_VBNCAS_SEL_SFT 26
+#define RG_SX_VBNCAS_SEL_HI 26
+#define RG_SX_VBNCAS_SEL_SZ 1
+#define RG_SX_PFD_RST_H_MSK 0x08000000
+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define RG_SX_PFD_RST_H_SFT 27
+#define RG_SX_PFD_RST_H_HI 27
+#define RG_SX_PFD_RST_H_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TRSEL_MSK 0x40000000
+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TRSEL_SFT 30
+#define RG_SX_PFD_TRSEL_HI 30
+#define RG_SX_PFD_TRSEL_SZ 1
+#define RG_SX_VCOBA_R_MSK 0x00000007
+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define RG_SX_VCOBA_R_SFT 0
+#define RG_SX_VCOBA_R_HI 2
+#define RG_SX_VCOBA_R_SZ 3
+#define RG_SX_VCORSEL_MSK 0x000000f8
+#define RG_SX_VCORSEL_I_MSK 0xffffff07
+#define RG_SX_VCORSEL_SFT 3
+#define RG_SX_VCORSEL_HI 7
+#define RG_SX_VCORSEL_SZ 5
+#define RG_SX_VCOCUSEL_MSK 0x00000f00
+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define RG_SX_VCOCUSEL_SFT 8
+#define RG_SX_VCOCUSEL_HI 11
+#define RG_SX_VCOCUSEL_SZ 4
+#define RG_SX_RXBFSEL_MSK 0x0000f000
+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define RG_SX_RXBFSEL_SFT 12
+#define RG_SX_RXBFSEL_HI 15
+#define RG_SX_RXBFSEL_SZ 4
+#define RG_SX_TXBFSEL_MSK 0x000f0000
+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define RG_SX_TXBFSEL_SFT 16
+#define RG_SX_TXBFSEL_HI 19
+#define RG_SX_TXBFSEL_SZ 4
+#define RG_SX_VCOBFSEL_MSK 0x00f00000
+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define RG_SX_VCOBFSEL_SFT 20
+#define RG_SX_VCOBFSEL_HI 23
+#define RG_SX_VCOBFSEL_SZ 4
+#define RG_SX_DIVBFSEL_MSK 0x0f000000
+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define RG_SX_DIVBFSEL_SFT 24
+#define RG_SX_DIVBFSEL_HI 27
+#define RG_SX_DIVBFSEL_SZ 4
+#define RG_SX_GNDR_SEL_MSK 0xf0000000
+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define RG_SX_GNDR_SEL_SFT 28
+#define RG_SX_GNDR_SEL_HI 31
+#define RG_SX_GNDR_SEL_SZ 4
+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define RG_SX_DITHER_WEIGHT_SFT 0
+#define RG_SX_DITHER_WEIGHT_HI 1
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_MOD_ORDER_MSK 0x00000030
+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define RG_SX_MOD_ORDER_SFT 4
+#define RG_SX_MOD_ORDER_HI 5
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_RST_H_DIV_MSK 0x00000200
+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define RG_SX_RST_H_DIV_SFT 9
+#define RG_SX_RST_H_DIV_HI 9
+#define RG_SX_RST_H_DIV_SZ 1
+#define RG_SX_SDM_EDGE_MSK 0x00000400
+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_SDM_EDGE_SFT 10
+#define RG_SX_SDM_EDGE_HI 10
+#define RG_SX_SDM_EDGE_SZ 1
+#define RG_SX_XO_GM_MSK 0x00001800
+#define RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define RG_SX_XO_GM_SFT 11
+#define RG_SX_XO_GM_HI 12
+#define RG_SX_XO_GM_SZ 2
+#define RG_SX_REFBYTWO_MSK 0x00002000
+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define RG_SX_REFBYTWO_SFT 13
+#define RG_SX_REFBYTWO_HI 13
+#define RG_SX_REFBYTWO_SZ 1
+#define RG_SX_LCKEN_MSK 0x00080000
+#define RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define RG_SX_LCKEN_SFT 19
+#define RG_SX_LCKEN_HI 19
+#define RG_SX_LCKEN_SZ 1
+#define RG_SX_PREVDD_MSK 0x00f00000
+#define RG_SX_PREVDD_I_MSK 0xff0fffff
+#define RG_SX_PREVDD_SFT 20
+#define RG_SX_PREVDD_HI 23
+#define RG_SX_PREVDD_SZ 4
+#define RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define RG_SX_PSCONTERVDD_SFT 24
+#define RG_SX_PSCONTERVDD_HI 27
+#define RG_SX_PSCONTERVDD_SZ 4
+#define RG_SX_PH_MSK 0x00002000
+#define RG_SX_PH_I_MSK 0xffffdfff
+#define RG_SX_PH_SFT 13
+#define RG_SX_PH_HI 13
+#define RG_SX_PH_SZ 1
+#define RG_SX_PL_MSK 0x00004000
+#define RG_SX_PL_I_MSK 0xffffbfff
+#define RG_SX_PL_SFT 14
+#define RG_SX_PL_HI 14
+#define RG_SX_PL_SZ 1
+#define RG_XOSC_CBANK_XO_MSK 0x00078000
+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
+#define RG_XOSC_CBANK_XO_SFT 15
+#define RG_XOSC_CBANK_XO_HI 18
+#define RG_XOSC_CBANK_XO_SZ 4
+#define RG_XOSC_CBANK_XI_MSK 0x00780000
+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
+#define RG_XOSC_CBANK_XI_SFT 19
+#define RG_XOSC_CBANK_XI_HI 22
+#define RG_XOSC_CBANK_XI_SZ 4
+#define RG_SX_VT_MON_MODE_MSK 0x00000001
+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define RG_SX_VT_MON_MODE_SFT 0
+#define RG_SX_VT_MON_MODE_HI 0
+#define RG_SX_VT_MON_MODE_SZ 1
+#define RG_SX_VT_TH_HI_MSK 0x00000006
+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_SX_VT_TH_HI_SFT 1
+#define RG_SX_VT_TH_HI_HI 2
+#define RG_SX_VT_TH_HI_SZ 2
+#define RG_SX_VT_TH_LO_MSK 0x00000018
+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_SX_VT_TH_LO_SFT 3
+#define RG_SX_VT_TH_LO_HI 4
+#define RG_SX_VT_TH_LO_SZ 2
+#define RG_SX_VT_SET_MSK 0x00000020
+#define RG_SX_VT_SET_I_MSK 0xffffffdf
+#define RG_SX_VT_SET_SFT 5
+#define RG_SX_VT_SET_HI 5
+#define RG_SX_VT_SET_SZ 1
+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define RG_SX_VT_MON_TMR_SFT 6
+#define RG_SX_VT_MON_TMR_HI 14
+#define RG_SX_VT_MON_TMR_SZ 9
+#define RG_EN_DP_VT_MON_MSK 0x00000001
+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define RG_EN_DP_VT_MON_SFT 0
+#define RG_EN_DP_VT_MON_HI 0
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x00000006
+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_DP_VT_TH_HI_SFT 1
+#define RG_DP_VT_TH_HI_HI 2
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00000018
+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_DP_VT_TH_LO_SFT 3
+#define RG_DP_VT_TH_LO_HI 4
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_CK320BY2_MSK 0x00004000
+#define RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define RG_DP_CK320BY2_SFT 14
+#define RG_DP_CK320BY2_HI 14
+#define RG_DP_CK320BY2_SZ 1
+#define RG_DP_OD_TEST_MSK 0x00200000
+#define RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define RG_DP_OD_TEST_SFT 21
+#define RG_DP_OD_TEST_HI 21
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000001
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_BP_SFT 0
+#define RG_DP_BBPLL_BP_HI 0
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_DP_BBPLL_ICP_MSK 0x00000006
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define RG_DP_BBPLL_ICP_SFT 1
+#define RG_DP_BBPLL_ICP_HI 2
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define RG_DP_BBPLL_IDUAL_SFT 3
+#define RG_DP_BBPLL_IDUAL_HI 4
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define RG_DP_BBPLL_OD_TEST_SFT 5
+#define RG_DP_BBPLL_OD_TEST_HI 8
+#define RG_DP_BBPLL_OD_TEST_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000200
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define RG_DP_BBPLL_PD_SFT 9
+#define RG_DP_BBPLL_PD_HI 9
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define RG_DP_BBPLL_TESTSEL_SFT 10
+#define RG_DP_BBPLL_TESTSEL_HI 12
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define RG_DP_BBPLL_PFD_DLY_SFT 13
+#define RG_DP_BBPLL_PFD_DLY_HI 14
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00038000
+#define RG_DP_RP_I_MSK 0xfffc7fff
+#define RG_DP_RP_SFT 15
+#define RG_DP_RP_HI 17
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x000c0000
+#define RG_DP_RHP_I_MSK 0xfff3ffff
+#define RG_DP_RHP_SFT 18
+#define RG_DP_RHP_HI 19
+#define RG_DP_RHP_SZ 2
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DP_FODIV_MSK 0x0007f000
+#define RG_DP_FODIV_I_MSK 0xfff80fff
+#define RG_DP_FODIV_SFT 12
+#define RG_DP_FODIV_HI 18
+#define RG_DP_FODIV_SZ 7
+#define RG_DP_REFDIV_MSK 0x1fc00000
+#define RG_DP_REFDIV_I_MSK 0xe03fffff
+#define RG_DP_REFDIV_SFT 22
+#define RG_DP_REFDIV_HI 28
+#define RG_DP_REFDIV_SZ 7
+#define RG_IDACAI_PGAG15_MSK 0x0000003f
+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG15_SFT 0
+#define RG_IDACAI_PGAG15_HI 5
+#define RG_IDACAI_PGAG15_SZ 6
+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG15_SFT 6
+#define RG_IDACAQ_PGAG15_HI 11
+#define RG_IDACAQ_PGAG15_SZ 6
+#define RG_IDACAI_PGAG14_MSK 0x0003f000
+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG14_SFT 12
+#define RG_IDACAI_PGAG14_HI 17
+#define RG_IDACAI_PGAG14_SZ 6
+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG14_SFT 18
+#define RG_IDACAQ_PGAG14_HI 23
+#define RG_IDACAQ_PGAG14_SZ 6
+#define RG_DP_BBPLL_BS_MSK 0x3f000000
+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
+#define RG_DP_BBPLL_BS_SFT 24
+#define RG_DP_BBPLL_BS_HI 29
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_IDACAI_PGAG13_MSK 0x0000003f
+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG13_SFT 0
+#define RG_IDACAI_PGAG13_HI 5
+#define RG_IDACAI_PGAG13_SZ 6
+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG13_SFT 6
+#define RG_IDACAQ_PGAG13_HI 11
+#define RG_IDACAQ_PGAG13_SZ 6
+#define RG_IDACAI_PGAG12_MSK 0x0003f000
+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG12_SFT 12
+#define RG_IDACAI_PGAG12_HI 17
+#define RG_IDACAI_PGAG12_SZ 6
+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG12_SFT 18
+#define RG_IDACAQ_PGAG12_HI 23
+#define RG_IDACAQ_PGAG12_SZ 6
+#define RG_IDACAI_PGAG11_MSK 0x0000003f
+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG11_SFT 0
+#define RG_IDACAI_PGAG11_HI 5
+#define RG_IDACAI_PGAG11_SZ 6
+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG11_SFT 6
+#define RG_IDACAQ_PGAG11_HI 11
+#define RG_IDACAQ_PGAG11_SZ 6
+#define RG_IDACAI_PGAG10_MSK 0x0003f000
+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG10_SFT 12
+#define RG_IDACAI_PGAG10_HI 17
+#define RG_IDACAI_PGAG10_SZ 6
+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG10_SFT 18
+#define RG_IDACAQ_PGAG10_HI 23
+#define RG_IDACAQ_PGAG10_SZ 6
+#define RG_IDACAI_PGAG9_MSK 0x0000003f
+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG9_SFT 0
+#define RG_IDACAI_PGAG9_HI 5
+#define RG_IDACAI_PGAG9_SZ 6
+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG9_SFT 6
+#define RG_IDACAQ_PGAG9_HI 11
+#define RG_IDACAQ_PGAG9_SZ 6
+#define RG_IDACAI_PGAG8_MSK 0x0003f000
+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG8_SFT 12
+#define RG_IDACAI_PGAG8_HI 17
+#define RG_IDACAI_PGAG8_SZ 6
+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG8_SFT 18
+#define RG_IDACAQ_PGAG8_HI 23
+#define RG_IDACAQ_PGAG8_SZ 6
+#define RG_IDACAI_PGAG7_MSK 0x0000003f
+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG7_SFT 0
+#define RG_IDACAI_PGAG7_HI 5
+#define RG_IDACAI_PGAG7_SZ 6
+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG7_SFT 6
+#define RG_IDACAQ_PGAG7_HI 11
+#define RG_IDACAQ_PGAG7_SZ 6
+#define RG_IDACAI_PGAG6_MSK 0x0003f000
+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG6_SFT 12
+#define RG_IDACAI_PGAG6_HI 17
+#define RG_IDACAI_PGAG6_SZ 6
+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG6_SFT 18
+#define RG_IDACAQ_PGAG6_HI 23
+#define RG_IDACAQ_PGAG6_SZ 6
+#define RG_IDACAI_PGAG5_MSK 0x0000003f
+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG5_SFT 0
+#define RG_IDACAI_PGAG5_HI 5
+#define RG_IDACAI_PGAG5_SZ 6
+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG5_SFT 6
+#define RG_IDACAQ_PGAG5_HI 11
+#define RG_IDACAQ_PGAG5_SZ 6
+#define RG_IDACAI_PGAG4_MSK 0x0003f000
+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG4_SFT 12
+#define RG_IDACAI_PGAG4_HI 17
+#define RG_IDACAI_PGAG4_SZ 6
+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG4_SFT 18
+#define RG_IDACAQ_PGAG4_HI 23
+#define RG_IDACAQ_PGAG4_SZ 6
+#define RG_IDACAI_PGAG3_MSK 0x0000003f
+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG3_SFT 0
+#define RG_IDACAI_PGAG3_HI 5
+#define RG_IDACAI_PGAG3_SZ 6
+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG3_SFT 6
+#define RG_IDACAQ_PGAG3_HI 11
+#define RG_IDACAQ_PGAG3_SZ 6
+#define RG_IDACAI_PGAG2_MSK 0x0003f000
+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG2_SFT 12
+#define RG_IDACAI_PGAG2_HI 17
+#define RG_IDACAI_PGAG2_SZ 6
+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG2_SFT 18
+#define RG_IDACAQ_PGAG2_HI 23
+#define RG_IDACAQ_PGAG2_SZ 6
+#define RG_IDACAI_PGAG1_MSK 0x0000003f
+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG1_SFT 0
+#define RG_IDACAI_PGAG1_HI 5
+#define RG_IDACAI_PGAG1_SZ 6
+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG1_SFT 6
+#define RG_IDACAQ_PGAG1_HI 11
+#define RG_IDACAQ_PGAG1_SZ 6
+#define RG_IDACAI_PGAG0_MSK 0x0003f000
+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG0_SFT 12
+#define RG_IDACAI_PGAG0_HI 17
+#define RG_IDACAI_PGAG0_SZ 6
+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG0_SFT 18
+#define RG_IDACAQ_PGAG0_HI 23
+#define RG_IDACAQ_PGAG0_SZ 6
+#define RG_EN_RCAL_MSK 0x00000001
+#define RG_EN_RCAL_I_MSK 0xfffffffe
+#define RG_EN_RCAL_SFT 0
+#define RG_EN_RCAL_HI 0
+#define RG_EN_RCAL_SZ 1
+#define RG_RCAL_SPD_MSK 0x00000002
+#define RG_RCAL_SPD_I_MSK 0xfffffffd
+#define RG_RCAL_SPD_SFT 1
+#define RG_RCAL_SPD_HI 1
+#define RG_RCAL_SPD_SZ 1
+#define RG_RCAL_TMR_MSK 0x000001fc
+#define RG_RCAL_TMR_I_MSK 0xfffffe03
+#define RG_RCAL_TMR_SFT 2
+#define RG_RCAL_TMR_HI 8
+#define RG_RCAL_TMR_SZ 7
+#define RG_RCAL_CODE_CWR_MSK 0x00000200
+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define RG_RCAL_CODE_CWR_SFT 9
+#define RG_RCAL_CODE_CWR_HI 9
+#define RG_RCAL_CODE_CWR_SZ 1
+#define RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define RG_RCAL_CODE_CWD_SFT 10
+#define RG_RCAL_CODE_CWD_HI 14
+#define RG_RCAL_CODE_CWD_SZ 5
+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_CWR_SFT 0
+#define RG_SX_SUB_SEL_CWR_HI 0
+#define RG_SX_SUB_SEL_CWR_SZ 1
+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define RG_SX_SUB_SEL_CWD_SFT 1
+#define RG_SX_SUB_SEL_CWD_HI 7
+#define RG_SX_SUB_SEL_CWD_SZ 7
+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
+#define RG_SX_LCK_BIN_OFFSET_SFT 15
+#define RG_SX_LCK_BIN_OFFSET_HI 18
+#define RG_SX_LCK_BIN_OFFSET_SZ 4
+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
+#define RG_SX_LCK_BIN_PRECISION_SFT 19
+#define RG_SX_LCK_BIN_PRECISION_HI 19
+#define RG_SX_LCK_BIN_PRECISION_SZ 1
+#define RG_SX_LOCK_EN_N_MSK 0x00100000
+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
+#define RG_SX_LOCK_EN_N_SFT 20
+#define RG_SX_LOCK_EN_N_HI 20
+#define RG_SX_LOCK_EN_N_SZ 1
+#define RG_SX_LOCK_MANUAL_MSK 0x00200000
+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
+#define RG_SX_LOCK_MANUAL_SFT 21
+#define RG_SX_LOCK_MANUAL_HI 21
+#define RG_SX_LOCK_MANUAL_SZ 1
+#define RG_SX_SUB_MANUAL_MSK 0x00400000
+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
+#define RG_SX_SUB_MANUAL_SFT 22
+#define RG_SX_SUB_MANUAL_HI 22
+#define RG_SX_SUB_MANUAL_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x3f800000
+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
+#define RG_SX_SUB_SEL_SFT 23
+#define RG_SX_SUB_SEL_HI 29
+#define RG_SX_SUB_SEL_SZ 7
+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
+#define RG_SX_MUX_SEL_VTH_BINL_HI 30
+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
+#define RG_TRX_DUMMMY_MSK 0xffffffff
+#define RG_TRX_DUMMMY_I_MSK 0x00000000
+#define RG_TRX_DUMMMY_SFT 0
+#define RG_TRX_DUMMMY_HI 31
+#define RG_TRX_DUMMMY_SZ 32
+#define RG_SX_DUMMMY_MSK 0xffffffff
+#define RG_SX_DUMMMY_I_MSK 0x00000000
+#define RG_SX_DUMMMY_SFT 0
+#define RG_SX_DUMMMY_HI 31
+#define RG_SX_DUMMMY_SZ 32
+#define RCAL_RDY_MSK 0x00000001
+#define RCAL_RDY_I_MSK 0xfffffffe
+#define RCAL_RDY_SFT 0
+#define RCAL_RDY_HI 0
+#define RCAL_RDY_SZ 1
+#define LCK_BIN_RDY_MSK 0x00000002
+#define LCK_BIN_RDY_I_MSK 0xfffffffd
+#define LCK_BIN_RDY_SFT 1
+#define LCK_BIN_RDY_HI 1
+#define LCK_BIN_RDY_SZ 1
+#define VT_MON_RDY_MSK 0x00000004
+#define VT_MON_RDY_I_MSK 0xfffffffb
+#define VT_MON_RDY_SFT 2
+#define VT_MON_RDY_HI 2
+#define VT_MON_RDY_SZ 1
+#define DA_R_CODE_LUT_MSK 0x000007c0
+#define DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define DA_R_CODE_LUT_SFT 6
+#define DA_R_CODE_LUT_HI 10
+#define DA_R_CODE_LUT_SZ 5
+#define AD_SX_VT_MON_Q_MSK 0x00001800
+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define AD_SX_VT_MON_Q_SFT 11
+#define AD_SX_VT_MON_Q_HI 12
+#define AD_SX_VT_MON_Q_SZ 2
+#define AD_DP_VT_MON_Q_MSK 0x00006000
+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define AD_DP_VT_MON_Q_SFT 13
+#define AD_DP_VT_MON_Q_HI 14
+#define AD_DP_VT_MON_Q_SZ 2
+#define RTC_CAL_RDY_MSK 0x00008000
+#define RTC_CAL_RDY_I_MSK 0xffff7fff
+#define RTC_CAL_RDY_SFT 15
+#define RTC_CAL_RDY_HI 15
+#define RTC_CAL_RDY_SZ 1
+#define RG_SARADC_BIT_MSK 0x003f0000
+#define RG_SARADC_BIT_I_MSK 0xffc0ffff
+#define RG_SARADC_BIT_SFT 16
+#define RG_SARADC_BIT_HI 21
+#define RG_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x00400000
+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
+#define SAR_ADC_FSM_RDY_SFT 22
+#define SAR_ADC_FSM_RDY_HI 22
+#define SAR_ADC_FSM_RDY_SZ 1
+#define AD_CIRCUIT_VERSION_MSK 0x07800000
+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
+#define AD_CIRCUIT_VERSION_SFT 23
+#define AD_CIRCUIT_VERSION_HI 26
+#define AD_CIRCUIT_VERSION_SZ 4
+#define DA_R_CAL_CODE_MSK 0x0000001f
+#define DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define DA_R_CAL_CODE_SFT 0
+#define DA_R_CAL_CODE_HI 4
+#define DA_R_CAL_CODE_SZ 5
+#define DA_SX_SUB_SEL_MSK 0x00000fe0
+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define DA_SX_SUB_SEL_SFT 5
+#define DA_SX_SUB_SEL_HI 11
+#define DA_SX_SUB_SEL_SZ 7
+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_DPL_RFCTRL_CH_SFT 0
+#define RG_DPL_RFCTRL_CH_HI 10
+#define RG_DPL_RFCTRL_CH_SZ 11
+#define RG_RSSIADC_RO_BIT_MSK 0x00007800
+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
+#define RG_RSSIADC_RO_BIT_SFT 11
+#define RG_RSSIADC_RO_BIT_HI 14
+#define RG_RSSIADC_RO_BIT_SZ 4
+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
+#define RG_RX_ADC_I_RO_BIT_SFT 15
+#define RG_RX_ADC_I_RO_BIT_HI 22
+#define RG_RX_ADC_I_RO_BIT_SZ 8
+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
+#define RG_RX_ADC_Q_RO_BIT_SFT 23
+#define RG_RX_ADC_Q_RO_BIT_HI 30
+#define RG_RX_ADC_Q_RO_BIT_SZ 8
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_SX_TARGET_CNT_MSK 0x00001fff
+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
+#define RG_SX_TARGET_CNT_SFT 0
+#define RG_SX_TARGET_CNT_HI 12
+#define RG_SX_TARGET_CNT_SZ 13
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RF_D_REG_MSK 0x0000ffff
+#define RG_RF_D_REG_I_MSK 0xffff0000
+#define RG_RF_D_REG_SFT 0
+#define RG_RF_D_REG_HI 15
+#define RG_RF_D_REG_SZ 16
+#define DIRECT_MODE_MSK 0x00000001
+#define DIRECT_MODE_I_MSK 0xfffffffe
+#define DIRECT_MODE_SFT 0
+#define DIRECT_MODE_HI 0
+#define DIRECT_MODE_SZ 1
+#define TAG_INTERLEAVE_MD_MSK 0x00000002
+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
+#define TAG_INTERLEAVE_MD_SFT 1
+#define TAG_INTERLEAVE_MD_HI 1
+#define TAG_INTERLEAVE_MD_SZ 1
+#define DIS_DEMAND_MSK 0x00000004
+#define DIS_DEMAND_I_MSK 0xfffffffb
+#define DIS_DEMAND_SFT 2
+#define DIS_DEMAND_HI 2
+#define DIS_DEMAND_SZ 1
+#define SAME_ID_ALLOC_MD_MSK 0x00000008
+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
+#define SAME_ID_ALLOC_MD_SFT 3
+#define SAME_ID_ALLOC_MD_HI 3
+#define SAME_ID_ALLOC_MD_SZ 1
+#define HS_ACCESS_MD_MSK 0x00000010
+#define HS_ACCESS_MD_I_MSK 0xffffffef
+#define HS_ACCESS_MD_SFT 4
+#define HS_ACCESS_MD_HI 4
+#define HS_ACCESS_MD_SZ 1
+#define SRAM_ACCESS_MD_MSK 0x00000020
+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
+#define SRAM_ACCESS_MD_SFT 5
+#define SRAM_ACCESS_MD_HI 5
+#define SRAM_ACCESS_MD_SZ 1
+#define NOHIT_RPASS_MD_MSK 0x00000040
+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
+#define NOHIT_RPASS_MD_SFT 6
+#define NOHIT_RPASS_MD_HI 6
+#define NOHIT_RPASS_MD_SZ 1
+#define DMN_FLAG_CLR_MSK 0x00000080
+#define DMN_FLAG_CLR_I_MSK 0xffffff7f
+#define DMN_FLAG_CLR_SFT 7
+#define DMN_FLAG_CLR_HI 7
+#define DMN_FLAG_CLR_SZ 1
+#define ERR_SW_RST_N_MSK 0x00000100
+#define ERR_SW_RST_N_I_MSK 0xfffffeff
+#define ERR_SW_RST_N_SFT 8
+#define ERR_SW_RST_N_HI 8
+#define ERR_SW_RST_N_SZ 1
+#define ALR_SW_RST_N_MSK 0x00000200
+#define ALR_SW_RST_N_I_MSK 0xfffffdff
+#define ALR_SW_RST_N_SFT 9
+#define ALR_SW_RST_N_HI 9
+#define ALR_SW_RST_N_SZ 1
+#define MCH_SW_RST_N_MSK 0x00000400
+#define MCH_SW_RST_N_I_MSK 0xfffffbff
+#define MCH_SW_RST_N_SFT 10
+#define MCH_SW_RST_N_HI 10
+#define MCH_SW_RST_N_SZ 1
+#define TAG_SW_RST_N_MSK 0x00000800
+#define TAG_SW_RST_N_I_MSK 0xfffff7ff
+#define TAG_SW_RST_N_SFT 11
+#define TAG_SW_RST_N_HI 11
+#define TAG_SW_RST_N_SZ 1
+#define ABT_SW_RST_N_MSK 0x00001000
+#define ABT_SW_RST_N_I_MSK 0xffffefff
+#define ABT_SW_RST_N_SFT 12
+#define ABT_SW_RST_N_HI 12
+#define ABT_SW_RST_N_SZ 1
+#define MMU_VER_MSK 0x0000e000
+#define MMU_VER_I_MSK 0xffff1fff
+#define MMU_VER_SFT 13
+#define MMU_VER_HI 15
+#define MMU_VER_SZ 3
+#define MMU_SHARE_MCU_MSK 0x00ff0000
+#define MMU_SHARE_MCU_I_MSK 0xff00ffff
+#define MMU_SHARE_MCU_SFT 16
+#define MMU_SHARE_MCU_HI 23
+#define MMU_SHARE_MCU_SZ 8
+#define HS_WR_MSK 0x00000001
+#define HS_WR_I_MSK 0xfffffffe
+#define HS_WR_SFT 0
+#define HS_WR_HI 0
+#define HS_WR_SZ 1
+#define HS_FLAG_MSK 0x00000010
+#define HS_FLAG_I_MSK 0xffffffef
+#define HS_FLAG_SFT 4
+#define HS_FLAG_HI 4
+#define HS_FLAG_SZ 1
+#define HS_ID_MSK 0x00007f00
+#define HS_ID_I_MSK 0xffff80ff
+#define HS_ID_SFT 8
+#define HS_ID_HI 14
+#define HS_ID_SZ 7
+#define HS_CHANNEL_MSK 0x000f0000
+#define HS_CHANNEL_I_MSK 0xfff0ffff
+#define HS_CHANNEL_SFT 16
+#define HS_CHANNEL_HI 19
+#define HS_CHANNEL_SZ 4
+#define HS_PAGE_MSK 0x00f00000
+#define HS_PAGE_I_MSK 0xff0fffff
+#define HS_PAGE_SFT 20
+#define HS_PAGE_HI 23
+#define HS_PAGE_SZ 4
+#define HS_DATA_MSK 0xff000000
+#define HS_DATA_I_MSK 0x00ffffff
+#define HS_DATA_SFT 24
+#define HS_DATA_HI 31
+#define HS_DATA_SZ 8
+#define CPU_POR0_MSK 0x0000000f
+#define CPU_POR0_I_MSK 0xfffffff0
+#define CPU_POR0_SFT 0
+#define CPU_POR0_HI 3
+#define CPU_POR0_SZ 4
+#define CPU_POR1_MSK 0x000000f0
+#define CPU_POR1_I_MSK 0xffffff0f
+#define CPU_POR1_SFT 4
+#define CPU_POR1_HI 7
+#define CPU_POR1_SZ 4
+#define CPU_POR2_MSK 0x00000f00
+#define CPU_POR2_I_MSK 0xfffff0ff
+#define CPU_POR2_SFT 8
+#define CPU_POR2_HI 11
+#define CPU_POR2_SZ 4
+#define CPU_POR3_MSK 0x0000f000
+#define CPU_POR3_I_MSK 0xffff0fff
+#define CPU_POR3_SFT 12
+#define CPU_POR3_HI 15
+#define CPU_POR3_SZ 4
+#define CPU_POR4_MSK 0x000f0000
+#define CPU_POR4_I_MSK 0xfff0ffff
+#define CPU_POR4_SFT 16
+#define CPU_POR4_HI 19
+#define CPU_POR4_SZ 4
+#define CPU_POR5_MSK 0x00f00000
+#define CPU_POR5_I_MSK 0xff0fffff
+#define CPU_POR5_SFT 20
+#define CPU_POR5_HI 23
+#define CPU_POR5_SZ 4
+#define CPU_POR6_MSK 0x0f000000
+#define CPU_POR6_I_MSK 0xf0ffffff
+#define CPU_POR6_SFT 24
+#define CPU_POR6_HI 27
+#define CPU_POR6_SZ 4
+#define CPU_POR7_MSK 0xf0000000
+#define CPU_POR7_I_MSK 0x0fffffff
+#define CPU_POR7_SFT 28
+#define CPU_POR7_HI 31
+#define CPU_POR7_SZ 4
+#define CPU_POR8_MSK 0x0000000f
+#define CPU_POR8_I_MSK 0xfffffff0
+#define CPU_POR8_SFT 0
+#define CPU_POR8_HI 3
+#define CPU_POR8_SZ 4
+#define CPU_POR9_MSK 0x000000f0
+#define CPU_POR9_I_MSK 0xffffff0f
+#define CPU_POR9_SFT 4
+#define CPU_POR9_HI 7
+#define CPU_POR9_SZ 4
+#define CPU_PORA_MSK 0x00000f00
+#define CPU_PORA_I_MSK 0xfffff0ff
+#define CPU_PORA_SFT 8
+#define CPU_PORA_HI 11
+#define CPU_PORA_SZ 4
+#define CPU_PORB_MSK 0x0000f000
+#define CPU_PORB_I_MSK 0xffff0fff
+#define CPU_PORB_SFT 12
+#define CPU_PORB_HI 15
+#define CPU_PORB_SZ 4
+#define CPU_PORC_MSK 0x000f0000
+#define CPU_PORC_I_MSK 0xfff0ffff
+#define CPU_PORC_SFT 16
+#define CPU_PORC_HI 19
+#define CPU_PORC_SZ 4
+#define CPU_PORD_MSK 0x00f00000
+#define CPU_PORD_I_MSK 0xff0fffff
+#define CPU_PORD_SFT 20
+#define CPU_PORD_HI 23
+#define CPU_PORD_SZ 4
+#define CPU_PORE_MSK 0x0f000000
+#define CPU_PORE_I_MSK 0xf0ffffff
+#define CPU_PORE_SFT 24
+#define CPU_PORE_HI 27
+#define CPU_PORE_SZ 4
+#define CPU_PORF_MSK 0xf0000000
+#define CPU_PORF_I_MSK 0x0fffffff
+#define CPU_PORF_SFT 28
+#define CPU_PORF_HI 31
+#define CPU_PORF_SZ 4
+#define ACC_WR_LEN_MSK 0x0000003f
+#define ACC_WR_LEN_I_MSK 0xffffffc0
+#define ACC_WR_LEN_SFT 0
+#define ACC_WR_LEN_HI 5
+#define ACC_WR_LEN_SZ 6
+#define ACC_RD_LEN_MSK 0x00003f00
+#define ACC_RD_LEN_I_MSK 0xffffc0ff
+#define ACC_RD_LEN_SFT 8
+#define ACC_RD_LEN_HI 13
+#define ACC_RD_LEN_SZ 6
+#define REQ_NACK_CLR_MSK 0x00008000
+#define REQ_NACK_CLR_I_MSK 0xffff7fff
+#define REQ_NACK_CLR_SFT 15
+#define REQ_NACK_CLR_HI 15
+#define REQ_NACK_CLR_SZ 1
+#define NACK_FLAG_BUS_MSK 0xffff0000
+#define NACK_FLAG_BUS_I_MSK 0x0000ffff
+#define NACK_FLAG_BUS_SFT 16
+#define NACK_FLAG_BUS_HI 31
+#define NACK_FLAG_BUS_SZ 16
+#define DMN_R_PASS_MSK 0x0000ffff
+#define DMN_R_PASS_I_MSK 0xffff0000
+#define DMN_R_PASS_SFT 0
+#define DMN_R_PASS_HI 15
+#define DMN_R_PASS_SZ 16
+#define PARA_ALC_RLS_MSK 0x00010000
+#define PARA_ALC_RLS_I_MSK 0xfffeffff
+#define PARA_ALC_RLS_SFT 16
+#define PARA_ALC_RLS_HI 16
+#define PARA_ALC_RLS_SZ 1
+#define REQ_PORNS_CHGEN_MSK 0x01000000
+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
+#define REQ_PORNS_CHGEN_SFT 24
+#define REQ_PORNS_CHGEN_HI 24
+#define REQ_PORNS_CHGEN_SZ 1
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_INT_MSK 0x00008000
+#define ALC_ABT_INT_I_MSK 0xffff7fff
+#define ALC_ABT_INT_SFT 15
+#define ALC_ABT_INT_HI 15
+#define ALC_ABT_INT_SZ 1
+#define RLS_ABT_ID_MSK 0x007f0000
+#define RLS_ABT_ID_I_MSK 0xff80ffff
+#define RLS_ABT_ID_SFT 16
+#define RLS_ABT_ID_HI 22
+#define RLS_ABT_ID_SZ 7
+#define RLS_ABT_INT_MSK 0x80000000
+#define RLS_ABT_INT_I_MSK 0x7fffffff
+#define RLS_ABT_INT_SFT 31
+#define RLS_ABT_INT_HI 31
+#define RLS_ABT_INT_SZ 1
+#define DEBUG_CTL_MSK 0x000000ff
+#define DEBUG_CTL_I_MSK 0xffffff00
+#define DEBUG_CTL_SFT 0
+#define DEBUG_CTL_HI 7
+#define DEBUG_CTL_SZ 8
+#define DEBUG_H16_MSK 0x00000100
+#define DEBUG_H16_I_MSK 0xfffffeff
+#define DEBUG_H16_SFT 8
+#define DEBUG_H16_HI 8
+#define DEBUG_H16_SZ 1
+#define DEBUG_OUT_MSK 0xffffffff
+#define DEBUG_OUT_I_MSK 0x00000000
+#define DEBUG_OUT_SFT 0
+#define DEBUG_OUT_HI 31
+#define DEBUG_OUT_SZ 32
+#define ALC_ERR_MSK 0x00000001
+#define ALC_ERR_I_MSK 0xfffffffe
+#define ALC_ERR_SFT 0
+#define ALC_ERR_HI 0
+#define ALC_ERR_SZ 1
+#define RLS_ERR_MSK 0x00000002
+#define RLS_ERR_I_MSK 0xfffffffd
+#define RLS_ERR_SFT 1
+#define RLS_ERR_HI 1
+#define RLS_ERR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_FLAG_MSK 0x00000001
+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
+#define DMN_NOHIT_FLAG_SFT 0
+#define DMN_NOHIT_FLAG_HI 0
+#define DMN_NOHIT_FLAG_SZ 1
+#define DMN_FLAG_MSK 0x00000002
+#define DMN_FLAG_I_MSK 0xfffffffd
+#define DMN_FLAG_SFT 1
+#define DMN_FLAG_HI 1
+#define DMN_FLAG_SZ 1
+#define DMN_WR_MSK 0x00000008
+#define DMN_WR_I_MSK 0xfffffff7
+#define DMN_WR_SFT 3
+#define DMN_WR_HI 3
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0xffff0000
+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 31
+#define DMN_NHIT_ADDR_SZ 16
+#define TX_MOUNT_MSK 0x000000ff
+#define TX_MOUNT_I_MSK 0xffffff00
+#define TX_MOUNT_SFT 0
+#define TX_MOUNT_HI 7
+#define TX_MOUNT_SZ 8
+#define RX_MOUNT_MSK 0x0000ff00
+#define RX_MOUNT_I_MSK 0xffff00ff
+#define RX_MOUNT_SFT 8
+#define RX_MOUNT_HI 15
+#define RX_MOUNT_SZ 8
+#define AVA_TAG_MSK 0x01ff0000
+#define AVA_TAG_I_MSK 0xfe00ffff
+#define AVA_TAG_SFT 16
+#define AVA_TAG_HI 24
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x80000000
+#define PKTBUF_FULL_I_MSK 0x7fffffff
+#define PKTBUF_FULL_SFT 31
+#define PKTBUF_FULL_HI 31
+#define PKTBUF_FULL_SZ 1
+#define DMN_NOHIT_MCU_MSK 0x00000001
+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
+#define DMN_NOHIT_MCU_SFT 0
+#define DMN_NOHIT_MCU_HI 0
+#define DMN_NOHIT_MCU_SZ 1
+#define DMN_MCU_FLAG_MSK 0x00000002
+#define DMN_MCU_FLAG_I_MSK 0xfffffffd
+#define DMN_MCU_FLAG_SFT 1
+#define DMN_MCU_FLAG_HI 1
+#define DMN_MCU_FLAG_SZ 1
+#define DMN_MCU_WR_MSK 0x00000008
+#define DMN_MCU_WR_I_MSK 0xfffffff7
+#define DMN_MCU_WR_SFT 3
+#define DMN_MCU_WR_HI 3
+#define DMN_MCU_WR_SZ 1
+#define DMN_MCU_PORT_MSK 0x000000f0
+#define DMN_MCU_PORT_I_MSK 0xffffff0f
+#define DMN_MCU_PORT_SFT 4
+#define DMN_MCU_PORT_HI 7
+#define DMN_MCU_PORT_SZ 4
+#define DMN_MCU_ID_MSK 0x00007f00
+#define DMN_MCU_ID_I_MSK 0xffff80ff
+#define DMN_MCU_ID_SFT 8
+#define DMN_MCU_ID_HI 14
+#define DMN_MCU_ID_SZ 7
+#define DMN_MCU_ADDR_MSK 0xffff0000
+#define DMN_MCU_ADDR_I_MSK 0x0000ffff
+#define DMN_MCU_ADDR_SFT 16
+#define DMN_MCU_ADDR_HI 31
+#define DMN_MCU_ADDR_SZ 16
+#define MB_IDTBL_31_0_MSK 0xffffffff
+#define MB_IDTBL_31_0_I_MSK 0x00000000
+#define MB_IDTBL_31_0_SFT 0
+#define MB_IDTBL_31_0_HI 31
+#define MB_IDTBL_31_0_SZ 32
+#define MB_IDTBL_63_32_MSK 0xffffffff
+#define MB_IDTBL_63_32_I_MSK 0x00000000
+#define MB_IDTBL_63_32_SFT 0
+#define MB_IDTBL_63_32_HI 31
+#define MB_IDTBL_63_32_SZ 32
+#define MB_IDTBL_95_64_MSK 0xffffffff
+#define MB_IDTBL_95_64_I_MSK 0x00000000
+#define MB_IDTBL_95_64_SFT 0
+#define MB_IDTBL_95_64_HI 31
+#define MB_IDTBL_95_64_SZ 32
+#define MB_IDTBL_127_96_MSK 0xffffffff
+#define MB_IDTBL_127_96_I_MSK 0x00000000
+#define MB_IDTBL_127_96_SFT 0
+#define MB_IDTBL_127_96_HI 31
+#define MB_IDTBL_127_96_SZ 32
+#define PKT_IDTBL_31_0_MSK 0xffffffff
+#define PKT_IDTBL_31_0_I_MSK 0x00000000
+#define PKT_IDTBL_31_0_SFT 0
+#define PKT_IDTBL_31_0_HI 31
+#define PKT_IDTBL_31_0_SZ 32
+#define PKT_IDTBL_63_32_MSK 0xffffffff
+#define PKT_IDTBL_63_32_I_MSK 0x00000000
+#define PKT_IDTBL_63_32_SFT 0
+#define PKT_IDTBL_63_32_HI 31
+#define PKT_IDTBL_63_32_SZ 32
+#define PKT_IDTBL_95_64_MSK 0xffffffff
+#define PKT_IDTBL_95_64_I_MSK 0x00000000
+#define PKT_IDTBL_95_64_SFT 0
+#define PKT_IDTBL_95_64_HI 31
+#define PKT_IDTBL_95_64_SZ 32
+#define PKT_IDTBL_127_96_MSK 0xffffffff
+#define PKT_IDTBL_127_96_I_MSK 0x00000000
+#define PKT_IDTBL_127_96_SFT 0
+#define PKT_IDTBL_127_96_HI 31
+#define PKT_IDTBL_127_96_SZ 32
+#define DMN_IDTBL_31_0_MSK 0xffffffff
+#define DMN_IDTBL_31_0_I_MSK 0x00000000
+#define DMN_IDTBL_31_0_SFT 0
+#define DMN_IDTBL_31_0_HI 31
+#define DMN_IDTBL_31_0_SZ 32
+#define DMN_IDTBL_63_32_MSK 0xffffffff
+#define DMN_IDTBL_63_32_I_MSK 0x00000000
+#define DMN_IDTBL_63_32_SFT 0
+#define DMN_IDTBL_63_32_HI 31
+#define DMN_IDTBL_63_32_SZ 32
+#define DMN_IDTBL_95_64_MSK 0xffffffff
+#define DMN_IDTBL_95_64_I_MSK 0x00000000
+#define DMN_IDTBL_95_64_SFT 0
+#define DMN_IDTBL_95_64_HI 31
+#define DMN_IDTBL_95_64_SZ 32
+#define DMN_IDTBL_127_96_MSK 0xffffffff
+#define DMN_IDTBL_127_96_I_MSK 0x00000000
+#define DMN_IDTBL_127_96_SFT 0
+#define DMN_IDTBL_127_96_HI 31
+#define DMN_IDTBL_127_96_SZ 32
+#define NEQ_MB_ID_31_0_MSK 0xffffffff
+#define NEQ_MB_ID_31_0_I_MSK 0x00000000
+#define NEQ_MB_ID_31_0_SFT 0
+#define NEQ_MB_ID_31_0_HI 31
+#define NEQ_MB_ID_31_0_SZ 32
+#define NEQ_MB_ID_63_32_MSK 0xffffffff
+#define NEQ_MB_ID_63_32_I_MSK 0x00000000
+#define NEQ_MB_ID_63_32_SFT 0
+#define NEQ_MB_ID_63_32_HI 31
+#define NEQ_MB_ID_63_32_SZ 32
+#define NEQ_MB_ID_95_64_MSK 0xffffffff
+#define NEQ_MB_ID_95_64_I_MSK 0x00000000
+#define NEQ_MB_ID_95_64_SFT 0
+#define NEQ_MB_ID_95_64_HI 31
+#define NEQ_MB_ID_95_64_SZ 32
+#define NEQ_MB_ID_127_96_MSK 0xffffffff
+#define NEQ_MB_ID_127_96_I_MSK 0x00000000
+#define NEQ_MB_ID_127_96_SFT 0
+#define NEQ_MB_ID_127_96_HI 31
+#define NEQ_MB_ID_127_96_SZ 32
+#define NEQ_PKT_ID_31_0_MSK 0xffffffff
+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
+#define NEQ_PKT_ID_31_0_SFT 0
+#define NEQ_PKT_ID_31_0_HI 31
+#define NEQ_PKT_ID_31_0_SZ 32
+#define NEQ_PKT_ID_63_32_MSK 0xffffffff
+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
+#define NEQ_PKT_ID_63_32_SFT 0
+#define NEQ_PKT_ID_63_32_HI 31
+#define NEQ_PKT_ID_63_32_SZ 32
+#define NEQ_PKT_ID_95_64_MSK 0xffffffff
+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
+#define NEQ_PKT_ID_95_64_SFT 0
+#define NEQ_PKT_ID_95_64_HI 31
+#define NEQ_PKT_ID_95_64_SZ 32
+#define NEQ_PKT_ID_127_96_MSK 0xffffffff
+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
+#define NEQ_PKT_ID_127_96_SFT 0
+#define NEQ_PKT_ID_127_96_HI 31
+#define NEQ_PKT_ID_127_96_SZ 32
+#define ALC_NOCHG_ID_MSK 0x0000007f
+#define ALC_NOCHG_ID_I_MSK 0xffffff80
+#define ALC_NOCHG_ID_SFT 0
+#define ALC_NOCHG_ID_HI 6
+#define ALC_NOCHG_ID_SZ 7
+#define ALC_NOCHG_INT_MSK 0x00008000
+#define ALC_NOCHG_INT_I_MSK 0xffff7fff
+#define ALC_NOCHG_INT_SFT 15
+#define ALC_NOCHG_INT_HI 15
+#define ALC_NOCHG_INT_SZ 1
+#define NEQ_PKT_FLAG_MSK 0x00010000
+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
+#define NEQ_PKT_FLAG_SFT 16
+#define NEQ_PKT_FLAG_HI 16
+#define NEQ_PKT_FLAG_SZ 1
+#define NEQ_MB_FLAG_MSK 0x01000000
+#define NEQ_MB_FLAG_I_MSK 0xfeffffff
+#define NEQ_MB_FLAG_SFT 24
+#define NEQ_MB_FLAG_HI 24
+#define NEQ_MB_FLAG_SZ 1
+#define SRAM_TAG_0_MSK 0x0000ffff
+#define SRAM_TAG_0_I_MSK 0xffff0000
+#define SRAM_TAG_0_SFT 0
+#define SRAM_TAG_0_HI 15
+#define SRAM_TAG_0_SZ 16
+#define SRAM_TAG_1_MSK 0xffff0000
+#define SRAM_TAG_1_I_MSK 0x0000ffff
+#define SRAM_TAG_1_SFT 16
+#define SRAM_TAG_1_HI 31
+#define SRAM_TAG_1_SZ 16
+#define SRAM_TAG_2_MSK 0x0000ffff
+#define SRAM_TAG_2_I_MSK 0xffff0000
+#define SRAM_TAG_2_SFT 0
+#define SRAM_TAG_2_HI 15
+#define SRAM_TAG_2_SZ 16
+#define SRAM_TAG_3_MSK 0xffff0000
+#define SRAM_TAG_3_I_MSK 0x0000ffff
+#define SRAM_TAG_3_SFT 16
+#define SRAM_TAG_3_HI 31
+#define SRAM_TAG_3_SZ 16
+#define SRAM_TAG_4_MSK 0x0000ffff
+#define SRAM_TAG_4_I_MSK 0xffff0000
+#define SRAM_TAG_4_SFT 0
+#define SRAM_TAG_4_HI 15
+#define SRAM_TAG_4_SZ 16
+#define SRAM_TAG_5_MSK 0xffff0000
+#define SRAM_TAG_5_I_MSK 0x0000ffff
+#define SRAM_TAG_5_SFT 16
+#define SRAM_TAG_5_HI 31
+#define SRAM_TAG_5_SZ 16
+#define SRAM_TAG_6_MSK 0x0000ffff
+#define SRAM_TAG_6_I_MSK 0xffff0000
+#define SRAM_TAG_6_SFT 0
+#define SRAM_TAG_6_HI 15
+#define SRAM_TAG_6_SZ 16
+#define SRAM_TAG_7_MSK 0xffff0000
+#define SRAM_TAG_7_I_MSK 0x0000ffff
+#define SRAM_TAG_7_SFT 16
+#define SRAM_TAG_7_HI 31
+#define SRAM_TAG_7_SZ 16
+#define SRAM_TAG_8_MSK 0x0000ffff
+#define SRAM_TAG_8_I_MSK 0xffff0000
+#define SRAM_TAG_8_SFT 0
+#define SRAM_TAG_8_HI 15
+#define SRAM_TAG_8_SZ 16
+#define SRAM_TAG_9_MSK 0xffff0000
+#define SRAM_TAG_9_I_MSK 0x0000ffff
+#define SRAM_TAG_9_SFT 16
+#define SRAM_TAG_9_HI 31
+#define SRAM_TAG_9_SZ 16
+#define SRAM_TAG_10_MSK 0x0000ffff
+#define SRAM_TAG_10_I_MSK 0xffff0000
+#define SRAM_TAG_10_SFT 0
+#define SRAM_TAG_10_HI 15
+#define SRAM_TAG_10_SZ 16
+#define SRAM_TAG_11_MSK 0xffff0000
+#define SRAM_TAG_11_I_MSK 0x0000ffff
+#define SRAM_TAG_11_SFT 16
+#define SRAM_TAG_11_HI 31
+#define SRAM_TAG_11_SZ 16
+#define SRAM_TAG_12_MSK 0x0000ffff
+#define SRAM_TAG_12_I_MSK 0xffff0000
+#define SRAM_TAG_12_SFT 0
+#define SRAM_TAG_12_HI 15
+#define SRAM_TAG_12_SZ 16
+#define SRAM_TAG_13_MSK 0xffff0000
+#define SRAM_TAG_13_I_MSK 0x0000ffff
+#define SRAM_TAG_13_SFT 16
+#define SRAM_TAG_13_HI 31
+#define SRAM_TAG_13_SZ 16
+#define SRAM_TAG_14_MSK 0x0000ffff
+#define SRAM_TAG_14_I_MSK 0xffff0000
+#define SRAM_TAG_14_SFT 0
+#define SRAM_TAG_14_HI 15
+#define SRAM_TAG_14_SZ 16
+#define SRAM_TAG_15_MSK 0xffff0000
+#define SRAM_TAG_15_I_MSK 0x0000ffff
+#define SRAM_TAG_15_SFT 16
+#define SRAM_TAG_15_HI 31
+#define SRAM_TAG_15_SZ 16
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h
new file mode 100644
index 000000000..4386a5065
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV6200_COMMON_H_
+#define _SSV6200_COMMON_H_
+#include
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6200_TX_PKT_RSVD_SETTING 0x3
+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
+#ifndef SSV_SUPPORT_HAL
+struct ssv6200_tx_desc {
+ u32 len:16;
+ u32 c_type:3;
+ u32 f80211:1;
+ u32 qos:1;
+ u32 ht:1;
+ u32 use_4addr:1;
+ u32 RSVD_0:3;
+ u32 bc_que:1;
+ u32 security:1;
+ u32 more_data:1;
+ u32 stype_b5b4:2;
+ u32 extra_info:1;
+ u32 fCmd;
+ u32 hdr_offset:8;
+ u32 frag:1;
+ u32 unicast:1;
+ u32 hdr_len:6;
+ u32 tx_report:1;
+ u32 tx_burst:1;
+ u32 ack_policy:2;
+ u32 aggregation:1;
+ u32 RSVD_1:3;
+ u32 do_rts_cts:2;
+ u32 reason:6;
+ u32 payload_offset:8;
+ u32 RSVD_4:7;
+ u32 RSVD_2:1;
+ u32 fCmdIdx:3;
+ u32 wsid:4;
+ u32 txq_idx:3;
+ u32 TxF_ID:6;
+ u32 rts_cts_nav:16;
+ u32 frame_consume_time:10;
+ u32 crate_idx:6;
+ u32 drate_idx:6;
+ u32 dl_length:12;
+ u32 RSVD_3:14;
+ u32 RESERVED[8];
+ struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
+};
+struct ssv6200_rx_desc {
+ u32 len:16;
+ u32 c_type:3;
+ u32 f80211:1;
+ u32 qos:1;
+ u32 ht:1;
+ u32 use_4addr:1;
+ u32 l3cs_err:1;
+ u32 l4cs_err:1;
+ u32 align2:1;
+ u32 RSVD_0:2;
+ u32 psm:1;
+ u32 stype_b5b4:2;
+ u32 extra_info:1;
+ u32 edca0_used:4;
+ u32 edca1_used:5;
+ u32 edca2_used:5;
+ u32 edca3_used:5;
+ u32 mng_used:4;
+ u32 tx_page_used:9;
+ u32 hdr_offset:8;
+ u32 frag:1;
+ u32 unicast:1;
+ u32 hdr_len:6;
+ u32 RxResult:8;
+ u32 wildcard_bssid:1;
+ u32 RSVD_1:1;
+ u32 reason:6;
+ u32 payload_offset:8;
+ u32 tx_id_used:8;
+ u32 fCmdIdx:3;
+ u32 wsid:4;
+ u32 RSVD_3:3;
+ u32 rate_idx:6;
+};
+struct ssv6200_rxphy_info {
+ u32 len:16;
+ u32 rsvd0:16;
+ u32 mode:3;
+ u32 ch_bw:3;
+ u32 preamble:1;
+ u32 ht_short_gi:1;
+ u32 rate:7;
+ u32 rsvd1:1;
+ u32 smoothing:1;
+ u32 no_sounding:1;
+ u32 aggregate:1;
+ u32 stbc:2;
+ u32 fec:1;
+ u32 n_ess:2;
+ u32 rsvd2:8;
+ u32 l_length:12;
+ u32 l_rate:3;
+ u32 rsvd3:17;
+ u32 rsvd4;
+ u32 rpci:8;
+ u32 snr:8;
+ u32 service:16;
+};
+struct ssv6200_rxphy_info_padding {
+ u32 rpci:8;
+ u32 snr:8;
+ u32 RSVD:16;
+};
+struct ssv6200_txphy_info {
+ u32 rsvd[7];
+};
+#endif
+#define SSV_NUM_HW_STA 2
+typedef enum {
+ SSV6XXX_RC_COUNTER_CLEAR = 1,
+ SSV6XXX_RC_REPORT,
+} ssv6xxx_host_rate_control_event;
+struct ssv62xx_tx_rate {
+ s8 data_rate;
+ u8 count;
+} __attribute__((packed));
+struct ampdu_ba_notify_data {
+ u8 wsid;
+ struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
+ u16 seq_no[MAX_AGGR_NUM];
+} __attribute__((packed));
+struct firmware_rate_control_report_data {
+ u8 wsid;
+ struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
+ u16 ampdu_len;
+ u16 ampdu_ack_len;
+ int ack_signal;
+} __attribute__((packed));
+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
+#define SSV_RC_RATE_MAX 39
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h
new file mode 100644
index 000000000..18e549582
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef SSV_SUPPORT_HAL
+ssv_cabrio_reg phy_setting[]= {
+ {0xce0071bc, 0x565B565B},
+ {0xce000008, 0x0000006a},
+ {0xce00000c, 0x00000064},
+ {0xce000010, 0x00007FFF},
+ {0xce000014, 0x00000003},
+ {0xce000018, 0x0055003C},
+ {0xce00001c, 0x00000064},
+ {0xce000020, 0x20000000},
+ {0xce00002c, 0x00000000},
+ {0xce000030, 0x80046072},
+ {0xce000034, 0x1f300f6f},
+ {0xce000038, 0x660F36D0},
+ {0xce00003c, 0x106C0004},
+ {0xce000040, 0x01601400},
+ {0xce000044, 0x00600008},
+ {0xce000048, 0xff000160},
+ {0xce00004c, 0x00000840},
+ {0xce000060, 0x01000405},
+ {0xce000064, 0x06090813},
+ {0xce000068, 0x12070000},
+ {0xce00006c, 0x01000405},
+ {0xce000070, 0x06090813},
+ {0xce000074, 0x12010000},
+ {0xce000078, 0x00000000},
+ {0xce00007c, 0x10110003},
+ {0xce000080, 0x0110000F},
+ {0xce000084, 0x00000000},
+ {0xce000088, 0x00000000},
+ {0xce000094, 0x01012425},
+ {0xce000098, 0x01010101},
+ {0xce00009c, 0x00000011},
+ {0xce0000a0, 0x1fff0000},
+ {0xce0000a4, 0x1fff0000},
+ {0xce0000a8, 0x1fff0000},
+ {0xce0000ac, 0x1fff0000},
+ {0xce0000b8, 0x0000fe3e},
+ {0xce0000fc, 0xffffffff},
+ {0xce000108, 0x0ead04f5},
+ {0xce00010c, 0x0fd60080},
+ {0xce000110, 0x00000009},
+ {0xce0010a4, 0x0000002c},
+ {0xce0010b4, 0x00003001},
+ {0xce0010d4, 0x00000001},
+ {0xce002000, 0x00000044},
+ {0xce002004, 0x00040000},
+ {0xce002008, 0x20300050},
+ {0xce00200c, 0x00003467},
+ {0xce002010, 0x00430000},
+ {0xce002014, 0x20304015},
+ {0xce002018, 0x00390005},
+ {0xce00201c, 0x05555555},
+ {0xce002020, 0x00570057},
+ {0xce002024, 0x00570057},
+ {0xce002028, 0x00236700},
+ {0xce00202c, 0x000d1746},
+ {0xce002030, 0x05061787},
+ {0xce002034, 0x07800000},
+ {0xce00209c, 0x00900008},
+ {0xce0020a0, 0x00000000},
+ {0xce0023f8, 0x00000000},
+ {0xce0023fc, 0x00000001},
+ {0xce0030a4, 0x00001901},
+ {0xce0030b8, 0x5d08908e},
+ {0xce004000, 0x00000044},
+ {0xce004004, 0x00750075},
+ {0xce004008, 0x00000075},
+ {0xce00400c, 0x10000075},
+ {0xce004010, 0x3F384905},
+ {0xce004014, 0x40182000},
+ {0xce004018, 0x20600000},
+ {0xce00401c, 0x0C010120},
+ {0xce004020, 0x50505050},
+ {0xce004024, 0x50000000},
+ {0xce004028, 0x50505050},
+ {0xce00402c, 0x506070A0},
+ {0xce004030, 0xF0000000},
+ {0xce004034, 0x00002424},
+ {0xce004038, 0x00001420},
+ {0xce00409c, 0x0000300A},
+ {0xce0040c0, 0x20000280},
+ {0xce0040c4, 0x30023002},
+ {0xce0040c8, 0x0000003a},
+ {0xce004130, 0x40000000},
+ {0xce004164, 0x009C007E},
+ {0xce004180, 0x00044400},
+ {0xce004188, 0x82000000},
+ {0xce004190, 0x00000000},
+ {0xce004194, 0xffffffff},
+ {0xce004380, 0x00700010},
+ {0xce004384, 0x00007575},
+ {0xce004388, 0x0001fe3e},
+ {0xce00438c, 0x0000fe3e},
+ {0xce0043f8, 0x00000001},
+ {0xce007000, 0x00000000},
+ {0xce007004, 0x00008000},
+ {0xce007008, 0x00000000},
+ {0xce00700c, 0x00000000},
+ {0xce007010, 0x00000000},
+ {0xce007014, 0x00000000},
+ {0xce007018, 0x00000000},
+ {0xce00701c, 0x00000000},
+ {0xce007020, 0x00000000},
+ {0xce007024, 0x00000000},
+ {0xce007028, 0x00000000},
+ {0xce00702c, 0x00000000},
+ {0xce007030, 0x00000000},
+ {0xce007034, 0x00000000},
+ {0xce007038, 0x00000000},
+ {0xce00703c, 0x00000000},
+ {0xce007040, 0x02000200},
+ {0xce007048, 0x00000000},
+ {0xce00704c, 0x00000000},
+ {0xce007050, 0x00000000},
+ {0xce007054, 0x00000000},
+ {0xce007058, 0x000028ff},
+ {0xce00705c, 0x00000000},
+ {0xce007060, 0x00000000},
+ {0xce007064, 0x00000000},
+ {0xce007068, 0x00000000},
+ {0xce00706c, 0x00000202},
+ {0xce007070, 0x80ffc200},
+ {0xce007074, 0x00000000},
+ {0xce007078, 0x00000000},
+ {0xce00707c, 0x00000000},
+ {0xce007080, 0x00000000},
+ {0xce007084, 0x00000000},
+ {0xce007088, 0x00000000},
+ {0xce00708c, 0x00000000},
+ {0xce007090, 0x00000000},
+ {0xce007094, 0x00000000},
+ {0xce007098, 0x00000000},
+ {0xce00709c, 0x00000000},
+ {0xce0070a0, 0x00000000},
+ {0xce0070a4, 0x00000000},
+ {0xce0070a8, 0x00000000},
+ {0xce0070ac, 0x00000000},
+ {0xce0070b0, 0x00000000},
+ {0xce0070b4, 0x00000000},
+ {0xce0070b8, 0x00000000},
+ {0xce0070bc, 0x00000000},
+ {0xce0070c0, 0x00000000},
+ {0xce0070c4, 0x00000000},
+ {0xce0070c8, 0x00000000},
+ {0xce0070cc, 0x00000000},
+ {0xce0070d0, 0x00000000},
+ {0xce0070d4, 0x00000000},
+ {0xce0070d8, 0x00000000},
+ {0xce0070dc, 0x00000000},
+ {0xce0070e0, 0x00000000},
+ {0xce0070e4, 0x00000000},
+ {0xce0070e8, 0x00000000},
+ {0xce0070ec, 0x00000000},
+ {0xce0070f0, 0x00000000},
+ {0xce0070f4, 0x00000000},
+ {0xce0070f8, 0x00000000},
+ {0xce0070fc, 0x00000000},
+ {0xce007100, 0x00000000},
+ {0xce007104, 0x00000000},
+ {0xce007108, 0x00000000},
+ {0xce00710c, 0x00000000},
+ {0xce007110, 0x00000000},
+ {0xce007114, 0x00000000},
+ {0xce007118, 0x00000000},
+ {0xce00711c, 0x00000000},
+ {0xce007120, 0x02000200},
+ {0xce007124, 0x02000200},
+ {0xce007128, 0x02000200},
+ {0xce00712c, 0x02000200},
+ {0xce007130, 0x02000200},
+ {0xce007134, 0x02000200},
+ {0xce007138, 0x02000200},
+ {0xce00713c, 0x02000200},
+ {0xce007140, 0x02000200},
+ {0xce007144, 0x02000200},
+ {0xce007148, 0x02000200},
+ {0xce00714c, 0x02000200},
+ {0xce007150, 0x02000200},
+ {0xce007154, 0x02000200},
+ {0xce007158, 0x00000000},
+ {0xce00715c, 0x00000000},
+ {0xce007160, 0x00000000},
+ {0xce007164, 0x00000000},
+ {0xce007168, 0x00000000},
+ {0xce00716c, 0x00000000},
+ {0xce007170, 0x00000000},
+ {0xce007174, 0x00000000},
+ {0xce007178, 0x00000000},
+ {0xce00717c, 0x00000000},
+ {0xce007180, 0x00000000},
+ {0xce007184, 0x00000000},
+ {0xce007188, 0x00000000},
+ {0xce00718c, 0x00000000},
+ {0xce007190, 0x00000000},
+ {0xce007194, 0x00000000},
+ {0xce007198, 0x00000000},
+ {0xce00719c, 0x00000000},
+ {0xce0071a0, 0x00000000},
+ {0xce0071a4, 0x00000000},
+ {0xce0071a8, 0x00000000},
+ {0xce0071ac, 0x00000000},
+ {0xce0071b0, 0x00000000},
+ {0xce0071b4, 0x00000100},
+ {0xce0071b8, 0x00000000},
+ {0xce0071c0, 0x00000000},
+ {0xce0071c4, 0x00000000},
+ {0xce0071c8, 0x00000000},
+ {0xce0071cc, 0x00000000},
+ {0xce0071d0, 0x00000000},
+ {0xce0071d4, 0x00000000},
+ {0xce0071d8, 0x00000000},
+ {0xce0071dc, 0x00000000},
+ {0xce0071e0, 0x00000000},
+ {0xce0071e4, 0x00000000},
+ {0xce0071e8, 0x00000000},
+ {0xce0071ec, 0x00000000},
+ {0xce0071f0, 0x00000000},
+ {0xce0071f4, 0x00000000},
+ {0xce0071f8, 0x00000000},
+ {0xce0071fc, 0x00000000},
+#ifdef CONFIG_SSV_CABRIO_E
+ {0xce0043fc, 0x000104e5},
+ {0xce007044, 0x00028080},
+ {0xce000000, 0x80000016},
+#endif
+#ifdef CONFIG_SSV_CABRIO_A
+ {0xce0043fc, 0x000004e1},
+ {0xce007044, 0x00038080},
+ {0xce000000, 0x0000001e},
+#endif
+};
+static const u32 wifi_tx_gain[]= {
+ 0x79807980,
+ 0x72797279,
+ 0x6C726C72,
+ 0x666C666C,
+ 0x60666066,
+ 0x5B605B60,
+ 0x565B565B,
+ 0x51565156,
+ 0x4C514C51,
+ 0x484C484C,
+ 0x44484448,
+ 0x40444044,
+ 0x3C403C40,
+ 0x3A3D3A3D,
+ 0x36393639,
+};
+#ifndef CONFIG_SSV_CABRIO_A
+static ssv_cabrio_reg asic_rf_setting[]= {
+ {0xCE010038, 0x0003E07C},
+ {0xCE010060, 0x00406000},
+ {0xCE01009C, 0x00000024},
+ {0xCE0100A0, 0x00EC4CC5},
+ {0xCE010000, 0x40002000},
+ {0xCE010004, 0x00020FC0},
+ {0xCE010008, 0x000DF69B},
+ {0xCE010014, 0x3D3E84FE},
+ {0xCE010018, 0x01457D79},
+ {0xCE01001C, 0x000103A7},
+ {0xCE010020, 0x000103A6},
+ {0xCE01002C, 0x00032CA8},
+ {0xCE010048, 0xFCCCCF27},
+ {0xCE010050, 0x00444000},
+ {0xCE01000C, 0x151558C5},
+ {0xCE010010, 0x01011A88},
+ {0xCE010024, 0x00012001},
+ {0xCE010028, 0x00036000},
+ {0xCE010030, 0x20EA0224},
+ {0xCE010034, 0x44000755},
+ {0xCE01003C, 0x55D89D8A},
+ {0xCE010040, 0x005508BB},
+ {0xCE010044, 0x07C08BFF},
+ {0xCE01004C, 0x07700830},
+ {0xCE010054, 0x00007FF4},
+ {0xCE010058, 0x0000000E},
+ {0xCE01005C, 0x00088018},
+ {0xCE010064, 0x08820820},
+ {0xCE010068, 0x00820820},
+ {0xCE01006C, 0x00820820},
+ {0xCE010070, 0x00820820},
+ {0xCE010074, 0x00820820},
+ {0xCE010078, 0x00820820},
+ {0xCE01007C, 0x00820820},
+ {0xCE010080, 0x00820820},
+ {0xCE010084, 0x00004080},
+ {0xCE010088, 0x200800FE},
+ {0xCE01008C, 0xAAAAAAAA},
+ {0xCE010090, 0xAAAAAAAA},
+ {0xCE010094, 0x0000A487},
+ {0xCE010098, 0x0000070E},
+ {0xCE0100A4, 0x00000F43},
+ {0xCE0100A8, 0x00098900},
+ {0xCE0100AC, 0x00000000},
+ {0xC00003AC, 0x00000000},
+ {0xC00003B0, 0x00000000},
+ {0xC00003B4, 0x00000000},
+ {0xC00003BC, 0x00000000},
+ {0xC0001D00, 0x5E000040},
+ {0xC0001D04, 0x015D015D},
+ {0xC0001D08, 0x00000001},
+ {0xC0001D0C, 0x55550000},
+ {0xC0001D20, 0x7FFF0000},
+ {0xC0001D24, 0x00000003},
+ {0xC0001D28, 0x00000000},
+ {0xC0001D2C, 0x00000000},
+};
+#endif
+#ifdef CONFIG_SSV_CABRIO_A
+static ssv_cabrio_reg fpga_rf_setting[]= {
+ {0xcb110000,0x5F00EFCE},
+ {0xcb110004,0x00001FC0},
+ {0xcb110008,0x1C96CA3A},
+ {0xcb11000c,0x15155A74},
+ {0xcb110010,0x01011A88},
+ {0xcb110014,0x3CBF703C},
+ {0xcb110018,0x00057579},
+ {0xcb11001c,0x000103A7},
+ {0xcb110020,0x000103A6},
+ {0xcb110024,0x00012001},
+ {0xcb110028,0x00036000},
+ {0xcb11002c,0x00000CA8},
+ {0xcb110030,0x002A0224},
+ {0xcb110034,0x00001E55},
+ {0xcb110038,0x00006C7C},
+ {0xcb11003c,0x55666666},
+ {0xcb110040,0x005508F8},
+ {0xcb110044,0x07C08BFF},
+ {0xcb110048,0xF1111A27},
+ {0xcb11004c,0x2773F53C},
+ {0xcb110050,0x00000A7C},
+ {0xcb110054,0x00087FF8},
+ {0xcb110058,0x00103014},
+ {0xcb11005c,0x0000848A},
+ {0xcb110060,0x00406030},
+ {0xcb110064,0x00820820},
+ {0xcb110068,0x00820820},
+ {0xcb11006c,0x00820820},
+ {0xcb110070,0x00820820},
+ {0xcb110074,0x00820820},
+ {0xcb110078,0x00820820},
+ {0xcb11007c,0x00820820},
+ {0xcb110080,0x00820820},
+ {0xcb110084,0x00004080},
+ {0xcb110088,0x00003EAA},
+ {0xcb11008c,0x5E00FFEB},
+ {0xcb110090,0xAAAAAAAA},
+ {0xcb110094,0x0000243F},
+ {0xcb110098,0x00018B10},
+ {0xcb120080,0x00000000},
+ {0xcb120084,0x00000000},
+ {0xcb120088,0x00000000},
+ {0xcb120090,0x00000813},
+ {0xcb120094,0x00000000},
+ {0xcb1203f8,0xFF000000},
+};
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h
new file mode 100644
index 000000000..42775fce1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h
@@ -0,0 +1,9693 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#define SYS_REG_BASE 0xc0000000
+#define WBOOT_REG_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define GPIO_REG_BASE 0xc0000300
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define INT_REG_BASE 0xc0000e00
+#define DBG_SPI_REG_BASE 0xc0000f00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define CSR_PMU_BASE 0xc0001d00
+#define CSR_RTC_BASE 0xc0001d20
+#define RTC_RAM_BASE 0xc0001d80
+#define D2_DMA_REG_BASE 0xc0001e00
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define SMS4_REG_BASE 0xc3000000
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define CBR_A_REG_BASE 0xcb000000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define CSR_PHY_BASE 0xce000000
+#define CSR_RF_BASE 0xce010000
+#define MMU_REG_BASE 0xcf000000
+#define SYS_REG_BANK_SIZE 0x000000b4
+#define WBOOT_REG_BANK_SIZE 0x0000000c
+#define TU0_US_REG_BANK_SIZE 0x00000010
+#define TU1_US_REG_BANK_SIZE 0x00000010
+#define TU2_US_REG_BANK_SIZE 0x00000010
+#define TU3_US_REG_BANK_SIZE 0x00000010
+#define TM0_MS_REG_BANK_SIZE 0x00000010
+#define TM1_MS_REG_BANK_SIZE 0x00000010
+#define TM2_MS_REG_BANK_SIZE 0x00000010
+#define TM3_MS_REG_BANK_SIZE 0x00000010
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define GPIO_REG_BANK_SIZE 0x000000d4
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_MST_BANK_SIZE 0x00000018
+#define UART_REG_BANK_SIZE 0x00000028
+#define DAT_UART_REG_BANK_SIZE 0x00000028
+#define INT_REG_BANK_SIZE 0x0000004c
+#define DBG_SPI_REG_BANK_SIZE 0x00000040
+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
+#define DMA_REG_BANK_SIZE 0x00000014
+#define CSR_PMU_BANK_SIZE 0x00000100
+#define CSR_RTC_BANK_SIZE 0x000000e0
+#define RTC_RAM_BANK_SIZE 0x00000080
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define HCI_REG_BANK_SIZE 0x000000cc
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x0000006c
+#define SMS4_REG_BANK_SIZE 0x00000070
+#define MRX_REG_BANK_SIZE 0x00000198
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
+#define MAC_GLB_SET_BANK_SIZE 0x0000003c
+#define BTCX_REG_BANK_SIZE 0x0000000c
+#define MIB_REG_BANK_SIZE 0x00000480
+#define CBR_A_REG_BANK_SIZE 0x001203fc
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define CSR_PHY_BANK_SIZE 0x000071c0
+#define CSR_RF_BANK_SIZE 0x000000b0
+#define MMU_REG_BANK_SIZE 0x000000c0
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
+#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
+#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
+#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
+#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h
new file mode 100644
index 000000000..4143f9c21
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include "ssv6200_reg.h"
+#define BANK_COUNT 49
+static const u32 BASE_BANK_SSV6200[] = {
+ SYS_REG_BASE,
+ WBOOT_REG_BASE,
+ TU0_US_REG_BASE,
+ TU1_US_REG_BASE,
+ TU2_US_REG_BASE,
+ TU3_US_REG_BASE,
+ TM0_MS_REG_BASE,
+ TM1_MS_REG_BASE,
+ TM2_MS_REG_BASE,
+ TM3_MS_REG_BASE,
+ MCU_WDT_REG_BASE,
+ SYS_WDT_REG_BASE,
+ GPIO_REG_BASE,
+ SD_REG_BASE,
+ SPI_REG_BASE,
+ CSR_I2C_MST_BASE,
+ UART_REG_BASE,
+ DAT_UART_REG_BASE,
+ INT_REG_BASE,
+ DBG_SPI_REG_BASE,
+ FLASH_SPI_REG_BASE,
+ DMA_REG_BASE,
+ CSR_PMU_BASE,
+ CSR_RTC_BASE,
+ RTC_RAM_BASE,
+ D2_DMA_REG_BASE,
+ HCI_REG_BASE,
+ CO_REG_BASE,
+ EFS_REG_BASE,
+ SMS4_REG_BASE,
+ MRX_REG_BASE,
+ AMPDU_REG_BASE,
+ MT_REG_CSR_BASE,
+ TXQ0_MT_Q_REG_CSR_BASE,
+ TXQ1_MT_Q_REG_CSR_BASE,
+ TXQ2_MT_Q_REG_CSR_BASE,
+ TXQ3_MT_Q_REG_CSR_BASE,
+ TXQ4_MT_Q_REG_CSR_BASE,
+ HIF_INFO_BASE,
+ PHY_RATE_INFO_BASE,
+ MAC_GLB_SET_BASE,
+ BTCX_REG_BASE,
+ MIB_REG_BASE,
+ CBR_A_REG_BASE,
+ MB_REG_BASE,
+ ID_MNG_REG_BASE,
+ CSR_PHY_BASE,
+ CSR_RF_BASE,
+ MMU_REG_BASE,
+ 0x00000000
+};
+static const char* STR_BANK_SSV6200[] = {
+ "SYS_REG",
+ "WBOOT_REG",
+ "TU0_US_REG",
+ "TU1_US_REG",
+ "TU2_US_REG",
+ "TU3_US_REG",
+ "TM0_MS_REG",
+ "TM1_MS_REG",
+ "TM2_MS_REG",
+ "TM3_MS_REG",
+ "MCU_WDT_REG",
+ "SYS_WDT_REG",
+ "GPIO_REG",
+ "SD_REG",
+ "SPI_REG",
+ "CSR_I2C_MST",
+ "UART_REG",
+ "DAT_UART_REG",
+ "INT_REG",
+ "DBG_SPI_REG",
+ "FLASH_SPI_REG",
+ "DMA_REG",
+ "CSR_PMU",
+ "CSR_RTC",
+ "RTC_RAM",
+ "D2_DMA_REG",
+ "HCI_REG",
+ "CO_REG",
+ "EFS_REG",
+ "SMS4_REG",
+ "MRX_REG",
+ "AMPDU_REG",
+ "MT_REG_CSR",
+ "TXQ0_MT_Q_REG_CSR",
+ "TXQ1_MT_Q_REG_CSR",
+ "TXQ2_MT_Q_REG_CSR",
+ "TXQ3_MT_Q_REG_CSR",
+ "TXQ4_MT_Q_REG_CSR",
+ "HIF_INFO",
+ "PHY_RATE_INFO",
+ "MAC_GLB_SET",
+ "BTCX_REG",
+ "MIB_REG",
+ "CBR_A_REG",
+ "MB_REG",
+ "ID_MNG_REG",
+ "CSR_PHY",
+ "CSR_RF",
+ "MMU_REG",
+ ""
+};
+static const u32 SIZE_BANK_SSV6200[] = {
+ SYS_REG_BANK_SIZE,
+ WBOOT_REG_BANK_SIZE,
+ TU0_US_REG_BANK_SIZE,
+ TU1_US_REG_BANK_SIZE,
+ TU2_US_REG_BANK_SIZE,
+ TU3_US_REG_BANK_SIZE,
+ TM0_MS_REG_BANK_SIZE,
+ TM1_MS_REG_BANK_SIZE,
+ TM2_MS_REG_BANK_SIZE,
+ TM3_MS_REG_BANK_SIZE,
+ MCU_WDT_REG_BANK_SIZE,
+ SYS_WDT_REG_BANK_SIZE,
+ GPIO_REG_BANK_SIZE,
+ SD_REG_BANK_SIZE,
+ SPI_REG_BANK_SIZE,
+ CSR_I2C_MST_BANK_SIZE,
+ UART_REG_BANK_SIZE,
+ DAT_UART_REG_BANK_SIZE,
+ INT_REG_BANK_SIZE,
+ DBG_SPI_REG_BANK_SIZE,
+ FLASH_SPI_REG_BANK_SIZE,
+ DMA_REG_BANK_SIZE,
+ CSR_PMU_BANK_SIZE,
+ CSR_RTC_BANK_SIZE,
+ RTC_RAM_BANK_SIZE,
+ D2_DMA_REG_BANK_SIZE,
+ HCI_REG_BANK_SIZE,
+ CO_REG_BANK_SIZE,
+ EFS_REG_BANK_SIZE,
+ SMS4_REG_BANK_SIZE,
+ MRX_REG_BANK_SIZE,
+ AMPDU_REG_BANK_SIZE,
+ MT_REG_CSR_BANK_SIZE,
+ TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+ HIF_INFO_BANK_SIZE,
+ PHY_RATE_INFO_BANK_SIZE,
+ MAC_GLB_SET_BANK_SIZE,
+ BTCX_REG_BANK_SIZE,
+ MIB_REG_BANK_SIZE,
+ CBR_A_REG_BANK_SIZE,
+ MB_REG_BANK_SIZE,
+ ID_MNG_REG_BANK_SIZE,
+ CSR_PHY_BANK_SIZE,
+ CSR_RF_BANK_SIZE,
+ MMU_REG_BANK_SIZE,
+ 0x00000000
+};
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h
new file mode 100644
index 000000000..1b54798cd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV6XXX_H_
+#define _SSV6XXX_H_
+#include
+#include
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include
+#endif
+#ifdef ECLIPSE
+#include
+#endif
+#include "ssv6xxx_common.h"
+#ifndef SSV_SUPPORT_HAL
+#include
+#include
+#endif
+#include
+#include
+#ifdef SSV6200_ECO
+#define SSV6200_TOTAL_ID 128
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD 115
+#define SSV6XXX_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 63
+#define SSV6200_ID_RX_THRESHOLD 63
+#ifdef PREFER_RX
+#define SSV6200_PAGE_TX_THRESHOLD (126-24)
+#define SSV6200_PAGE_RX_THRESHOLD (126+24)
+#else
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#define SSV6200_PAGE_TX_THRESHOLD 126
+#define SSV6200_PAGE_RX_THRESHOLD 126
+#endif
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD/2)
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (128)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+ u32 txUsePage:8;
+ u32 txUseID:6;
+ u32 edca0:4;
+ u32 edca1:4;
+ u32 edca2:5;
+ u32 edca3:5;
+};
+#include "ssv_cfg.h"
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h
new file mode 100644
index 000000000..f3a3789d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef __SSV6XXX_COMMON_H__
+#define __SSV6XXX_COMMON_H__
+#include
+#define SSV_RC_MAX_HARDWARE_SUPPORT 1
+#define RC_FIRMWARE_REPORT_FLAG 0x80
+#define FIRWARE_NOT_MATCH_CODE 0xF1F1F1F1
+#define MAX_RX_PKT_RSVD 512
+#define MAX_FRAME_SIZE 2432
+#define MAX_FRAME_SIZE_DMG 4096
+#define HCI_RX_AGGR_SIZE 0x1b00
+#define MAX_HCI_RX_AGGR_SIZE (HCI_RX_AGGR_SIZE+MAX_FRAME_SIZE)
+#define RX_NORMAL_MODE 0x0001
+#define RX_HW_AGG_MODE 0x0002
+#define RX_HW_AGG_MODE_METH3 0x0004
+#define RX_BURSTREAD_MODE 0x0008
+#define RX_BURSTREAD_SZ_FROM_CMD 0x0001
+#define RX_BURSTREAD_SZ_MAX_FRAME 0x0002
+#define RX_BURSTREAD_SZ_MAX_FRAME_DMG 0x0003
+#define MAX_RX_BURSTREAD_CNT 3
+#define MAX_RX_BURSTREAD_LENGTH 1024
+#define LOG_TX_DESC 0x0001
+#define LOG_AMPDU_SSN 0x0002
+#define LOG_AMPDU_DBG 0x0004
+#define LOG_AMPDU_ERR 0x0008
+#define LOG_BEACON 0x0010
+#define LOG_RATE_CONTROL 0x0020
+#define LOG_RATE_REPORT 0x0040
+#define LOG_TX_FRAME 0x0080
+#define LOG_RX_DESC 0x0100
+#define LOG_HCI 0x0200
+#define LOG_HWIF 0x0400
+#define LOG_HAL 0x0800
+#define LOG_REGW 0x1000
+#define LOG_FLASH_BIN 0x2000
+#define MAX_AGGR_NUM (24)
+#define SSV62XX_TX_MAX_RATES 3
+struct fw_rc_retry_params {
+ u32 count:4;
+ u32 drate:6;
+ u32 crate:6;
+ u32 rts_cts_nav:16;
+ u32 frame_consume_time:10;
+ u32 dl_length:12;
+ u32 RSVD:10;
+} __attribute__((packed));
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6XXX_CHIP_ID_LENGTH (24)
+#define SSV6XXX_CHIP_ID_SHORT_LENGTH (8)
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define RATE_RPT 7
+#ifndef SSV_SUPPORT_HAL
+#define SSV6XXX_RX_DESC_LEN \
+ (sizeof(struct ssv6200_rx_desc) + \
+ sizeof(struct ssv6200_rxphy_info))
+#define SSV6XXX_TX_DESC_LEN \
+ (sizeof(struct ssv6200_tx_desc) + 0)
+#endif
+#define SSV6XXX_PKT_RUN_TYPE_NOTUSED 0x0
+#define SSV6XXX_PKT_RUN_TYPE_AMPDU_START 0x1
+#define SSV6XXX_PKT_RUN_TYPE_AMPDU_END 0x7f
+#define SSV6XXX_PKT_RUN_TYPE_NULLFUN 0x80
+typedef enum __PBuf_Type_E {
+ NOTYPE_BUF = 0,
+ TX_BUF = 1,
+ RX_BUF = 2
+} PBuf_Type_E;
+typedef struct cfg_host_cmd {
+ u32 len:16;
+ u32 c_type:3;
+ u32 RSVD0:5;
+ u32 h_cmd:8;
+ u32 cmd_seq_no;
+ union {
+ u32 dummy;
+ u8 dat8[0];
+ u16 dat16[0];
+ u32 dat32[0];
+ };
+} HDR_HostCmd;
+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
+#define HOST_CMD_DUMMY_LEN 4
+struct sdio_rxtput_cfg {
+ u32 size_per_frame;
+ u32 total_frames;
+};
+typedef enum {
+ SSV6XXX_HOST_CMD_START = 0,
+ SSV6XXX_HOST_CMD_LOG = 1,
+ SSV6XXX_HOST_CMD_PS = 2,
+ SSV6XXX_HOST_CMD_INIT_CALI = 3,
+ SSV6XXX_HOST_CMD_RX_TPUT = 4,
+ SSV6XXX_HOST_CMD_TX_TPUT = 5,
+ SSV6XXX_HOST_CMD_SMART_ICOMM = 6,
+ SSV6XXX_HOST_CMD_WSID_OP = 7,
+ SSV6XXX_HOST_CMD_SET_NOA = 8,
+ SSV6XXX_HOST_CMD_TX_POLL = 9,
+ SSV6XXX_HOST_CMD_SOFT_BEACON = 10,
+ SSV6XXX_HOST_CMD_MRX_MODE = 11,
+ SSV6XXX_HOST_SOC_CMD_MAXID = 12,
+} ssv6xxx_host_cmd_id;
+typedef struct cfg_host_event {
+ u32 len :16;
+ u32 c_type :3;
+ u32 RSVD0 :5;
+ u32 h_event :8;
+ u32 evt_seq_no;
+ u8 dat[0];
+} HDR_HostEvent;
+typedef enum {
+ SOC_EVT_CMD_RESP = 0,
+ SOC_EVT_SCAN_RESULT = 1,
+ SOC_EVT_DEAUTH = 2,
+ SOC_EVT_GET_REG_RESP = 3,
+ SOC_EVT_NO_BA = 4,
+ SOC_EVT_RC_MPDU_REPORT = 5,
+ SOC_EVT_RC_AMPDU_REPORT = 6,
+ SOC_EVT_LOG = 7,
+ SOC_EVT_NOA = 8,
+ SOC_EVT_USER_END = 9,
+ SOC_EVT_SDIO_TEST_COMMAND = 10,
+ SOC_EVT_RESET_HOST = 11,
+ SOC_EVT_SDIO_TXTPUT_RESULT = 12,
+ SOC_EVT_TXLOOPBK_RESULT = 13,
+ SOC_EVT_SMART_ICOMM = 14,
+ SOC_EVT_BEACON_LOSS = 15,
+ SOC_EVT_TX_STUCK_RESP = 16,
+ SOC_EVT_SW_BEACON_RESP = 17,
+ SOC_EVT_MAXID = 18,
+} ssv6xxx_soc_event;
+#ifdef CONFIG_P2P_NOA
+typedef enum {
+ SSV6XXX_NOA_START = 0,
+ SSV6XXX_NOA_STOP,
+} ssv6xxx_host_noa_event;
+struct ssv62xx_noa_evt {
+ u8 evt_id;
+ u8 vif;
+} __attribute__((packed));
+#endif
+enum SSV6XXX_WSID_SEC {
+ SSV6XXX_WSID_SEC_NONE = 0,
+ SSV6XXX_WSID_SEC_PAIRWISE = 1<<0,
+ SSV6XXX_WSID_SEC_GROUP = 1<<1,
+};
+enum SSV6XXX_RETURN_STATE {
+ SSV6XXX_STATE_OK,
+ SSV6XXX_STATE_NG,
+ SSV6XXX_STATE_MAX
+};
+#ifdef FW_WSID_WATCH_LIST
+enum SSV6XXX_WSID_OPS {
+ SSV6XXX_WSID_OPS_ADD,
+ SSV6XXX_WSID_OPS_DEL,
+ SSV6XXX_WSID_OPS_RESETALL,
+ SSV6XXX_WSID_OPS_ENABLE_CAPS,
+ SSV6XXX_WSID_OPS_DISABLE_CAPS,
+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
+ SSV6XXX_WSID_OPS_MAX
+};
+enum SSV6XXX_WSID_SEC_TYPE {
+ SSV6XXX_WSID_SEC_SW,
+ SSV6XXX_WSID_SEC_HW,
+ SSV6XXX_WSID_SEC_TYPE_MAX
+};
+struct ssv6xxx_wsid_params {
+ u8 cmd;
+ u8 wsid_idx;
+ u8 target_wsid[6];
+ u8 hw_security;
+};
+#endif
+enum SSV6XXX_TX_POLL_TYPE {
+ SSV6XXX_TX_POLL_START = 0,
+ SSV6XXX_TX_POLL_RESET = 1,
+ SSV6XXX_TX_POLL_STOP = 2
+};
+enum SSV6XXX_SOFT_BEACON_TYPE {
+ SSV6XXX_SOFT_BEACON_START = 0,
+ SSV6XXX_SOFT_BEACON_STOP = 1
+};
+enum SSV6XXX_MRX_MODE_TYPE {
+ SSV6XXX_MRX_NORMAL = 0,
+ SSV6XXX_MRX_PROMISCUOUS = 1
+};
+struct ssv6xxx_iqk_cfg {
+ u32 cfg_xtal :8;
+ u32 cfg_pa :8;
+ u32 cfg_pabias_ctrl :8;
+ u32 cfg_pacascode_ctrl :8;
+ u32 cfg_tssi_trgt :8;
+ u32 cfg_tssi_div :8;
+ u32 cfg_def_tx_scale_11b :8;
+ u32 cfg_def_tx_scale_11b_p0d5 :8;
+ u32 cfg_def_tx_scale_11g :8;
+ u32 cfg_def_tx_scale_11g_p0d5 :8;
+ u32 cmd_sel;
+ union {
+ u32 fx_sel;
+ u32 argv;
+ };
+ u32 phy_tbl_size;
+ u32 rf_tbl_size;
+};
+#define PHY_SETTING_SIZE sizeof(phy_setting)
+struct ssv6xxx_ch_cfg {
+ u32 reg_addr;
+ u32 ch1_12_value;
+ u32 ch13_14_value;
+};
+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
+#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
+#define MAX_PHY_SETTING_TABLE_SIZE 1920
+#define MAX_RF_SETTING_TABLE_SIZE 512
+typedef enum {
+ SSV6XXX_VOLT_DCDC_CONVERT = 0,
+ SSV6XXX_VOLT_LDO_CONVERT = 1,
+} ssv6xxx_cfg_volt;
+typedef enum {
+ SSV6XXX_VOLT_33V = 0,
+ SSV6XXX_VOLT_42V,
+} ssv6xxx_cfg_volt_value;
+typedef enum {
+ SSV6XXX_IQK_CFG_XTAL_26M = 0,
+ SSV6XXX_IQK_CFG_XTAL_40M,
+ SSV6XXX_IQK_CFG_XTAL_24M,
+ SSV6XXX_IQK_CFG_XTAL_25M,
+ SSV6XXX_IQK_CFG_XTAL_12M,
+ SSV6XXX_IQK_CFG_XTAL_16M,
+ SSV6XXX_IQK_CFG_XTAL_20M,
+ SSV6XXX_IQK_CFG_XTAL_32M,
+ SSV6XXX_IQK_CFG_XTAL_MAX,
+} ssv6xxx_iqk_cfg_xtal;
+typedef enum {
+ SSV6XXX_IQK_CFG_PA_DEF = 0,
+ SSV6XXX_IQK_CFG_PA_LI_MPB,
+ SSV6XXX_IQK_CFG_PA_LI_EVB,
+ SSV6XXX_IQK_CFG_PA_HP,
+} ssv6xxx_iqk_cfg_pa;
+typedef enum {
+ SSV6XXX_IQK_CMD_INIT_CALI = 0,
+ SSV6XXX_IQK_CMD_RTBL_LOAD,
+ SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
+ SSV6XXX_IQK_CMD_RTBL_RESET,
+ SSV6XXX_IQK_CMD_RTBL_SET,
+ SSV6XXX_IQK_CMD_RTBL_EXPORT,
+ SSV6XXX_IQK_CMD_TK_EVM,
+ SSV6XXX_IQK_CMD_TK_TONE,
+ SSV6XXX_IQK_CMD_TK_CHCH,
+} ssv6xxx_iqk_cmd_sel;
+#define SSV6XXX_IQK_TEMPERATURE 0x00000004
+#define SSV6XXX_IQK_RXDC 0x00000008
+#define SSV6XXX_IQK_RXRC 0x00000010
+#define SSV6XXX_IQK_TXDC 0x00000020
+#define SSV6XXX_IQK_TXIQ 0x00000040
+#define SSV6XXX_IQK_RXIQ 0x00000080
+#define SSV6XXX_IQK_TSSI 0x00000100
+#define SSV6XXX_IQK_PAPD 0x00000200
+typedef struct ssv_cabrio_reg_st {
+ u32 address;
+ u32 data;
+} ssv_cabrio_reg;
+#ifdef MULTI_THREAD_ENCRYPT
+enum ssv_pkt_crypt_status {
+ PKT_CRYPT_ST_DEC_PRE,
+ PKT_CRYPT_ST_ENC_PRE,
+ PKT_CRYPT_ST_DEC_DONE,
+ PKT_CRYPT_ST_ENC_DONE,
+ PKT_CRYPT_ST_FAIL,
+ PKT_CRYPT_ST_NOT_SUPPORT
+};
+#endif
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+#define SKB_DURATION_TIMEOUT_MS 100
+enum ssv_debug_skb_timestamp {
+ SKB_DURATION_STAGE_TX_ENQ,
+ SKB_DURATION_STAGE_TO_SDIO,
+ SKB_DURATION_STAGE_IN_HWQ,
+ SKB_DURATION_STAGE_END
+};
+#endif
+
+#define SSV_FIRMWARE_PATH_MAX 256
+#define SSV_FIRMWARE_MAX 32
+#ifdef CONFIG_SSV_SMARTLINK
+enum ssv_smart_icomm_cmd {
+ STOP_SMART_ICOMM,
+ START_SMART_ICOMM,
+ RESET_SMART_ICOMM,
+ MAX_SMART_ICOMM
+};
+struct ssv6xxx_si_cfg {
+ u8 ssid[32];
+ u8 password[64];
+ s32 ssid_len;
+ s32 password_len;
+} __attribute__((packed));
+#endif
+#ifdef CONFIG_SSV_CABRIO_E
+struct ssv6xxx_tx_loopback {
+ u32 reg;
+ u32 val;
+ u32 restore_val;
+ u8 restore;
+ u8 delay_ms;
+};
+#endif
+struct hci_rx_aggr_info {
+ u32 jmp_mpdu_len:16;
+ u32 accu_rx_len:16;
+ u32 RSVD0:15;
+ u32 tx_page_remain:9;
+ u32 tx_id_remain:8;
+ u32 edca0:4;
+ u32 edca1:5;
+ u32 edca2:5;
+ u32 edca3:5;
+ u32 edca4:4;
+ u32 edca5:5;
+ u32 RSVD1:4;
+} __attribute__((packed));
+struct ssv6xxx_tx_hw_info {
+ u32 tx_id_threshold;
+ u32 tx_page_threshold;
+ u32 tx_lowthreshold_page_trigger;
+ u32 tx_lowthreshold_id_trigger;
+ u32 bk_txq_size;
+ u32 be_txq_size;
+ u32 vi_txq_size;
+ u32 vo_txq_size;
+ u32 manage_txq_size;
+};
+struct ssv6xxx_rx_hw_info {
+ u32 rx_id_threshold;
+ u32 rx_page_threshold;
+ u32 rx_ba_ma_sessions;
+};
+#define ENABLE_FW_SELF_CHECK 1
+#define FW_START_SRAM_ADDR 0x00000000
+#define FW_BLOCK_SIZE 0x8000
+#define CHECKSUM_BLOCK_SIZE 1024
+#define FW_CHECKSUM_INIT (0x12345678)
+#define FW_STATUS_MASK (0x00FF0000)
+enum SSV_SRAM_MODE {
+ SRAM_MODE_ILM_64K_DLM_128K = 0,
+ SRAM_MODE_ILM_160K_DLM_32K,
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h b/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h
new file mode 100644
index 000000000..b085cff10
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV_CFG_H_
+#define _SSV_CFG_H_
+#define SSV6200_HW_CAP_HT 0x00000001
+#define SSV6200_HW_CAP_GF 0x00000002
+#define SSV6200_HW_CAP_2GHZ 0x00000004
+#define SSV6200_HW_CAP_5GHZ 0x00000008
+#define SSV6200_HW_CAP_SECURITY 0x00000010
+#define SSV6200_HW_CAP_SGI 0x00000020
+#define SSV6200_HW_CAP_HT40 0x00000040
+#define SSV6200_HW_CAP_AP 0x00000080
+#define SSV6200_HW_CAP_P2P 0x00000100
+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
+#define SSV6200_HW_CAP_TDLS 0x00000800
+#define SSV6200_HW_CAP_STBC 0x00001000
+#define SSV6200_HW_CAP_HCI_RX_AGGR 0x00002000
+#define SSV6200_HW_CAP_BEACON 0x00004000
+#define EXTERNEL_CONFIG_SUPPORT 64
+#define USB_HW_RESOURCE_CHK_NONE 0x00000000
+#define USB_HW_RESOURCE_CHK_TXID 0x00000001
+#define USB_HW_RESOURCE_CHK_TXPAGE 0x00000002
+#define USB_HW_RESOURCE_CHK_SCAN 0x00000004
+#define USB_HW_RESOURCE_CHK_FORCE_OFF 0x00000008
+#define ONLINE_RESET_ENABLE 0x00000100
+#define ONLINE_RESET_EDCA_THRESHOLD_MASK 0x000000ff
+#define ONLINE_RESET_EDCA_THRESHOLD_SFT 0
+
+
+enum ssv_reg_domain {
+ DOMAIN_FCC = 0,
+ DOMAIN_china,
+ DOMAIN_ETSI,
+ DOMAIN_Japan,
+ DOMAIN_Japan2,
+ DOMAIN_Israel,
+ DOMAIN_Korea,
+ DOMAIN_North_America,
+ DOMAIN_Singapore,
+ DOMAIN_Taiwan,
+ DOMAIN_other = 0xff,
+};
+
+
+
+
+struct rc_setting {
+ u16 aging_period;
+ u16 target_success_67;
+ u16 target_success_5;
+ u16 target_success_4;
+ u16 target_success;
+ u16 up_pr;
+ u16 up_pr3;
+ u16 up_pr4;
+ u16 up_pr5;
+ u16 up_pr6;
+ u16 forbid;
+ u16 forbid3;
+ u16 forbid4;
+ u16 forbid5;
+ u16 forbid6;
+ u16 sample_pr_4;
+ u16 sample_pr_5;
+ u16 force_sample_pr;
+};
+struct ssv6xxx_cfg {
+ u32 hw_caps;
+ u32 def_chan;
+ u32 crystal_type;
+ u32 volt_regulator;
+ u32 force_chip_identity;
+ u32 ignore_firmware_version;
+ u8 maddr[2][6];
+ u32 n_maddr;
+ u32 use_sw_cipher;
+ u32 use_wpa2_only;
+ u32 online_reset;
+ bool tx_stuck_detect;
+ u32 r_calbration_result;
+ u32 sar_result;
+ u32 crystal_frequency_offset;
+ u32 tx_power_index_1;
+ u32 tx_power_index_2;
+ u32 chip_identity;
+ u32 rate_table_1;
+ u32 rate_table_2;
+ u32 wifi_tx_gain_level_gn;
+ u32 wifi_tx_gain_level_b;
+ u32 configuration[EXTERNEL_CONFIG_SUPPORT+1][2];
+ u8 firmware_path[128];
+ u8 flash_bin_path[128];
+ u8 external_firmware_name[128];
+ u8 mac_address_path[128];
+ u8 mac_output_path[128];
+ u32 ignore_efuse_mac;
+ u32 efuse_rate_gain_mask;
+ u32 mac_address_mode;
+ u32 beacon_rssi_minimal;
+ u32 rc_ht_support_cck;
+ u32 auto_rate_enable;
+ u32 rc_rate_idx_set;
+ u32 rc_retry_set;
+ u32 rc_mf;
+ u32 rc_long_short;
+ u32 rc_ht40;
+ u32 rc_phy_mode;
+ u32 rc_log;
+ u32 tx_id_threshold;
+ u32 tx_page_threshold;
+ u32 max_rx_aggr_size;
+ bool rx_burstread;
+ u32 hw_rx_agg_cnt;
+ bool hw_rx_agg_method_3;
+ u32 hw_rx_agg_timer_reload;
+ u32 usb_hw_resource;
+ u32 lpbk_pkt_cnt;
+ u32 lpbk_type;
+ u32 lpbk_sec;
+ u32 lpbk_mode;
+ bool clk_src_80m;
+ u32 rts_thres_len;
+ u32 cci;
+ u32 bk_txq_size;
+ u32 be_txq_size;
+ u32 vi_txq_size;
+ u32 vo_txq_size;
+ u32 manage_txq_size;
+ u32 aggr_size_sel_pr;
+ u32 greentx;
+ u32 gt_stepsize;
+ u32 gt_max_attenuation;
+ struct rc_setting rc_setting;
+ u32 directly_ack_low_threshold;
+ u32 directly_ack_high_threshold;
+ u32 txrxboost_prio;
+ u32 txrxboost_low_threshold;
+ u32 txrxboost_high_threshold;
+ u32 rx_threshold;
+ bool force_xtal_fo;
+ u32 auto_sgi;
+ u32 disable_dpd;
+ u32 mic_err_notify;
+ u32 domain;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h b/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h
new file mode 100644
index 000000000..965bcfd3f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h
@@ -0,0 +1,30 @@
+#ifndef __SSV_CHIP_ID_H__
+#define __SSV_CHIP_ID_H__
+#define SSV6051_CHIP "SSV6200A0"
+#define SSV6051_CHIP_ECO3 "RSV6200A0"
+#define SSV6200A "SSV6200A"
+#define RSV6200A "RSV6200A"
+#define SSV6006A "SSV6006A"
+#define SSV6006C "SSV6006C"
+#define SSV6006D "SSV6006D"
+#define SSV6006 "SSV6006A0"
+#define SSV6006MP "SSV6006C0"
+#define SSV6166 "SSV6006D0"
+#define SSV6006D1 "SSV6006D1"
+#define SSV6006D2 "SSV6006D2"
+#define SSV6006D3 "SSV6006D3"
+#define SSV6051Q_P1 0x00000000
+#define SSV6051Q_P2 0x70000000
+#define SSV6051Z 0x71000000
+#define SSV6051Q 0x73000000
+#define SSV6051P 0x75000000
+#define SV6155P 0x70000000
+#define SV6156P 0x71000000
+#define SV6166P 0x72000000
+#define SV6151P_SV6152P 0x73000000
+#define SV6167Q 0x74000000
+#define SV6166F 0x75000000
+#define SV6255P 0x78000000
+#define SV6256P 0x79000000
+#define SV6267Q 0x7C000000
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h b/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h
new file mode 100644
index 000000000..6c095e638
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h
@@ -0,0 +1,35 @@
+#ifndef __SSV_CONF_PARSER_H__
+#define __SSV_CONF_PARSER_H__
+char const *conf_parser[] = {
+"CONFIG_SSV_SUPPORT_ANDROID",
+"CONFIG_FW_ALIGNMENT_CHECK",
+"CONFIG_PLATFORM_SDIO_OUTPUT_TIMING_3",
+"CONFIG_PLATFORM_SDIO_BLOCK_SIZE_128",
+"MULTI_THREAD_ENCRYPT",
+"KTHREAD_BIND",
+"CONFIG_SSV_RSSI",
+"CONFIG_SSV_VENDOR_EXT_SUPPORT",
+"__CHECK_ENDIAN__",
+"SSV_SUPPORT_HAL",
+"SSV_SUPPORT_SSV6006",
+"CONFIG_SSV_CABRIO_E",
+"CONFIG_SSV6200_CLI_ENABLE",
+"CONFIG_SSV_TX_LOWTHRESHOLD",
+"RATE_CONTROL_REALTIME_UPDATE",
+"CONFIG_SSV6200_HAS_RX_WORKQUEUE",
+"USE_THREAD_RX",
+"USE_THREAD_TX",
+"ENABLE_AGGREGATE_IN_TIME",
+"ENABLE_INCREMENTAL_AGGREGATION",
+"USE_GENERIC_DECI_TBL",
+"USE_LOCAL_CRYPTO",
+"USE_LOCAL_WEP_CRYPTO",
+"USE_LOCAL_TKIP_CRYPTO",
+"USE_LOCAL_CCMP_CRYPTO",
+"USE_LOCAL_SMS4_CRYPTO",
+"CONFIG_SSV_WAPI",
+"HAS_CRYPTO_LOCK",
+"SSV6200_ECO",
+"CONFIG_SSV_CCI_IMPROVEMENT",
+""};
+#endif // __SSV_CONF_PARSER_H__
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h b/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h
new file mode 100644
index 000000000..893ab5eeb
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV_DATA_STRUCT_H_
+#define _SSV_DATA_STRUCT_H_
+#include
+#include
+#include
+struct ssv6xxx_queue {
+ struct list_head queue;
+ spinlock_t lock;
+};
+struct ssv6xxx_list_node {
+ struct list_head list;
+};
+static inline void tu_ssv6xxx_init_queue(struct ssv6xxx_queue *ssv_queue)
+{
+ INIT_LIST_HEAD(&ssv_queue->queue);
+ spin_lock_init(&ssv_queue->lock);
+}
+static inline void tu_ssv6xxx_init_list_node(struct ssv6xxx_list_node *node)
+{
+ INIT_LIST_HEAD(&node->list);
+}
+static inline void ssv6xxx_enqueue_list_node(struct ssv6xxx_list_node *node, struct ssv6xxx_queue *ssv_queue)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&ssv_queue->lock, flags);
+ list_del_init(&node->list);
+ list_add_tail(&node->list, &ssv_queue->queue);
+ spin_unlock_irqrestore(&ssv_queue->lock, flags);
+}
+static inline struct ssv6xxx_list_node *ssv6xxx_dequeue_list_node(struct ssv6xxx_queue *ssv_queue)
+{
+ unsigned long flags;
+ struct ssv6xxx_list_node *ssv_list_node;
+ spin_lock_irqsave(&ssv_queue->lock, flags);
+ if (list_empty(&ssv_queue->queue)) {
+ ssv_list_node = NULL;
+ } else {
+ ssv_list_node = container_of((&ssv_queue->queue)->next, struct ssv6xxx_list_node, list);
+ list_del_init(&ssv_list_node->list);
+ }
+ spin_unlock_irqrestore(&ssv_queue->lock, flags);
+ return ssv_list_node;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h
new file mode 100644
index 000000000..7185a6b33
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _SSV_FRIMWARE_VERSION_H_
+#define _SSV_FRIMWARE_VERSION_H_
+static u32 ssv_firmware_version = 17215;
+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/SMAC.0000.1807/ssv6x5x/smac/hal/ssv6006/firmware"
+#define FRIMWARE_COMPILERHOST "willlu-Latitude-E5440"
+#define FRIMWARE_COMPILERDATE "08-09-2018-14:24:22"
+#define FRIMWARE_COMPILEROS "linux"
+#define FRIMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h b/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h
new file mode 100755
index 000000000..0744939e8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h
@@ -0,0 +1,86 @@
+#ifndef __SSV_MOD_CONF_H__
+#define __SSV_MOD_CONF_H__
+#ifndef __CHECK_ENDIAN__
+#define __CHECK_ENDIAN__
+#endif
+#ifndef DEBUG
+#define DEBUG
+#endif
+#ifndef SSV_SUPPORT_HAL
+#define SSV_SUPPORT_HAL
+#endif
+#ifndef SSV_SUPPORT_SSV6006
+#define SSV_SUPPORT_SSV6006
+#endif
+#ifndef CONFIG_SSV_CABRIO_E
+#define CONFIG_SSV_CABRIO_E
+#endif
+#ifndef CONFIG_SSV6200_CLI_ENABLE
+#define CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifndef CONFIG_SSV_TX_LOWTHRESHOLD
+#define CONFIG_SSV_TX_LOWTHRESHOLD
+#endif
+#ifndef RATE_CONTROL_REALTIME_UPDATE
+#define RATE_CONTROL_REALTIME_UPDATE
+#endif
+#ifndef CONFIG_SSV6200_HAS_RX_WORKQUEUE
+#define CONFIG_SSV6200_HAS_RX_WORKQUEUE
+#endif
+#ifndef USE_THREAD_RX
+#define USE_THREAD_RX
+#endif
+#ifndef USE_THREAD_TX
+#define USE_THREAD_TX
+#endif
+#ifndef ENABLE_AGGREGATE_IN_TIME
+#define ENABLE_AGGREGATE_IN_TIME
+#endif
+#ifndef ENABLE_INCREMENTAL_AGGREGATION
+#define ENABLE_INCREMENTAL_AGGREGATION
+#endif
+#ifndef USE_GENERIC_DECI_TBL
+#define USE_GENERIC_DECI_TBL
+#endif
+#ifndef USE_LOCAL_CRYPTO
+#define USE_LOCAL_CRYPTO
+#endif
+#ifndef USE_LOCAL_WEP_CRYPTO
+#define USE_LOCAL_WEP_CRYPTO
+#endif
+#ifndef USE_LOCAL_TKIP_CRYPTO
+#define USE_LOCAL_TKIP_CRYPTO
+#endif
+#ifndef USE_LOCAL_CCMP_CRYPTO
+#define USE_LOCAL_CCMP_CRYPTO
+#endif
+#ifndef USE_LOCAL_SMS4_CRYPTO
+#define USE_LOCAL_SMS4_CRYPTO
+#endif
+#ifndef CONFIG_SSV_WAPI
+#define CONFIG_SSV_WAPI
+#endif
+#ifndef HAS_CRYPTO_LOCK
+#define HAS_CRYPTO_LOCK
+#endif
+#ifndef SSV6200_ECO
+#define SSV6200_ECO
+#endif
+#ifndef CONFIG_SSV_CCI_IMPROVEMENT
+#define CONFIG_SSV_CCI_IMPROVEMENT
+#endif
+#ifndef REPORT_TX_STATUS_DIRECTLY
+#define REPORT_TX_STATUS_DIRECTLY
+#endif
+#ifndef CONFIG_IRQ_DEBUG_COUNT
+#define CONFIG_IRQ_DEBUG_COUNT
+#endif
+#ifndef CONFIG_SSV6XXX_DEBUGFS
+#define CONFIG_SSV6XXX_DEBUGFS
+#endif
+#define __must_check
+#define __devinit
+#define __devexit
+#define __init
+#define __exit
+#endif // __SSV_MOD_CONF_H__
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_version.h b/drivers/net/wireless/ssv6x5x/include/ssv_version.h
new file mode 100755
index 000000000..504f4256f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_version.h
@@ -0,0 +1,13 @@
+#ifndef _SSV_VERSION_H_
+#define _SSV_VERSION_H_
+
+static u32 ssv_root_version = 17680;
+
+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/SMAC.0000.1807.12.SPUR.90/ssv6x5x"
+#define COMPILERHOST "willlu-Latitude-E5440"
+#define COMPILERDATE "07-04-2019-17:27:36"
+#define COMPILEROS "linux"
+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+
+#endif
+
diff --git a/drivers/net/wireless/ssv6x5x/kmsg.sh b/drivers/net/wireless/ssv6x5x/kmsg.sh
new file mode 100755
index 000000000..b8e2fc7f8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/kmsg.sh
@@ -0,0 +1,2 @@
+#/bin/bash
+tail -f /var/log/kern.log
diff --git a/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh b/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh
new file mode 100755
index 000000000..0b648890e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh
@@ -0,0 +1,129 @@
+#!/bin/bash
+
+HOSTPAD_DIR=../../../../3rd-party/hostapd/hostapd2.0/
+WPA_SUPPLICANT_DIR=../../../../3rd-party/wpa_supplicant-2.4/wpa_supplicant
+
+## unload ap
+service isc-dhcp-server stop
+killall dhcpd
+killall hostapd
+killall wpa_supplicant
+
+# load driver
+./load.sh
+
+# find wlan1
+ssv_wlan_1=`script/find_ssv_wlan`
+
+sleep 1
+
+ssv_phy=`script/find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+ echo SSV PHY device not found.;
+ exit 1;
+fi
+
+ssv_wlan_1=`script/find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+ echo SSV primary WLAN device not found.;
+ exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+# add wlan2
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type station
+
+sleep 1
+
+ssv_wlans="`script/find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+ if [ $ssv_wlan != $ssv_wlan_1 ]; then
+ echo Second SSV WLAN device is actually $ssv_wlan
+ break;
+ fi
+done
+
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+#rm -rf load_dhcp.sh
+#rm -rf hostapd.conf
+#relpace wlan@@ to real device name
+cp script/template/load_dhcp.sh load_dhcp.sh
+
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$ssv_wlan_1/" load_dhcp.sh
+sed -i "s/wlan@@/$ssv_wlan_1/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+#move to right position
+#mv load_dhcp.sh $HOSTPAD_DIR
+#mv hostapd.conf $HOSTPAD_DIR/hostapd/
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$ssv_wlan_1" $dhcp_config_file)
+if [ "$dhcp_config" == "" ]; then
+ echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+
+ rm -rf tmp
+ sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+ echo "INTERFACES=\"$ssv_wlan_1\"" >>tmp
+ rm -rf $dhcp_config_file
+ mv tmp /etc/default/isc-dhcp-server
+
+ echo -e "${YELLOW}OK${NC}"
+fi
+
+
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+# popd
+ if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi on
+ else
+ nmcli nm wifi on
+ fi
+
+ echo -e "${YELLOW}Shutting down AP.${NC}"
+ ./ap_shutdown.sh
+}
+
+
+if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi off
+else
+ nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+./load_dhcp.sh &
+
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd/hostapd -t hostapd.conf &
+#hostapd -t hostapd.conf
+
+ifconfig $ssv_wlan_2 192.168.1.33 up
+sleep 2
+#$WPA_SUPPLICANT_DIR/wpa_supplicant -Dnl80211 -i $ssv_wlan_2 -c ./wpa_supplicant.conf -dd -B -f /var/log/wpa_supplicant.log
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh b/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh
new file mode 100755
index 000000000..98dd4066c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh
@@ -0,0 +1,121 @@
+#!/bin/bash
+
+HOSTPAD_DIR=/home/liamhu/svn/3rd-party/hostapd/hostapd2.0
+WPA_SUPPLICANT_DIR=/home/liamhu/wpa_supplicant-2.4/wpa_supplicant
+
+## unload ap
+service isc-dhcp-server stop
+killall dhcpd
+killall hostapd
+killall wpa_supplicant
+
+# load driver
+./load.sh
+
+# find wlan1
+ssv_wlan_1=`script/find_ssv_wlan`
+
+sleep 1
+
+ssv_phy=`script/find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+ echo SSV PHY device not found.;
+ exit 1;
+fi
+
+ssv_wlan_1=`script/find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+ echo SSV primary WLAN device not found.;
+ exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+# add wlan2
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type station
+
+sleep 1
+
+ssv_wlans="`script/find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+ if [ $ssv_wlan != $ssv_wlan_1 ]; then
+ echo Second SSV WLAN device is actually $ssv_wlan
+ break;
+ fi
+done
+
+ifconfig $ssv_wlan_1 192.168.1.33 up
+sleep 2
+$WPA_SUPPLICANT_DIR/wpa_supplicant -Dnl80211 -i $ssv_wlan_1 -c ./wpa_supplicant.conf -dd -B -f /var/log/wpa_supplicant.log
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+
+cp script/template/load_dhcp.sh load_dhcp.sh
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$ssv_wlan/" load_dhcp.sh
+sed -i "s/wlan@@/$ssv_wlan/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$ssv_wlan" $dhcp_config_file)
+if [ "$dhcp_config" == "" ]; then
+ echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+
+ rm -rf tmp
+ sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+ echo "INTERFACES=\"$ssv_wlan\"" >>tmp
+ rm -rf $dhcp_config_file
+ mv tmp /etc/default/isc-dhcp-server
+
+ echo -e "${YELLOW}OK${NC}"
+fi
+
+
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+# popd
+ if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi on
+ else
+ nmcli nm wifi on
+ fi
+
+ echo -e "${YELLOW}Shutting down AP.${NC}"
+ ./ap_shutdown.sh
+}
+
+
+if version_great $nmcli_version $chk_nmcli_version; then
+ nmcli radio wifi off
+else
+ nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+./load_dhcp.sh &
+
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd/hostapd -t hostapd.conf
+
diff --git a/drivers/net/wireless/ssv6x5x/linux-build.sh b/drivers/net/wireless/ssv6x5x/linux-build.sh
new file mode 100755
index 000000000..75f909e49
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/linux-build.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+ "a64" \
+ "h8" \
+ "h3")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do
+ case "$REPLY" in
+
+ 1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+ 4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+ $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+ *) echo "Invalid option. Try another one.";continue;;
+ esac
+done
+
+echo ${chip_options[$REPLY-1]}
+echo $PLATFORM
+exit 0
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+cp Makefile.cross_linux Makefile
+cp platforms/${chip_options[$REPLY-1]}.cfg ssv6051.cfg
+cp platforms/platform-config.mak platform-config.mak
+cp platforms/${chip_options[$REPLY-1]}-generic-wlan.c ssv6051-generic-wlan.c
+cp platforms/${chip_options[$REPLY-1]}-wifi.cfg ssv6051-wifi.cfg
+rm -rf platforms
+echo "Done Makefile!"
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/load.sh b/drivers/net/wireless/ssv6x5x/load.sh
new file mode 100755
index 000000000..d3682659c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/load.sh
@@ -0,0 +1,33 @@
+#/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload.sh
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+./ssvcfg.sh
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+
+modprobe sdhci-pci
+modprobe sdhci
+
+modprobe mmc_core sdiomaxclock=25000000
+modprobe mmc_block
+
+modprobe ssv6200_usb
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+#modprobe ssv6200_sdio
+
diff --git a/drivers/net/wireless/ssv6x5x/parser-conf.sh b/drivers/net/wireless/ssv6x5x/parser-conf.sh
new file mode 100755
index 000000000..796845d14
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/parser-conf.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+# Script to convert defines in compiler option in to C's defines
+# Should be executed in make file and it take ccflags-y as the
+# compiler options. The content will be redirected to the first arguement.
+
+temp=$1_temp
+
+echo "#ifndef __SSV_CONF_PARSER_H__" > $temp
+echo "#define __SSV_CONF_PARSER_H__" >> $temp
+
+echo "char const *conf_parser[] = {" >> $temp
+
+for flag in ${ccflags-y}; do
+ if [[ "$flag" =~ ^-D.* ]]; then
+ def=${flag:2}
+ if [[ "$def" =~ .= ]]; then
+ def_1=${def/\=/_}
+ echo "\"$def_1\"," >> $temp
+ else
+ echo "\"$def\"," >> $temp
+ fi
+ fi
+done
+
+echo "\"\"};" >> $temp
+
+echo "#endif // __SSV_CONF_PARSER_H__" >> $temp
+
+DIFF=$(diff $1 $temp)
+if [ "$DIFF" == "" ]; then
+ rm $temp
+else
+ mv $temp $1
+fi
diff --git a/drivers/net/wireless/ssv6x5x/platform-config.mak b/drivers/net/wireless/ssv6x5x/platform-config.mak
new file mode 100755
index 000000000..fccd042e2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platform-config.mak
@@ -0,0 +1,7 @@
+
+include $(KBUILD_TOP)/config_common.mak
+
+# SDIO delay chain
+#ccflags-y += -D CONFIG_SSV_SDIO_INPUT_DELAY=0x00000000
+#ccflags-y += -D CONFIG_SSV_SDIO_OUTPUT_DELAY=0x00000000
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c
new file mode 100644
index 000000000..3798964fa
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_HAS_WAKELOCK
+#include
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include
+#else
+struct wifi_platform_data {
+ int (*set_power)(int val);
+ int (*set_reset)(int val);
+ int (*set_carddetect)(int val);
+ void *(*mem_prealloc)(int section, unsigned long size);
+ int (*get_mac_addr)(unsigned char *buf);
+ void *(*get_country_code)(char *ccode);
+};
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+struct wake_lock icomm_wake_lock;
+#endif
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+#ifdef SSV_WAKEUP_HOST
+static unsigned int g_wifi_irq_rc = 0;
+#endif
+static int sdc_id = -1;
+#define SDIO_ID 1
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+extern int wifi_pm_gpio_ctrl(char *name, int level);
+extern int enable_wakeup_src(cpu_wakeup_src_e src, int para);
+extern int disable_wakeup_src(cpu_wakeup_src_e src, int para);
+extern void wifi_pm_power(int on);
+static int ssv_wifi_power(int on)
+{
+ printk("ssv pwr on=%d\n", on);
+ if (on) {
+ wifi_pm_power(0);
+ mdelay(50);
+ wifi_pm_power(1);
+ } else {
+ wifi_pm_power(0);
+ }
+ return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+ return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+ sunxi_mci_rescan_card(sdc_id, val);
+ return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+ .set_power = ssv_wifi_power,
+ .set_reset = ssv_wifi_reset,
+ .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+ {
+ .start = WIFI_HOST_WAKE,
+ .flags = IORESOURCE_IRQ,
+ .name = IRQ_RES_NAME,
+ },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+ printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+ .name = "ssv_wlan",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(resources),
+ .resource = resources,
+ .dev = {
+ .platform_data = &ssv_wifi_control,
+ .release = ssv_wifi_device_release,
+ },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_power) {
+ wifi_control_data->set_power(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_reset) {
+ wifi_control_data->set_reset(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+ if (wifi_control_data && wifi_control_data->set_carddetect) {
+ wifi_control_data->set_carddetect(on);
+ }
+ return 0;
+}
+#ifdef SSV_WAKEUP_HOST
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+ wake_lock_timeout(&icomm_wake_lock, HZ);
+ printk("***** %s ******\n", __func__);
+ return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+ int ret = 0;
+ unsigned int oob_irq;
+ unsigned gpio_eint_wlan = 0;
+ bool enable = bEnable;
+ script_item_u val;
+ script_item_value_type_e type;
+ int wakeup_src_cnt = 0;
+ script_item_u *list = NULL;
+ wakeup_src_cnt = script_get_pio_list("wakeup_src_para", &list);
+ pr_err("wakeup src cnt is : %d. \n", wakeup_src_cnt);
+ type = script_get_item("wifi_para", "ssv6051_wl_host_wake", &val);
+ if (SCIRPT_ITEM_VALUE_TYPE_PIO != type || !enable) {
+ printk("No definition of wake up host PIN\n");
+ enable = false;
+ } else {
+ printk("WiFi wake up host PIN:%d=0x%x\n", val.gpio.gpio, val.gpio.gpio);
+ gpio_eint_wlan = val.gpio.gpio;
+ oob_irq = gpio_to_irq(gpio_eint_wlan);
+ }
+ if (enable) {
+ printk("%s: enable irq\n", __FUNCTION__);
+ g_wifi_irq_rc = oob_irq;
+ ret = request_threaded_irq(
+ oob_irq, NULL, (void *)wifi_wakeup_irq_handler,
+ IRQ_TYPE_EDGE_FALLING,
+ "wlan_wakeup_irq", NULL);
+ enable_irq_wake(g_wifi_irq_rc);
+ } else {
+ if (g_wifi_irq_rc) {
+ free_irq(g_wifi_irq_rc, NULL);
+ g_wifi_irq_rc = 0;
+ }
+ }
+}
+#endif
+static int wifi_probe(struct platform_device *pdev)
+{
+ script_item_u val;
+ script_item_value_type_e type;
+ int ret = 0;
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ printk(KERN_ALERT "wifi_probe\n");
+ wifi_control_data = wifi_ctrl;
+ type = script_get_item("wifi_para", "wifi_sdc_id", &val);
+ if (SCIRPT_ITEM_VALUE_TYPE_INT!=type) {
+ printk("get wifi_sdc_id failed\n");
+ ret = -1;
+ } else {
+ sdc_id = val.val;
+ }
+ wifi_set_power(0, 40);
+ wifi_set_power(1, 50);
+ wifi_set_carddetect(1);
+#ifdef SSV_WAKEUP_HOST
+ setup_wifi_wakeup_BB(pdev, true);
+#endif
+ up(&wifi_control_sem);
+ return ret;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ wifi_control_data = wifi_ctrl;
+#ifdef SSV_WAKEUP_HOST
+ setup_wifi_wakeup_BB(pdev, false);
+#endif
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_carddetect(0);
+ return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ printk("%s\n", __FUNCTION__);
+ return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+ printk("%s\n", __FUNCTION__);
+ sunxi_mci_rescan_card(sdc_id, 1);
+ wake_lock_timeout(&icomm_wake_lock, 5 * HZ);
+ return 0;
+}
+static struct platform_driver wifi_driver = {
+ .probe = wifi_probe,
+ .remove = wifi_remove,
+ .suspend = wifi_suspend,
+ .resume = wifi_resume,
+ .driver = {
+ .name = "ssv_wlan",
+ }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+ int ret = 0;
+#ifdef CONFIG_HAS_WAKELOCK
+ wake_lock_init(&icomm_wake_lock, WAKE_LOCK_SUSPEND, "ssv6051");
+ wake_lock(&icomm_wake_lock);
+#endif
+ sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ sha1_mod_init();
+ aes_init();
+#endif
+ platform_device_register(&ssv_wifi_device);
+ platform_driver_register(&wifi_driver);
+ g_wifidev_registered = 1;
+ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+ ret = -EINVAL;
+ printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+ }
+ ret = tu_ssvdevice_init();
+#ifdef CONFIG_HAS_WAKELOCK
+ wake_unlock(&icomm_wake_lock);
+#endif
+ return ret;
+}
+void exitWlan(void)
+{
+ if (g_wifidev_registered) {
+ tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ aes_fini();
+ sha1_mod_fini();
+#endif
+ platform_driver_unregister(&wifi_driver);
+ platform_device_unregister(&ssv_wifi_device);
+ g_wifidev_registered = 0;
+ }
+#ifdef CONFIG_HAS_WAKELOCK
+ wake_lock_destroy(&icomm_wake_lock);
+#endif
+ return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+ return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg
new file mode 100755
index 000000000..6f28d7776
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg
@@ -0,0 +1,89 @@
+############################################################
+# A33
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 1
+mac_address_path = /mnt/private/ULI/factory/mac.txt
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+# High PA
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 2
+#register = CE010018:02457D79
+
+# Normal PA
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33.cfg b/drivers/net/wireless/ssv6x5x/platforms/a33.cfg
new file mode 100755
index 000000000..608633b6d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33.cfg
@@ -0,0 +1,17 @@
+############################################################
+# A33
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/../lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/../lichee/linux-3.4
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c
new file mode 100644
index 000000000..76f3694ca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+int initWlan(void)
+{
+ int ret=0;
+ printk(KERN_INFO "wlan.c initWlan\n");
+ ret = tu_ssvdevice_init();
+ return ret;
+}
+void exitWlan(void)
+{
+ tu_ssvdevice_exit();
+ return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+ return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+#ifdef CONFIG_SSV6X5X
+late_initcall(tu_generic_wifi_init_module);
+#else
+module_init(tu_generic_wifi_init_module);
+#endif
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg
new file mode 100755
index 000000000..dd3cf373b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg
@@ -0,0 +1,94 @@
+############################################################
+# Anyka 3916
+# WIFI-CONFIGURATION
+##################################################
+
+hw_mac = 00:a5:b5:39:16:00
+hw_mac_2 = 00:a5:b5:39:16:01
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /usr/modules/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 2
+#mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 40
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+hw_cap_5ghz = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg b/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg
new file mode 100755
index 000000000..fdac6011a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg
@@ -0,0 +1,23 @@
+############################################################
+# Anyka 3916
+############################################################
+
+#ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=0
+
+#ccflags-y += -DCONFIG_SMARTLINK
+############################################################
+# SSV Airkiss
+############################################################
+#cflags-y += -DCONFIG_SSV_SMARTLINK
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c
new file mode 100644
index 000000000..87a90cf7d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int is_on);
+extern int wifi_setup_dt(void);
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+struct semaphore icomm_chipup_sem;
+static int g_wifidev_registered = 0;
+char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+ int ret=0;
+ if (wifi_setup_dt()) {
+ printk("wifi_dt : fail to setup dt\n");
+ goto fail;
+ }
+ extern_wifi_set_enable(0);
+ mdelay(200);
+ extern_wifi_set_enable(1);
+ mdelay(200);
+ sdio_reinit();
+ mdelay(100);
+ g_wifidev_registered = 1;
+fail:
+ up(&icomm_chipup_sem);
+ return ret;
+}
+void exitWlan(void)
+{
+ if (g_wifidev_registered) {
+ tu_ssvdevice_exit();
+ extern_wifi_set_enable(0);
+ g_wifidev_registered = 0;
+ }
+ return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+ int ret;
+ printk("%s\n", __func__);
+ sema_init(&icomm_chipup_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ sha1_mod_init();
+ aes_init();
+#endif
+ ret = initWlan();
+ if (down_timeout(&icomm_chipup_sem,
+ msecs_to_jiffies(1000)) != 0) {
+ ret = -EINVAL;
+ printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+ goto out;
+ }
+ ret = tu_ssvdevice_init();
+out:
+ return ret;
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+ printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ aes_fini();
+ sha1_mod_fini();
+#endif
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg
new file mode 100755
index 000000000..c77fd9ef1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# S805
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg
new file mode 100755
index 000000000..1358a7b31
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg
@@ -0,0 +1,21 @@
+############################################################
+# amlogic m201 s805
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c
new file mode 100644
index 000000000..3078c437c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int is_on);
+extern int wifi_setup_dt(void);
+#define GPIO_REG_WRITEL(val,reg) \
+ do { \
+ __raw_writel(val, CTL_PIN_BASE + (reg)); \
+ } while (0)
+struct semaphore icomm_chipup_sem;
+static int g_wifidev_registered = 0;
+char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+ int ret = 0;
+ extern_wifi_set_enable(0);
+ mdelay(100);
+ extern_wifi_set_enable(1);
+ mdelay(100);
+ sdio_reinit();
+ mdelay(100);
+ g_wifidev_registered = 1;
+ up(&icomm_chipup_sem);
+ return ret;
+}
+void exitWlan(void)
+{
+ if (g_wifidev_registered) {
+ tu_ssvdevice_exit();
+ extern_wifi_set_enable(0);
+ g_wifidev_registered = 0;
+ }
+ return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+ int ret;
+ printk("%s\n", __func__);
+ sema_init(&icomm_chipup_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ sha1_mod_init();
+ aes_init();
+#endif
+ ret = initWlan();
+ if (down_timeout(&icomm_chipup_sem, msecs_to_jiffies(1000)) != 0) {
+ ret = -EINVAL;
+ printk(KERN_ALERT "%s: platform_driver_register timeout\n",
+ __FUNCTION__);
+ goto out;
+ }
+ ret = tu_ssvdevice_init();
+out:
+ return ret;
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+ printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ aes_fini();
+ sha1_mod_fini();
+#endif
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg
new file mode 100755
index 000000000..a624b6c79
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg
@@ -0,0 +1,89 @@
+############################################################
+# S905
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/wifi/ssv/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg
new file mode 100755
index 000000000..25c738a83
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg
@@ -0,0 +1,23 @@
+############################################################
+# amlogic s905
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DCONFIG_SSV_OPENFILE_LOADFW
+ccflags-y += -DPLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm64
+#KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg
new file mode 100755
index 000000000..e2660d847
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg
@@ -0,0 +1,96 @@
+############################################################
+# T920
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/wifi/ssv6x5x/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+#xtal_clock = 25
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_5ghz = off
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
+
+##################################################
+# TXRX SKBQ Threshold Settings:
+##################################################
+rx_threshold = 128
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg
new file mode 100755
index 000000000..8af3f674b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg
@@ -0,0 +1,23 @@
+############################################################
+# amlogic t920
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DCONFIG_SSV_OPENFILE_LOADFW
+ccflags-y += -DPLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm64
+#KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c
new file mode 100644
index 000000000..be7a386c4
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0)
+#include
+#else
+struct wifi_platform_data {
+ int (*set_power)(int val);
+ int (*set_reset)(int val);
+ int (*set_carddetect)(int val);
+ void *(*mem_prealloc)(int section, unsigned long size);
+ int (*get_mac_addr)(unsigned char *buf);
+ void *(*get_country_code)(char *ccode);
+};
+#endif
+#include
+extern int acts_wifi_init(int type);
+extern void acts_wifi_cleanup(void);
+int platform_wifi_power_on(void)
+{
+ int ret = 0;
+ int wifi_type = 0;
+ wifi_type = WLAN_SSV6051;
+ ret = acts_wifi_init(wifi_type);
+ if (unlikely(ret < 0)) {
+ pr_err("SSV6051: Failed to register the power control driver.\n");
+ goto exit;
+ }
+exit:
+ return ret;
+}
+void platform_wifi_power_off(void)
+{
+ acts_wifi_cleanup();
+}
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc = 0;
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+static int ssv_wifi_power(int on)
+{
+ printk("ssv pwr on=%d\n", on);
+ if (on) {
+ } else {
+ }
+ return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+ return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+ val = val;
+ return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+ .set_power = ssv_wifi_power,
+ .set_reset = ssv_wifi_reset,
+ .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = { {
+ .start = WIFI_HOST_WAKE,
+ .flags = IORESOURCE_IRQ,
+ .name = IRQ_RES_NAME,
+ },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+ printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+ .name = "ssv_wlan",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(resources),
+ .resource = resources,
+ .dev = {
+ .platform_data = &ssv_wifi_control,
+ .release = ssv_wifi_device_release,
+ },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_power) {
+ wifi_control_data->set_power(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_reset) {
+ wifi_control_data->set_reset(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+ if (wifi_control_data && wifi_control_data->set_carddetect) {
+ wifi_control_data->set_carddetect(on);
+ }
+ return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+ printk("sdhci_wakeup_irq_handler\n");
+ disable_irq_nosync(irq);
+ return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+ int rc = 0, ret = 0;
+ if (bEnable) {
+ wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ IRQ_RES_NAME);
+ rc = (int)wifi_irqres->start;
+ g_wifi_irq_rc = rc;
+ ret = request_threaded_irq(
+ rc, NULL, (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 0, 0)
+ IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT | IRQF_FORCE_RESUME,
+#else
+ IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+ "wlan_wakeup_irq", NULL);
+ enable_irq_wake(g_wifi_irq_rc);
+ } else {
+ if (g_wifi_irq_rc) {
+ free_irq(g_wifi_irq_rc, NULL);
+ g_wifi_irq_rc = 0;
+ }
+ }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ printk(KERN_ALERT "wifi_probe\n");
+ wifi_control_data = wifi_ctrl;
+ wifi_set_power(0, 40);
+ wifi_set_power(1, 10);
+ wifi_set_carddetect(1);
+ up(&wifi_control_sem);
+ return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ wifi_control_data = wifi_ctrl;
+ wifi_set_power(0, 0);
+ wifi_set_carddetect(0);
+ setup_wifi_wakeup_BB(pdev, false);
+ return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ setup_wifi_wakeup_BB(pdev, true);
+ return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+ setup_wifi_wakeup_BB(pdev, false);
+ return 0;
+}
+static struct platform_driver wifi_driver = { .probe = wifi_probe,
+ .remove = wifi_remove,
+ .suspend = wifi_suspend,
+ .resume = wifi_resume,
+ .driver = { .name =
+ "ssv_wlan",
+ }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+ int ret = 0;
+ sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ sha1_mod_init();
+ aes_init();
+#endif
+ platform_device_register(&ssv_wifi_device);
+ platform_driver_register(&wifi_driver);
+ (void)platform_wifi_power_on();
+ g_wifidev_registered = 1;
+ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+ ret = -EINVAL;
+ printk(KERN_ALERT "%s: platform_driver_register timeout\n",
+ __FUNCTION__);
+ }
+ ret = tu_ssvdevice_init();
+ return ret;
+}
+void exitWlan(void)
+{
+ if (g_wifidev_registered) {
+ tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ aes_fini();
+ sha1_mod_fini();
+#endif
+ (void)platform_wifi_power_off();
+ platform_driver_unregister(&wifi_driver);
+ platform_device_unregister(&ssv_wifi_device);
+ g_wifidev_registered = 0;
+ }
+ return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+ return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg
new file mode 100755
index 000000000..478f18aa0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# ATM7039
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg
new file mode 100755
index 000000000..fc68872dd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg
@@ -0,0 +1,17 @@
+############################################################
+# ATM7039
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/cli b/drivers/net/wireless/ssv6x5x/platforms/cli
new file mode 100755
index 000000000..bc9b65bb7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/cli
@@ -0,0 +1,6 @@
+
+SSV_DFS_FILE=/sys/kernel/debug/ssv/ssv_cmd
+if [ -f $SSV_DFS_FILE ]; then
+ echo "$*" > $SSV_DFS_FILE
+ cat $SSV_DFS_FILE
+fi
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c
new file mode 100644
index 000000000..f5b15bfa3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include
+#include
+#else
+#include
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include
+#else
+struct wifi_platform_data {
+ int (*set_power)(int val);
+ int (*set_reset)(int val);
+ int (*set_carddetect)(int val);
+ void *(*mem_prealloc)(int section, unsigned long size);
+ int (*get_mac_addr)(unsigned char *buf);
+ void *(*get_country_code)(char *ccode);
+};
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc=0;
+#define SDIO_ID 1
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+extern int wifi_pm_gpio_ctrl(char* name, int level);
+static int ssv_wifi_power(int on)
+{
+ printk("ssv pwr on=%d\n",on);
+ if(on) {
+ wifi_pm_gpio_ctrl("wl_reg_on", 0);
+ mdelay(50);
+ wifi_pm_gpio_ctrl("wl_reg_on", 1);
+ } else {
+ wifi_pm_gpio_ctrl("wl_reg_on", 0);
+ }
+ return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+ return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+ sunxi_mci_rescan_card(SDIO_ID, val);
+ return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+ .set_power = ssv_wifi_power,
+ .set_reset = ssv_wifi_reset,
+ .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+ {
+ .start = WIFI_HOST_WAKE,
+ .flags = IORESOURCE_IRQ,
+ .name = IRQ_RES_NAME,
+ },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+ printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+ .name = "ssv_wlan",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(resources),
+ .resource = resources,
+ .dev = {
+ .platform_data = &ssv_wifi_control,
+ .release = ssv_wifi_device_release,
+ },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_power) {
+ wifi_control_data->set_power(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+ if (wifi_control_data && wifi_control_data->set_reset) {
+ wifi_control_data->set_reset(on);
+ }
+ if (msec)
+ msleep(msec);
+ return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+ if (wifi_control_data && wifi_control_data->set_carddetect) {
+ wifi_control_data->set_carddetect(on);
+ }
+ return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+ printk("sdhci_wakeup_irq_handler\n");
+ disable_irq_nosync(irq);
+ return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+ int rc=0,ret=0;
+ if (bEnable) {
+ wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, IRQ_RES_NAME);
+ rc = (int)wifi_irqres->start;
+ g_wifi_irq_rc = rc;
+ ret = request_threaded_irq(rc,
+ NULL,
+ (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+ IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT |IRQF_FORCE_RESUME,
+#else
+ IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+ "wlan_wakeup_irq", NULL);
+ enable_irq_wake(g_wifi_irq_rc);
+ } else {
+ if(g_wifi_irq_rc) {
+ free_irq(g_wifi_irq_rc,NULL);
+ g_wifi_irq_rc = 0;
+ }
+ }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ printk(KERN_ALERT "wifi_probe\n");
+ wifi_control_data = wifi_ctrl;
+ wifi_set_power(0,40);
+ wifi_set_power(1,50);
+ wifi_set_carddetect(1);
+ up(&wifi_control_sem);
+ return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+ struct wifi_platform_data *wifi_ctrl =
+ (struct wifi_platform_data *)(pdev->dev.platform_data);
+ wifi_control_data = wifi_ctrl;
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_power(0, 0);
+ wifi_set_carddetect(0);
+ return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+static struct platform_driver wifi_driver = {
+ .probe = wifi_probe,
+ .remove = wifi_remove,
+ .suspend = wifi_suspend,
+ .resume = wifi_resume,
+ .driver = {
+ .name = "ssv_wlan",
+ }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+ int ret=0;
+ sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ sha1_mod_init();
+ aes_init();
+#endif
+ platform_device_register(&ssv_wifi_device);
+ platform_driver_register(&wifi_driver);
+ g_wifidev_registered = 1;
+ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+ ret = -EINVAL;
+ printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+ }
+ ret = tu_ssvdevice_init();
+ return ret;
+}
+void exitWlan(void)
+{
+ if (g_wifidev_registered) {
+ tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+ aes_fini();
+ sha1_mod_fini();
+#endif
+ platform_driver_unregister(&wifi_driver);
+ platform_device_unregister(&ssv_wifi_device);
+ g_wifidev_registered = 0;
+ }
+ return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+ return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+ exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg
new file mode 100755
index 000000000..6758bd142
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg
@@ -0,0 +1,83 @@
+##################################################
+# H3
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3.cfg b/drivers/net/wireless/ssv6x5x/platforms/h3.cfg
new file mode 100755
index 000000000..7947b303c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3.cfg
@@ -0,0 +1,17 @@
+############################################################
+# H3
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/../lichee/out/sun8iw7p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/../lichee/linux-3.4
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c
new file mode 100644
index 000000000..f5b15bfa3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include