From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Sun, 2 Apr 2023 10:53:07 +0000 Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks --- drivers/clk/rockchip/clk-rk3228.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 996f8bfee..0f690dd84 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), - COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0, + COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, + RK2928_CLKSEL_CON(12), 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 13, GFLAGS), - DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, - RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), - COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, + COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, + RK2928_CLKSEL_CON(12), 8, 8, DFLAGS, RK2928_CLKGATE_CON(2), 14, GFLAGS), - DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, - RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), /* * Clock-Architecture Diagram 2 -- 2.34.1