From 198cad9a30ea2a5a252ceb97736f3475d7a6b08d Mon Sep 17 00:00:00 2001 From: ashthespy Date: Mon, 3 Feb 2020 17:19:33 +0100 Subject: [PATCH 20/23] arm64: dts: rockchip: Add acodec node for rk3308 Change-Id: I76f4a877711d33620bdef295e9047bdba26d4da4 Signed-off-by: Xing Zheng --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index c711c248ce29..3863f8cc2517 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -510,7 +510,7 @@ rk_timer_rtc: rk-timer-rtc@ff1a0020 { clock-names = "pclk", "timer"; status = "disabled"; }; - + saradc: saradc@ff1e0000 { compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff1e0000 0x0 0x100>; @@ -837,6 +837,22 @@ cru: clock-controller@ff500000 { assigned-clock-rates = <32768>; }; + acodec: acodec@ff560000 { + compatible = "rockchip,rk3308-codec"; + reg = <0x0 0xff560000 0x0 0x10000>; + rockchip,grf = <&grf>; + rockchip,detect-grf = <&detect_grf>; + interrupts = , + ; + clocks = <&cru PCLK_ACODEC>, + <&cru SCLK_I2S2_8CH_TX_OUT>, + <&cru SCLK_I2S2_8CH_RX_OUT>; + clock-names = "acodec", "mclk_tx", "mclk_rx"; + resets = <&cru SRST_ACODEC_P>; + reset-names = "acodec-reset"; + status = "disabled"; +}; + gic: interrupt-controller@ff580000 { compatible = "arm,gic-400"; reg = <0x0 0xff581000 0x0 0x1000>, -- 2.25.1