From edc93fd70ee759fd989664fcb85996cb48a006e6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 14 Aug 2023 07:28:09 +0200 Subject: [PATCH 210/464] clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes Notify TCON0 clock (and in consequence PLL-MIPI by CLK_SET_RATE_PARENT) to reset when PLL-Video0 changes (because of HDMI PHY clk which is a child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can get clock tree to satisfy both pipelines. Signed-off-by: Icenowy Zheng Signed-off-by: Frank Oltmanns --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index ef567775fc95..93beedb0428e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; +/* + * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0 clock will + * conflict with HDMI PHY clock which is on another display pipeline. + * + * Therefore, a notifier is required to restore the rate of TCON0 when the rate + * of PLL-Video0 changed. + */ +static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = { + .common = &pll_video0_clk.common, +}; + static int sun50i_a64_ccu_probe(struct platform_device *pdev) { void __iomem *reg; @@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, &sun50i_a64_cpu_nb); + /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */ + sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk; + ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb); + return 0; } -- 2.34.1