From 2bd59104066b4daf9157c573e2ac747accd1ebd6 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 20 Dec 2016 11:25:12 +0100 Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers Kernel would lower the divider on first CLK change and cause the lock up. --- arch/arm/mach-sunxi/clock_sun6i.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 6bd75a15f6..86f08ab717 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -134,11 +134,10 @@ void clock_set_pll1(unsigned int clk) int k = 1; int m = 1; - if (clk > 1152000000) { - k = 2; - } else if (clk > 768000000) { + if (clk >= 1368000000) { k = 4; - m = 2; + } else if (clk >= 768000000) { + k = 2; } /* Switch to 24MHz clock while changing PLL1 */ -- 2.34.1