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build/patch/kernel/archive/meson-6.4/onecloud-0001-add-dts.patch

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From 7ee5e1ab3026c8011af1e49d7930bdcf782c3c56 Mon Sep 17 00:00:00 2001
From: hzy <hzyitc@outlook.com>
Date: Sat, 1 Apr 2023 13:24:42 +0800
Subject: [PATCH 1/2] ARM: dts: meson8b: Add DTS for Xunlei Onecloud
Signed-off-by: hzy <hzyitc@outlook.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/meson8b-onecloud.dts | 410 +++++++++++++++++++++++++
2 files changed, 411 insertions(+)
create mode 100644 arch/arm/boot/dts/meson8b-onecloud.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 59829fc9..d45f45cc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -406,6 +406,7 @@ dtb-$(CONFIG_MACH_MESON8) += \
meson8b-ec100.dtb \
meson8b-mxq.dtb \
meson8b-odroidc1.dtb \
+ meson8b-onecloud.dtb \
meson8m2-mxiii-plus.dtb
dtb-$(CONFIG_ARCH_MMP) += \
pxa168-aspenite.dtb \
diff --git a/arch/arm/boot/dts/meson8b-onecloud.dts b/arch/arm/boot/dts/meson8b-onecloud.dts
new file mode 100644
index 00000000..1fa5420f
--- /dev/null
+++ b/arch/arm/boot/dts/meson8b-onecloud.dts
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: hzy <hzyitc@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "meson8b.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Xunlei OneCloud";
+ compatible = "xunlei,onecloud", "amlogic,meson8b";
+
+ aliases {
+ serial0 = &uart_AO;
+ mmc0 = &sd_card_slot;
+ mmc1 = &sdhc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ button {
+ // compatible = "gpio-keys-polled";
+ // poll-interval = <100>;
+
+ compatible = "gpio-keys";
+
+ autorepeat;
+
+ reset-button {
+ label = "reset";
+ linux,code = <BTN_0>;
+
+ // gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; // GPIOAO 5
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red {
+ label = "onecloud:red:alive";
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+
+ default-state = "on";
+ linux,default-trigger = "default-on";
+ };
+
+ green {
+ label = "onecloud:green:alive";
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+
+ default-state = "off";
+ linux,default-trigger = "mmc1";
+ };
+
+ blue {
+ label = "onecloud:blue:alive";
+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
+
+ default-state = "off";
+ linux,default-trigger = "usb-host";
+ };
+ };
+
+ p12v: regulator-p12v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "P12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_5v: regulator-vcc-5v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ vin-supply = <&p12v>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&p12v>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ vin-supply = <&p12v>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_ddr: regulator-vcc-ddr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC_DDR";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+
+ vin-supply = <&vcc_3v3>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_core: regulator-vcc-core {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VCC_CORE";
+
+ // +---------------------------------------------------+
+ // | The actual mapping in phyical |
+ // +------+--------+--------+--------+--------+--------+
+ // | | 100% | 60% | 30% | 10% | 0% |
+ // +------+--------+--------+--------+--------+--------+
+ // | V1.0 | 677mV | 857mV | 992mV | 1082mV | 1127mV |
+ // | V1.3 | 1116mV | 1121mV | 1125mV | 1128mV | 1129mV |
+ // +------+--------+--------+--------+--------+--------+
+ //
+ // According to meson8b.dtsi, the CPU should be able to
+ // run at 504MHz with 870mV. But this regulator supplies
+ // not only CPU but also GPU. And according to the users'
+ // tests on V1.0, we need such higher voltages.
+
+ pwms = <&pwm_cd 1 12001 0>; // PWM_D
+ pwm-dutycycle-range = <10 0>;
+ regulator-min-microvolt = <860000>;
+ regulator-max-microvolt = <1140000>;
+
+ pwm-supply = <&p12v>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>, <&xtal>;
+ clock-names = "clkin0", "clkin1";
+};
+
+&cpu0 {
+ cpu-supply = <&vcc_core>;
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc_1v8>;
+};
+
+&mali {
+ // commented to allow cpufreq tweaking
+ // mali-supply = <&vcc_core>;
+};
+
+&gpio {
+ gpio-line-names =
+ /* 0 */ "WIFI_SDIO_D0 PIN18 (GPIOX_0)",
+ /* 1 */ "WIFI_SDIO_D1 PIN19 (GPIOX_1)",
+ /* 2 */ "WIFI_SDIO_D2 PIN14 (GPIOX_2)",
+ /* 3 */ "WIFI_SDIO_D3 PIN15 (GPIOX_3)",
+ /* 4 */ "WIFI_PCM_DIN PIN27 (GPIOX_4)",
+ /* 5 */ "WIFI_PCM_DOUT PIN25 (GPIOX_5)",
+ /* 6 */ "WIFI_PCM_SYNC PIN28 (GPIOX_6)",
+ /* 7 */ "WIFI_PCM_CLK PIN26 (GPIOX_7)",
+ /* 8 */ "WIFI_SDIO_CLK PIN17_Resistor (GPIOX_8)",
+ /* 9 */ "WIFI_SDIO_CMD PIN16 (GPIOX_9)",
+ /* 10 */ "GPIOX_10",
+ /* 11 */ "WIFI PIN12 (GPIOX_11)",
+ /* 12 */ "WIFI_UART_RX PIN43 (GPIOX_16)",
+ /* 13 */ "WIFI_UART_TX PIN42 (GPIOX_17)",
+ /* 14 */ "WIFI_UART_RTS PIN41_Resistor (GPIOX_18)",
+ /* 15 */ "WIFI_UART_CTS PIN44 (GPIOX_19)",
+ /* 16 */ "WIFI PIN34 (GPIOX_20)",
+ /* 17 */ "WIFI_WAKE PIN13 (GPIOX_21)",
+
+ /* 18 */ "Resistor_TopOf_LED (GPIOY_0)",
+ /* 19 */ "GPIOY_1",
+ /* 20 */ "GPIOY_3",
+ /* 21 */ "GPIOY_6",
+ /* 22 */ "GPIOY_7",
+ /* 23 */ "GPIOY_8",
+ /* 24 */ "GPIOY_9",
+ /* 25 */ "GPIOY_10",
+ /* 26 */ "GPIOY_11",
+ /* 27 */ "GPIOY_12",
+ /* 28 */ "Left_BottomOf_CPU (GPIOY_13)",
+ /* 29 */ "Right_BottomOf_CPU (GPIOY_14)",
+
+ /* 30 */ "GPIODV_9 (PWM_C)",
+ /* 31 */ "GPIODV_24",
+ /* 32 */ "GPIODV_25",
+ /* 33 */ "GPIODV_26",
+ /* 34 */ "GPIODV_27",
+ /* 35 */ "VCC_CPU_PWM (GPIODV_28)",
+ /* 36 */ "GPIODV_29",
+
+ /* 37 */ "HDMI_HPD (GPIOH_0)",
+ /* 38 */ "HDMI_SDA (GPIOH_1)",
+ /* 39 */ "HDMI_SCL (GPIOH_2)",
+ /* 40 */ "ETH_PHY_INTR (GPIOH_3)",
+ /* 41 */ "ETH_PHY_nRST (GPIOH_4)",
+ /* 42 */ "ETH_TXD1 (GPIOH_5)",
+ /* 43 */ "ETH_TXD0 (GPIOH_6)",
+ /* 44 */ "ETH_TXD3 (GPIOH_7)",
+ /* 45 */ "ETH_TXD2 (GPIOH_8)",
+ /* 46 */ "ETH_TX_CLK (GPIOH_9)",
+
+ /* 47 */ "SDCARD_D1 (CARD_0)",
+ /* 48 */ "SDCARD_D0 (CARD_1)",
+ /* 49 */ "SDCARD_CLK (CARD_2)",
+ /* 50 */ "SDCARD_CMD (CARD_3)",
+ /* 51 */ "SDCARD_D3 (CARD_4)",
+ /* 52 */ "SDCARD_D2 (CARD_5)",
+ /* 53 */ "SDCARD_CD (CARD_6)",
+
+ /* 54 */ "EMMC_D0 (BOOT_0)",
+ /* 55 */ "EMMC_D1 (BOOT_1)",
+ /* 56 */ "EMMC_D2 (BOOT_2)",
+ /* 57 */ "EMMC_D3 (BOOT_3)",
+ /* 58 */ "EMMC_D4 (BOOT_4)",
+ /* 59 */ "EMMC_D5 (BOOT_5)",
+ /* 60 */ "EMMC_D6 (BOOT_6)",
+ /* 61 */ "EMMC_D7 (BOOT_7)",
+ /* 62 */ "EMMC_CLK (BOOT_8)",
+ /* 63 */ "EMMC_nRST (BOOT_9)",
+ /* 64 */ "EMMC_CMD (BOOT_10)",
+ /* 65 */ "BOOT_11",
+ /* 66 */ "BOOT_12",
+ /* 67 */ "BOOT_13",
+ /* 68 */ "BOOT_14",
+ /* 69 */ "BOOT_15",
+ /* 70 */ "BOOT_16",
+ /* 71 */ "BOOT_17",
+ /* 72 */ "BOOT_18",
+
+ /* 73 */ "ETH_RXD1 (DIF_0_P)",
+ /* 74 */ "ETH_RXD0 (DIF_0_N)",
+ /* 75 */ "ETH_RX_DV (DIF_1_P)",
+ /* 76 */ "ETH_RX_CLK (DIF_1_N)",
+ /* 77 */ "ETH_RXD3 (DIF_2_P)",
+ /* 78 */ "ETH_RXD2 (DIF_2_N)",
+ /* 79 */ "ETH_TX_EN (DIF_3_P)",
+ /* 80 */ "ETH_REF_CLK (DIF_3_N)",
+ /* 81 */ "ETH_MDC (DIF_4_P)",
+ /* 82 */ "ETH_MDIO_EN (DIF_4_N)";
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* 0 */ "UART TX (GPIOAO_0)",
+ /* 1 */ "UART RX (GPIOAO_1)",
+ /* 2 */ "RED_LED (GPIOAO_2)",
+ /* 3 */ "GREEN_LED (GPIOAO_3)",
+ /* 4 */ "BLUE_LED (GPIOAO_4)",
+ /* 5 */ "BUTTON (GPIOAO_5)",
+ /* 6 */ "GPIOAO_6",
+ /* 7 */ "IR_IN (GPIOAO_7)",
+ /* 8 */ "GPIOAO_8",
+ /* 9 */ "GPIOAO_9",
+ /* 10 */ "GPIOAO_10",
+ /* 11 */ "GPIOAO_11",
+ /* 12 */ "GPIOAO_12",
+ /* 13 */ "GPIOAO_13",
+
+ /* 14 */ "GPIO_BSD_EN",
+ /* 15 */ "GPIO_TEST_N";
+};
+
+// eMMC
+&sdhc {
+ status = "okay";
+
+ pinctrl-0 = <&sdxc_c_pins>;
+ pinctrl-names = "default";
+
+ non-removable;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ // vqmmc-supply = <&vcc_3v3>;
+};
+
+&sdio {
+ status = "okay";
+
+ pinctrl-0 = <&sd_b_pins>;
+ pinctrl-names = "default";
+
+ // SD card
+ sd_card_slot: slot@1 {
+ compatible = "mmc-slot";
+ reg = <1>;
+ status = "okay";
+
+ bus-width = <4>;
+ no-sdio;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vcc_3v3>;
+ // vqmmc-supply = <&vcc_3v3>;
+ };
+};
+
+&ethmac {
+ status = "okay";
+
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&eth_phy>;
+ phy-mode = "rgmii-rxid";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Realtek RTL8211F (0x001cc916)
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; // GPIOH 3
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&ir_receiver {
+ status = "okay";
+ pinctrl-0 = <&ir_recv_pins>;
+ pinctrl-names = "default";
+};
--
2.34.1
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