build/patch/kernel/archive/meson64-6.4/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch

45 lines
1.5 KiB
Diff

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Vyacheslav Bocharov <adeep@lexina.in>
Date: Mon, 7 Nov 2022 16:19:08 +0300
Subject: arm64: amlogic: dts: meson: update meson-axg device-tree for new
core, tx, rx phase clock settings.
Use phase 270 for core MMC clock on axg meson boards.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b984950591e2..7a7180c39449 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
#include <dt-bindings/power/meson-axg-power.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -1892,6 +1893,7 @@ sd_emmc_b: mmc@5000 {
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
resets = <&reset RESET_SD_EMMC_B>;
};
@@ -1905,6 +1907,7 @@ sd_emmc_c: mmc@7000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
};
usb2_phy1: phy@9020 {
--
Armbian