224 lines
6.8 KiB
Diff
224 lines
6.8 KiB
Diff
--- a/drivers/gpio/gpio-mvebu.c
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+++ b/drivers/gpio/gpio-mvebu.c
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@@ -93,20 +93,41 @@
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#define MVEBU_MAX_GPIO_PER_BANK 32
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-struct mvebu_pwm {
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+enum mvebu_pwm_ctrl {
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+ MVEBU_PWM_CTRL_SET_A = 0,
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+ MVEBU_PWM_CTRL_SET_B,
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+ MVEBU_PWM_CTRL_MAX
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+};
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+
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+struct mvebu_pwmchip {
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void __iomem *membase;
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unsigned long clk_rate;
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+ spinlock_t lock;
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+ bool in_use;
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+
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+ /* Used to preserve GPIO/PWM registers across suspend/resume */
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+ u32 blink_on_duration;
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+ u32 blink_off_duration;
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+};
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+
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+struct mvebu_pwm_chip_drv {
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+ enum mvebu_pwm_ctrl ctrl;
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struct gpio_desc *gpiod;
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+ bool master;
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+};
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+
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+struct mvebu_pwm {
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struct pwm_chip chip;
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- spinlock_t lock;
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struct mvebu_gpio_chip *mvchip;
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+ struct mvebu_pwmchip controller;
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+ enum mvebu_pwm_ctrl default_counter;
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/* Used to preserve GPIO/PWM registers across suspend/resume */
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u32 blink_select;
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- u32 blink_on_duration;
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- u32 blink_off_duration;
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};
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+static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
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+
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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struct regmap *regs;
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@@ -283,12 +304,12 @@ mvebu_gpio_write_level_mask(struct mvebu
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* Functions returning addresses of individual registers for a given
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* PWM controller.
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*/
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-static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
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+static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm)
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{
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return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
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}
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-static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
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+static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm)
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{
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return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
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}
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@@ -723,17 +744,24 @@ static void mvebu_pwm_get_state(struct p
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struct pwm_state *state) {
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struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
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+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
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+ struct mvebu_pwmchip *controller;
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struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
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unsigned long long val;
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unsigned long flags;
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u32 u;
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- spin_lock_irqsave(&mvpwm->lock, flags);
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+ if (chip_data)
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+ controller = mvebu_pwm_list[chip_data->ctrl];
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+ else
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+ controller = &mvpwm->controller;
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+
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+ spin_lock_irqsave(&controller->lock, flags);
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val = (unsigned long long)
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- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
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+ readl_relaxed(mvebu_pwmreg_blink_on_duration(controller));
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val *= NSEC_PER_SEC;
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- do_div(val, mvpwm->clk_rate);
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+ do_div(val, controller->clk_rate);
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if (val > UINT_MAX)
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state->duty_cycle = UINT_MAX;
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else if (val)
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@@ -742,9 +770,9 @@ static void mvebu_pwm_get_state(struct p
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state->duty_cycle = 1;
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val = (unsigned long long)
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- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
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+ readl_relaxed(mvebu_pwmreg_blink_off_duration(controller));
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val *= NSEC_PER_SEC;
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- do_div(val, mvpwm->clk_rate);
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+ do_div(val, controller->clk_rate);
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if (val < state->duty_cycle) {
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state->period = 1;
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} else {
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@@ -786,7 +814,7 @@ static int mvebu_pwm_apply(struct pwm_ch
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else
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on = 1;
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- val = (unsigned long long) mvpwm->clk_rate *
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+ val = (unsigned long long) controller->clk_rate *
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(state->period - state->duty_cycle);
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do_div(val, NSEC_PER_SEC);
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if (val > UINT_MAX)
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@@ -796,16 +824,16 @@ static int mvebu_pwm_apply(struct pwm_ch
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else
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off = 1;
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- spin_lock_irqsave(&mvpwm->lock, flags);
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+ spin_lock_irqsave(&controller->lock, flags);
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- writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
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- writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
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+ writel_relaxed(on, mvebu_pwmreg_blink_on_duration(controller));
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+ writel_relaxed(off, mvebu_pwmreg_blink_off_duration(controller));
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if (state->enabled)
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mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
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else
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mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
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- spin_unlock_irqrestore(&mvpwm->lock, flags);
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+ spin_unlock_irqrestore(&controller->lock, flags);
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return 0;
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}
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@@ -824,10 +852,10 @@ static void __maybe_unused mvebu_pwm_sus
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regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
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&mvpwm->blink_select);
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- mvpwm->blink_on_duration =
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- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
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- mvpwm->blink_off_duration =
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- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
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+ mvpwm->controller.blink_on_duration =
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+ readl_relaxed(mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
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+ mvpwm->controller.blink_off_duration =
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+ readl_relaxed(mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
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}
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static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
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@@ -836,10 +864,10 @@ static void __maybe_unused mvebu_pwm_res
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regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
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mvpwm->blink_select);
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- writel_relaxed(mvpwm->blink_on_duration,
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- mvebu_pwmreg_blink_on_duration(mvpwm));
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- writel_relaxed(mvpwm->blink_off_duration,
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- mvebu_pwmreg_blink_off_duration(mvpwm));
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+ writel_relaxed(mvpwm->controller.blink_on_duration,
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+ mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
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+ writel_relaxed(mvpwm->controller.blink_off_duration,
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+ mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
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}
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static int mvebu_pwm_probe(struct platform_device *pdev,
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@@ -849,6 +877,7 @@ static int mvebu_pwm_probe(struct platfo
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struct device *dev = &pdev->dev;
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struct mvebu_pwm *mvpwm;
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u32 set;
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+ enum mvebu_pwm_ctrl ctrl_set;
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if (!of_device_is_compatible(mvchip->chip.of_node,
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"marvell,armada-370-gpio"))
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@@ -870,12 +899,15 @@ static int mvebu_pwm_probe(struct platfo
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* Use set A for lines of GPIO chip with id 0, B for GPIO chip
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* with id 1. Don't allow further GPIO chips to be used for PWM.
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*/
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- if (id == 0)
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+ if (id == 0) {
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set = 0;
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- else if (id == 1)
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+ ctrl_set = MVEBU_PWM_CTRL_SET_A;
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+ } else if (id == 1) {
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set = U32_MAX;
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- else
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+ ctrl_set = MVEBU_PWM_CTRL_SET_B;
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+ } else {
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return -EINVAL;
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+ }
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regmap_write(mvchip->regs,
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GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
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@@ -885,15 +917,13 @@ static int mvebu_pwm_probe(struct platfo
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mvchip->mvpwm = mvpwm;
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mvpwm->mvchip = mvchip;
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- mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
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- if (IS_ERR(mvpwm->membase))
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- return PTR_ERR(mvpwm->membase);
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-
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- mvpwm->clk_rate = clk_get_rate(mvchip->clk);
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- if (!mvpwm->clk_rate) {
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- dev_err(dev, "failed to get clock rate\n");
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+ mvpwm->controller.membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
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+ if (IS_ERR(mvpwm->controller.membase))
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+ return PTR_ERR(mvpwm->controller.membase);
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+
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+ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk);
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+ if (!mvpwm->controller.clk_rate)
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return -EINVAL;
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- }
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mvpwm->chip.dev = dev;
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mvpwm->chip.ops = &mvebu_pwm_ops;
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@@ -906,7 +936,9 @@ static int mvebu_pwm_probe(struct platfo
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*/
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mvpwm->chip.base = -1;
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- spin_lock_init(&mvpwm->lock);
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+ spin_lock_init(&mvpwm->controller.lock);
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+ mvpwm->default_counter = ctrl_set;
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+ mvebu_pwm_list[ctrl_set] = &mvpwm->controller;
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return pwmchip_add(&mvpwm->chip);
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}
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