746 lines
20 KiB
Diff
746 lines
20 KiB
Diff
From 415ed43c9b64ca38bc433bd5dc0359292dd80380 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Tue, 6 Jul 2021 14:25:41 +0000
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Subject: [PATCH 3/5] rk3228/rk3328: extend rockchip dfi driver
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---
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arch/arm/boot/dts/rk322x.dtsi | 7 +
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drivers/devfreq/event/rockchip-dfi.c | 598 ++++++++++++++++++++++++---
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2 files changed, 557 insertions(+), 48 deletions(-)
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diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
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index ad98fcf37..7e06acc31 100644
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--- a/arch/arm/boot/dts/rk322x.dtsi
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+++ b/arch/arm/boot/dts/rk322x.dtsi
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@@ -97,6 +97,13 @@ opp-1200000000 {
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};
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};
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+ dfi: dfi@11210000 {
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+ reg = <0x11210000 0x400>;
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+ compatible = "rockchip,rk3228-dfi";
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+ rockchip,grf = <&grf>;
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+ status = "okay";
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+ };
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+
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
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index 9a88faaf8..01fb84b99 100644
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -18,25 +18,68 @@
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#include <linux/list.h>
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#include <linux/of.h>
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-#include <soc/rockchip/rk3399_grf.h>
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-
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-#define RK3399_DMC_NUM_CH 2
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-
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+#define PX30_PMUGRF_OS_REG2 0x208
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+
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+#define RK3128_GRF_SOC_CON0 0x140
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+#define RK3128_GRF_OS_REG1 0x1cc
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+#define RK3128_GRF_DFI_WRNUM 0x220
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+#define RK3128_GRF_DFI_RDNUM 0x224
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+#define RK3128_GRF_DFI_TIMERVAL 0x22c
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+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
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+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
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+
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+#define RK3228_GRF_OS_REG2 0x5d0
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+
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+#define RK3288_PMU_SYS_REG2 0x9c
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+#define RK3288_GRF_SOC_CON4 0x254
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+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
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+#define RK3288_DFI_EN (0x30003 << 14)
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+#define RK3288_DFI_DIS (0x30000 << 14)
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+#define RK3288_LPDDR_SEL (0x10001 << 13)
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+#define RK3288_DDR3_SEL (0x10000 << 13)
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+
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+#define RK3328_GRF_OS_REG2 0x5d0
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+
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+#define RK3368_GRF_DDRC0_CON0 0x600
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+#define RK3368_GRF_SOC_STATUS5 0x494
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+#define RK3368_GRF_SOC_STATUS6 0x498
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+#define RK3368_GRF_SOC_STATUS8 0x4a0
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+#define RK3368_GRF_SOC_STATUS9 0x4a4
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+#define RK3368_GRF_SOC_STATUS10 0x4a8
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+#define RK3368_DFI_EN (0x30003 << 5)
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+#define RK3368_DFI_DIS (0x30000 << 5)
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+
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+#define MAX_DMC_NUM_CH 2
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+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
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+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
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/* DDRMON_CTRL */
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-#define DDRMON_CTRL 0x04
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-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
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-#define LPDDR4_EN (0x10001 << 4)
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-#define HARDWARE_EN (0x10001 << 3)
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-#define LPDDR3_EN (0x10001 << 2)
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-#define SOFTWARE_EN (0x10001 << 1)
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-#define SOFTWARE_DIS (0x10000 << 1)
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-#define TIME_CNT_EN (0x10001 << 0)
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+#define DDRMON_CTRL 0x04
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+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
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+#define DDR4_EN (0x10001 << 5)
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+#define LPDDR4_EN (0x10001 << 4)
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+#define HARDWARE_EN (0x10001 << 3)
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+#define LPDDR2_3_EN (0x10001 << 2)
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+#define SOFTWARE_EN (0x10001 << 1)
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+#define SOFTWARE_DIS (0x10000 << 1)
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+#define TIME_CNT_EN (0x10001 << 0)
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#define DDRMON_CH0_COUNT_NUM 0x28
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#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
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#define DDRMON_CH1_COUNT_NUM 0x3c
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#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
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+/* pmu grf */
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+#define PMUGRF_OS_REG2 0x308
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+
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+enum {
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+ DDR4 = 0,
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+ DDR3 = 3,
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+ LPDDR2 = 5,
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+ LPDDR3 = 6,
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+ LPDDR4 = 7,
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+ UNUSED = 0xFF
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+};
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+
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struct dmc_usage {
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u32 access;
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u32 total;
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@@ -50,33 +93,261 @@ struct dmc_usage {
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struct rockchip_dfi {
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struct devfreq_event_dev *edev;
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struct devfreq_event_desc *desc;
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- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
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+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
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struct device *dev;
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void __iomem *regs;
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struct regmap *regmap_pmu;
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+ struct regmap *regmap_grf;
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+ struct regmap *regmap_pmugrf;
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struct clk *clk;
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+ u32 dram_type;
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+ /*
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+ * available mask, 1: available, 0: not available
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+ * each bit represent a channel
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+ */
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+ u32 ch_msk;
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+};
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+
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+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf,
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+ RK3128_GRF_SOC_CON0,
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+ RK3128_DDR_MONITOR_EN);
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+}
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+
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+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf,
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+ RK3128_GRF_SOC_CON0,
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+ RK3128_DDR_MONITOR_DISB);
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+}
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+
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+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
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+{
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+ rk3128_dfi_stop_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
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+{
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+ rk3128_dfi_start_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
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+{
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+ return 0;
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+}
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+
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+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
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+ struct devfreq_event_data *edata)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+ unsigned long flags;
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+ u32 dfi_wr, dfi_rd, dfi_timer;
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+
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+ local_irq_save(flags);
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+
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+ rk3128_dfi_stop_hardware_counter(edev);
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+
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+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
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+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
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+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
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+
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+ edata->load_count = (dfi_wr + dfi_rd) * 4;
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+ edata->total_count = dfi_timer;
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+
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+ rk3128_dfi_start_hardware_counter(edev);
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+
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+ local_irq_restore(flags);
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+
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+ return 0;
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+}
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+
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+static const struct devfreq_event_ops rk3128_dfi_ops = {
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+ .disable = rk3128_dfi_disable,
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+ .enable = rk3128_dfi_enable,
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+ .get_event = rk3128_dfi_get_event,
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+ .set_event = rk3128_dfi_set_event,
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+};
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+
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+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
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+}
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+
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+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
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+}
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+
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+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
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+{
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+ rk3288_dfi_stop_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
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+{
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+ rk3288_dfi_start_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
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+{
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+ return 0;
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+}
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+
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+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+ u32 tmp, max = 0;
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+ u32 i, busier_ch = 0;
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+ u32 rd_count, wr_count, total_count;
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+
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+ rk3288_dfi_stop_hardware_counter(edev);
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+
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+ /* Find out which channel is busier */
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+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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+ if (!(info->ch_msk & BIT(i)))
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+ continue;
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+ regmap_read(info->regmap_grf,
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+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
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+ regmap_read(info->regmap_grf,
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+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
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+ regmap_read(info->regmap_grf,
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+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
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+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
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+ info->ch_usage[i].total = total_count;
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+ tmp = info->ch_usage[i].access;
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+ if (tmp > max) {
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+ busier_ch = i;
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+ max = tmp;
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+ }
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+ }
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+ rk3288_dfi_start_hardware_counter(edev);
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+
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+ return busier_ch;
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+}
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+
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+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
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+ struct devfreq_event_data *edata)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+ int busier_ch;
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+ busier_ch = rk3288_dfi_get_busier_ch(edev);
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+ local_irq_restore(flags);
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+
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+ edata->load_count = info->ch_usage[busier_ch].access;
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+ edata->total_count = info->ch_usage[busier_ch].total;
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+
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+ return 0;
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+}
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+
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+static const struct devfreq_event_ops rk3288_dfi_ops = {
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+ .disable = rk3288_dfi_disable,
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+ .enable = rk3288_dfi_enable,
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+ .get_event = rk3288_dfi_get_event,
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+ .set_event = rk3288_dfi_set_event,
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+};
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+
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+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
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+}
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+
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+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+
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+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
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+}
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+
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+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
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+{
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+ rk3368_dfi_stop_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
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+{
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+ rk3368_dfi_start_hardware_counter(edev);
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+
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+ return 0;
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+}
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+
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+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
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+{
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+ return 0;
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+}
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+
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+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
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+ struct devfreq_event_data *edata)
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+{
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+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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+ unsigned long flags;
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+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
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+
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+ local_irq_save(flags);
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+
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+ rk3368_dfi_stop_hardware_counter(edev);
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+
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+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
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+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
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+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
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+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
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+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
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+
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+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
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+ edata->total_count = dfi_timer;
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+
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+ rk3368_dfi_start_hardware_counter(edev);
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+
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+ local_irq_restore(flags);
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+
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+ return 0;
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+}
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+
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+static const struct devfreq_event_ops rk3368_dfi_ops = {
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+ .disable = rk3368_dfi_disable,
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+ .enable = rk3368_dfi_enable,
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+ .get_event = rk3368_dfi_get_event,
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+ .set_event = rk3368_dfi_set_event,
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};
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static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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void __iomem *dfi_regs = info->regs;
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- u32 val;
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- u32 ddr_type;
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-
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- /* get ddr type */
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- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
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- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
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- RK3399_PMUGRF_DDRTYPE_MASK;
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/* clear DDRMON_CTRL setting */
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writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
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/* set ddr type to dfi */
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- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
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- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
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- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
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+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
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+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
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+ else if (info->dram_type == LPDDR4)
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writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
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+ else if (info->dram_type == DDR4)
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+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
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/* enable count, use software mode */
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writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
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@@ -100,12 +371,22 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
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rockchip_dfi_stop_hardware_counter(edev);
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/* Find out which channel is busier */
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- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
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- info->ch_usage[i].access = readl_relaxed(dfi_regs +
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- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
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+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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+ if (!(info->ch_msk & BIT(i)))
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+ continue;
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+
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info->ch_usage[i].total = readl_relaxed(dfi_regs +
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DDRMON_CH0_COUNT_NUM + i * 20);
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- tmp = info->ch_usage[i].access;
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+
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+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
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+ tmp = readl_relaxed(dfi_regs +
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+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
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+ if (info->dram_type == LPDDR4)
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+ tmp *= 8;
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+ else
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+ tmp *= 4;
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+ info->ch_usage[i].access = tmp;
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|
+
|
|
if (tmp > max) {
|
|
busier_ch = i;
|
|
max = tmp;
|
|
@@ -118,10 +399,14 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
|
|
|
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
|
{
|
|
+ struct device *dev = &edev->dev;
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
|
|
rockchip_dfi_stop_hardware_counter(edev);
|
|
- clk_disable_unprepare(info->clk);
|
|
+ if (info->clk)
|
|
+ clk_disable_unprepare(info->clk);
|
|
+
|
|
+ dev_notice(dev,"Rockchip DFI interface disabled\n");
|
|
|
|
return 0;
|
|
}
|
|
@@ -129,20 +414,28 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
|
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
|
|
{
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
+ struct device *dev = &edev->dev;
|
|
int ret;
|
|
|
|
- ret = clk_prepare_enable(info->clk);
|
|
- if (ret) {
|
|
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
|
- return ret;
|
|
+ if (info->clk) {
|
|
+ ret = clk_prepare_enable(info->clk);
|
|
+ if (ret) {
|
|
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
|
+ ret);
|
|
+ return ret;
|
|
+ }
|
|
}
|
|
|
|
rockchip_dfi_start_hardware_counter(edev);
|
|
+
|
|
+ dev_notice(dev,"Rockchip DFI interface enabled\n");
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
|
|
{
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -151,8 +444,11 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
|
|
{
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
int busier_ch;
|
|
+ unsigned long flags;
|
|
|
|
+ local_irq_save(flags);
|
|
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
|
+ local_irq_restore(flags);
|
|
|
|
edata->load_count = info->ch_usage[busier_ch].access;
|
|
edata->total_count = info->ch_usage[busier_ch].total;
|
|
@@ -167,22 +463,151 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
|
|
.set_event = rockchip_dfi_set_event,
|
|
};
|
|
|
|
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
|
- { .compatible = "rockchip,rk3399-dfi" },
|
|
- { },
|
|
-};
|
|
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
|
+static __init int px30_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
|
+ struct resource *res;
|
|
+ u32 val;
|
|
|
|
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
+ if (IS_ERR(data->regs))
|
|
+ return PTR_ERR(data->regs);
|
|
+
|
|
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
|
+ if (node) {
|
|
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_pmugrf))
|
|
+ return PTR_ERR(data->regmap_pmugrf);
|
|
+ }
|
|
+
|
|
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
+ data->ch_msk = 1;
|
|
+ data->clk = NULL;
|
|
+
|
|
+ desc->ops = &rockchip_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
|
+
|
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
+ if (node) {
|
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_grf))
|
|
+ return PTR_ERR(data->regmap_grf);
|
|
+ }
|
|
+
|
|
+ desc->ops = &rk3128_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rk3228_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
{
|
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
|
+ struct resource *res;
|
|
struct device *dev = &pdev->dev;
|
|
- struct rockchip_dfi *data;
|
|
- struct devfreq_event_desc *desc;
|
|
+ u32 val;
|
|
+
|
|
+ dev_notice(dev,"rk3228_dfi_init enter\n");
|
|
+
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
+ if (IS_ERR(data->regs))
|
|
+ return PTR_ERR(data->regs);
|
|
+
|
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
+ if (node) {
|
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_grf))
|
|
+ return PTR_ERR(data->regmap_grf);
|
|
+ }
|
|
+
|
|
+ regmap_read(data->regmap_grf, RK3228_GRF_OS_REG2, &val);
|
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
+ data->ch_msk = 1;
|
|
+ data->clk = NULL;
|
|
+
|
|
+ desc->ops = &rockchip_dfi_ops;
|
|
+
|
|
+ dev_notice(dev,"rk3228-dfi initialized, dram type: 0x%x, channels: %d\n", data->dram_type, data->ch_msk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
+ u32 val;
|
|
|
|
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
|
- if (!data)
|
|
- return -ENOMEM;
|
|
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
|
+ if (node) {
|
|
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_pmu))
|
|
+ return PTR_ERR(data->regmap_pmu);
|
|
+ }
|
|
+
|
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
+ if (node) {
|
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_grf))
|
|
+ return PTR_ERR(data->regmap_grf);
|
|
+ }
|
|
+
|
|
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
+ data->ch_msk = READ_CH_INFO(val);
|
|
+
|
|
+ if (data->dram_type == DDR3)
|
|
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
|
+ RK3288_DDR3_SEL);
|
|
+ else
|
|
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
|
+ RK3288_LPDDR_SEL);
|
|
+
|
|
+ desc->ops = &rk3288_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+
|
|
+ if (!dev->parent || !dev->parent->of_node)
|
|
+ return -EINVAL;
|
|
+
|
|
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
|
+ if (IS_ERR(data->regmap_grf))
|
|
+ return PTR_ERR(data->regmap_grf);
|
|
+
|
|
+ desc->ops = &rk3368_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
|
+ u32 val;
|
|
|
|
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(data->regs))
|
|
@@ -202,21 +627,98 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
|
|
if (IS_ERR(data->regmap_pmu))
|
|
return PTR_ERR(data->regmap_pmu);
|
|
}
|
|
- data->dev = dev;
|
|
+
|
|
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
+ data->ch_msk = READ_CH_INFO(val);
|
|
+
|
|
+ desc->ops = &rockchip_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
|
+ struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc)
|
|
+{
|
|
+ struct device_node *np = pdev->dev.of_node, *node;
|
|
+ struct resource *res;
|
|
+ u32 val;
|
|
+
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
+ if (IS_ERR(data->regs))
|
|
+ return PTR_ERR(data->regs);
|
|
+
|
|
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
+ if (node) {
|
|
+ data->regmap_grf = syscon_node_to_regmap(node);
|
|
+ if (IS_ERR(data->regmap_grf))
|
|
+ return PTR_ERR(data->regmap_grf);
|
|
+ }
|
|
+
|
|
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
|
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
+ data->ch_msk = 1;
|
|
+ data->clk = NULL;
|
|
+
|
|
+ desc->ops = &rockchip_dfi_ops;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
|
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
|
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
|
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
|
+ { .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
|
|
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
|
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
|
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
|
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
|
+ { },
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
|
+
|
|
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct rockchip_dfi *data;
|
|
+ struct devfreq_event_desc *desc;
|
|
+ struct device_node *np = pdev->dev.of_node;
|
|
+ const struct of_device_id *match;
|
|
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
|
+ struct devfreq_event_desc *desc);
|
|
+
|
|
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
|
+ if (!data)
|
|
+ return -ENOMEM;
|
|
|
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
|
if (!desc)
|
|
return -ENOMEM;
|
|
|
|
- desc->ops = &rockchip_dfi_ops;
|
|
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
|
+ if (match) {
|
|
+ init = match->data;
|
|
+ if (init) {
|
|
+ if (init(pdev, data, desc))
|
|
+ return -EINVAL;
|
|
+ } else {
|
|
+ return 0;
|
|
+ }
|
|
+ } else {
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
desc->driver_data = data;
|
|
desc->name = np->name;
|
|
data->desc = desc;
|
|
+ data->dev = dev;
|
|
|
|
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
|
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
|
if (IS_ERR(data->edev)) {
|
|
- dev_err(&pdev->dev,
|
|
- "failed to add devfreq-event device\n");
|
|
+ dev_err(dev, "failed to add devfreq-event device\n");
|
|
return PTR_ERR(data->edev);
|
|
}
|
|
|
|
--
|
|
2.25.1
|
|
|
|
|