1514 lines
35 KiB
Diff
1514 lines
35 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Piotr Szczepanik <piter75@gmail.com>
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Date: Sun, 24 Nov 2019 22:07:46 +0100
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Subject: [ARCHEOLOGY] Multiple bootloader creation options for rk3399 (#1614)
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> X-Git-Archeology: > recovered message: > * Updated rockchip64-dev to u-boot v2019.10 and BL31 v1.30 (rk3399 boards)
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> X-Git-Archeology: > recovered message: > * Updated rk3399 to u-boot v2019.10 and BL31 v1.30
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> X-Git-Archeology: > recovered message: > * Revert changes to renegade u-boot patches
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> X-Git-Archeology: > recovered message: > * Moved renegade u-boot patches into board dir
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> X-Git-Archeology: > recovered message: > * Added debug info for RockPro64 and switched sdmmc to fifo-mode
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> X-Git-Archeology: > recovered message: > * Disabled regulators in SPL for RockPro64
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> X-Git-Archeology: > recovered message: > * Re-enabled sd vcc regulator in SPL for RockPro64
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> X-Git-Archeology: > recovered message: > * Some device tree and config changes for OrangePi RK3399
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> X-Git-Archeology: > recovered message: > * Fixed Rock Pi 4A's $BOOTCONFIG
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> X-Git-Archeology: > recovered message: > * Let some boards use mainline atf instead of the one in rkbin
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> X-Git-Archeology: > recovered message: > For example, roc-rk3399-pc can just boot the kernel using the
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> X-Git-Archeology: > recovered message: > mainline atf.
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> X-Git-Archeology: > recovered message: > * Add roc-rk3399-pc
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> X-Git-Archeology: > recovered message: > * Fixed reset in mainline ATF
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> X-Git-Archeology: > recovered message: > * Attached ATF version to v2.2 tag
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> X-Git-Archeology: > recovered message: > * WIP: sdmmc fifo-mode in SPL only
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> X-Git-Archeology: > recovered message: > * Renamed source config files
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> X-Git-Archeology: > recovered message: > * Reverted changes to rockchip64 sources config
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> X-Git-Archeology: > recovered message: > * Reverted patch moves
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> X-Git-Archeology: > recovered message: > * Add missing trust.ini patch to rk3399 u-boot
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> X-Git-Archeology: > recovered message: > * Reinstated tpl/spl patches in rk3399 family
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> X-Git-Archeology: > recovered message: > * Added $RKBIN_DIR prefix in rk3399 sources
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> X-Git-Archeology: > recovered message: > * Add demonstration of boards bootloader assignment in rk3399
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> X-Git-Archeology: - Revision 1c9ef0872bfdda69e66de11f0e97b6b43218f73c: https://github.com/armbian/build/commit/1c9ef0872bfdda69e66de11f0e97b6b43218f73c
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> X-Git-Archeology: Date: Sun, 24 Nov 2019 22:07:46 +0100
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> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
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> X-Git-Archeology: Subject: Multiple bootloader creation options for rk3399 (#1614)
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision 79d0040b89ef733b2a16a28cf020557b70f0ccfc: https://github.com/armbian/build/commit/79d0040b89ef733b2a16a28cf020557b70f0ccfc
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> X-Git-Archeology: Date: Mon, 09 Dec 2019 22:11:59 +0000
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> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
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> X-Git-Archeology: Subject: Moved roc-rk3399-pc from default to legacy
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision c27379e93fee03453d3275a4f68fea2277d375c9: https://github.com/armbian/build/commit/c27379e93fee03453d3275a4f68fea2277d375c9
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> X-Git-Archeology: Date: Mon, 10 Aug 2020 18:22:48 +0200
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> X-Git-Archeology: From: Aditya Prayoga <aprayoga@users.noreply.github.com>
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> X-Git-Archeology: Subject: Add Helios64 support (#2126)
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision b031de58d76f332cd4ab37c97ac3361383f0aa05: https://github.com/armbian/build/commit/b031de58d76f332cd4ab37c97ac3361383f0aa05
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> X-Git-Archeology: Date: Mon, 05 Oct 2020 00:16:28 +0200
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> X-Git-Archeology: From: Uwe Kleine-Konig <ukleinek@users.noreply.github.com>
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> X-Git-Archeology: Subject: rk3399: Adapt helios64 devicetree name to match upstream linux (#2235)
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision cd886792c0e4cb9761eddb6e9dca355892663769: https://github.com/armbian/build/commit/cd886792c0e4cb9761eddb6e9dca355892663769
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> X-Git-Archeology: Date: Tue, 15 Dec 2020 23:07:54 +0100
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> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
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> X-Git-Archeology: Subject: Fix booting of roc-rk3399-pc/station-p1 with legacy
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
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> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
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> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
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> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
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> X-Git-Archeology:
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> X-Git-Archeology: - Revision 510e348202f8efb838a57a9eec6ccbc910d7e06e: https://github.com/armbian/build/commit/510e348202f8efb838a57a9eec6ccbc910d7e06e
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> X-Git-Archeology: Date: Sun, 18 Apr 2021 22:48:56 +0200
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> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
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> X-Git-Archeology: Subject: 150balbes fix station legacy (#2782)
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> X-Git-Archeology:
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---
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arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1437 ++++++++++
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1 file changed, 1437 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
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new file mode 100644
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index 000000000000..2c2208daf5dd
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
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@@ -0,0 +1,1437 @@
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+/dts-v1/;
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+
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+#include <dt-bindings/pwm/pwm.h>
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+#include <dt-bindings/input/input.h>
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+#include "rk3399.dtsi"
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+#include "rk3399-opp.dtsi"
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+#include "rk3399-vop-clk-set.dtsi"
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+
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+/ {
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+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
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+
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+ /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */
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+
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+ iram: sram@ff8d0000 {
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+ compatible = "mmio-sram";
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+ reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */
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+ };
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+
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+ clkin_gmac: external-gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "clkin_gmac";
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+ #clock-cells = <0>;
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+ };
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+
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+ hdmi_sound: hdmi-sound {
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+ status = "disabled";
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,mclk-fs = <256>;
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+ simple-audio-card,name = "rockchip,hdmi";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s2>;
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+ };
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+ simple-audio-card,codec {
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+ sound-dai = <&hdmi>;
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+ };
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+ };
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+
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+ vccadc_ref: vccadc-ref {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc1v8_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ vcc3v3_sys: vcc3v3-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ vcc5v0_host: vcc5v0-host-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&host_vbus_drv>;
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+ regulator-name = "vcc5v0_host";
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+ regulator-always-on;
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+ };
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+
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+ vcc_hub_en: vcc_hub_en-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hub_rst_en>;
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+ regulator-name = "vcc_hub_en";
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+ regulator-always-on;
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+ };
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+
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+ vcc_wifi: vcc-wifi {
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+ status = "okay";
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_wifi";
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+ enable-active-high;
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+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_wifi_h>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vcc_pcie: vcc-pcie {
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+ status = "okay";
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_pcie";
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+ enable-active-high;
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+ gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_pcie_h>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vcc_chargen: vcc-chargen {
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+ status = "disabled";
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_chargen";
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+ enable-active-high;
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+ gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_chargen_h>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vcc_sd: vcc-sd {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_sd_h>;
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+ regulator-name = "vcc_sd";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ vcc5v0_sys: vcc5v0-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vcc_phy: vcc-phy-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_phy";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ vdd_log: vdd-log {
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+ compatible = "pwm-regulator";
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+ pwms = <&pwm2 0 25000 1>;
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+ regulator-name = "vdd_log";
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+ regulator-min-microvolt = <800000>;
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+ regulator-max-microvolt = <1100000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+
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+ /* for rockchip boot on */
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+ rockchip,pwm_id= <2>;
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+ rockchip,pwm_voltage = <1000000>;
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+ };
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+
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+ vcc_lcd: vcc-lcd-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ enable-active-high;
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+ gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&lcd_en>;
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+ regulator-name = "vcc_lcd";
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rk808 1>;
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+ clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_enable_h>;
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+
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+ /*
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+ * On the module itself this is one of these (depending
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+ * on the actual card populated):
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+ * - SDIO_RESET_L_WL_REG_ON
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+ * - PDN (power down when low)
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+ */
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+ reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
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+ };
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+
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+ wireless_wlan: wireless-wlan {
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+ compatible = "wlan-platdata";
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+ rockchip,grf = <&grf>;
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+ wifi_chip_type = "ap6354";
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+ sdio_vref = <1800>;
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+ WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
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+ status = "disabled";
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+ };
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+
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+ wireless_bluetooth: wireless-bluetooth {
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+ compatible = "bluetooth-platdata";
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+ //wifi-bt-power-toggle;
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+ clocks = <&rk808 1>;
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+ clock-name = "ext_clock";
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+ uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
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+ pinctrl-names = "default", "rts_gpio";
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+ pinctrl-0 = <&uart0_rts>;
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+ pinctrl-1 = <&uart0_gpios>;
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+ //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
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+ BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
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+ BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
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+ BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
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+ status = "disabled";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ power {
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+ label = "firefly:blue:power";
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+ linux,default-trigger = "ir-power-click";
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+ default-state = "on";
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+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
|
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+ pinctrl-names = "default";pinctrl-0 = <&led_power>;
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+ };
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+ user {
|
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+ label = "firefly:yellow:user";
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+ linux,default-trigger = "ir-user-click";
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+ default-state = "off";
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+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
|
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+ pinctrl-names = "default";
|
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+ pinctrl-0 = <&led_user>;
|
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+ };
|
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+ };
|
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+
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+ adc-keys {
|
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+ compatible = "adc-keys";
|
|
+ io-channels = <&saradc 1>;
|
|
+ io-channel-names = "buttons";
|
|
+ poll-interval = <300>;
|
|
+ keyup-threshold-microvolt = <1800000>;
|
|
+
|
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+ esc-key {
|
|
+ linux,code = <KEY_ESC>;
|
|
+ label = "esc";
|
|
+ press-threshold-microvolt = <0>;
|
|
+ };
|
|
+ };
|
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+
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+ gpio-keys {
|
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+ compatible = "gpio-keys";
|
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+ #address-cells = <1>;
|
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+ #size-cells = <0>;
|
|
+ autorepeat;
|
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+
|
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+ pinctrl-names = "default";
|
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+ pinctrl-0 = <&pwrbtn>;
|
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+
|
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+ button@0 {
|
|
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
|
+ linux,code = <KEY_POWER>;
|
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+ label = "GPIO Key Power";
|
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+ linux,input-type = <1>;
|
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+ gpio-key,wakeup = <1>;
|
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+ debounce-interval = <100>;
|
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+ };
|
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+ };
|
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+
|
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+ usb_charge: usb-charge {
|
|
+ compatible = "usb-ext-charge";
|
|
+ status = "disabled";
|
|
+ io-channels = <&saradc 0>;
|
|
+ extcon = <&fusb0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&vcc_chargen_h &bat_int_h &cur_ctl_h &poe_det_h>;
|
|
+ bat-int = <&gpio2 28 IRQ_TYPE_EDGE_RISING>;
|
|
+ charge-en-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
|
|
+ cur-ctl-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
|
|
+ poe-state-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
|
|
+ //cap-led-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ dp_sound: dp-sound {
|
|
+ status = "disabled";
|
|
+ compatible = "rockchip,cdndp-sound";
|
|
+ rockchip,cpu = <&spdif>;
|
|
+ rockchip,codec = <&cdn_dp 1>;
|
|
+ };
|
|
+
|
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+ vcc_mipi: vcc_mipi {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
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+ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&dvp_pwr>;
|
|
+ regulator-name = "vcc_mipi";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
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+ dvdd_1v2: dvdd-1v2 {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&cif_pwr>;
|
|
+ regulator-name = "dvdd_1v2";
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cpu_l0 {
|
|
+ cpu-supply = <&vdd_cpu_l>;
|
|
+};
|
|
+
|
|
+&cpu_l1 {
|
|
+ cpu-supply = <&vdd_cpu_l>;
|
|
+};
|
|
+
|
|
+&cpu_l2 {
|
|
+ cpu-supply = <&vdd_cpu_l>;
|
|
+};
|
|
+
|
|
+&cpu_l3 {
|
|
+ cpu-supply = <&vdd_cpu_l>;
|
|
+};
|
|
+
|
|
+&cpu_b0 {
|
|
+ cpu-supply = <&vdd_cpu_b>;
|
|
+};
|
|
+
|
|
+&cpu_b1 {
|
|
+ cpu-supply = <&vdd_cpu_b>;
|
|
+};
|
|
+
|
|
+&display_subsystem {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&emmc_phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gmac {
|
|
+ phy-supply = <&vcc_phy>;
|
|
+ phy-mode = "rgmii";
|
|
+ clock_in_out = "input";
|
|
+ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
|
|
+ snps,reset-active-low;
|
|
+ snps,reset-delays-us = <0 10000 50000>;
|
|
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
|
+ assigned-clock-parents = <&clkin_gmac>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&rgmii_pins>;
|
|
+ tx_delay = <0x2e>;
|
|
+ rx_delay = <0x13>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpu {
|
|
+ status = "okay";
|
|
+ mali-supply = <&vdd_gpu>;
|
|
+};
|
|
+
|
|
+&hdmi {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ status = "okay";
|
|
+ i2c-scl-rising-time-ns = <168>;
|
|
+ i2c-scl-falling-time-ns = <4>;
|
|
+ clock-frequency = <400000>;
|
|
+
|
|
+ vdd_cpu_b: syr827@40 {
|
|
+ compatible = "silergy,syr827";
|
|
+ reg = <0x40>;
|
|
+ vin-supply = <&vcc5v0_sys>;
|
|
+ regulator-compatible = "fan53555-reg";
|
|
+ regulator-name = "vdd_cpu_b";
|
|
+ regulator-min-microvolt = <712500>;
|
|
+ regulator-max-microvolt = <1500000>;
|
|
+ regulator-ramp-delay = <1000>;
|
|
+ pinctrl-0 = <&vsel1_gpio>;
|
|
+ vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
|
|
+ fcs,suspend-voltage-selector = <1>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-initial-state = <3>;
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_gpu: syr828@41 {
|
|
+ compatible = "silergy,syr828";
|
|
+ reg = <0x41>;
|
|
+ vin-supply = <&vcc5v0_sys>;
|
|
+ pinctrl-0 = <&vsel2_gpio>;
|
|
+ vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
|
+ regulator-compatible = "fan53555-reg";
|
|
+ regulator-name = "vdd_gpu";
|
|
+ regulator-min-microvolt = <712500>;
|
|
+ regulator-max-microvolt = <1500000>;
|
|
+ regulator-ramp-delay = <1000>;
|
|
+ fcs,suspend-voltage-selector = <1>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-initial-state = <3>;
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rk808: pmic@1b {
|
|
+ compatible = "rockchip,rk808";
|
|
+ reg = <0x1b>;
|
|
+ interrupt-parent = <&gpio1>;
|
|
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
|
+ pinctrl-names = "default";
|
|
+ //pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
|
|
+ pinctrl-0 = <&pmic_int_l &pmic_dvs2 &vcc_5v0_h>;
|
|
+ rockchip,system-power-controller;
|
|
+ wakeup-source;
|
|
+ #clock-cells = <1>;
|
|
+ clock-output-names = "xin32k", "rk808-clkout2";
|
|
+
|
|
+ pmic,hold-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
|
|
+
|
|
+ //vin-supply = <&sys_12v>;
|
|
+
|
|
+ vcc1-supply = <&vcc3v3_sys>;
|
|
+ vcc2-supply = <&vcc3v3_sys>;
|
|
+ vcc3-supply = <&vcc3v3_sys>;
|
|
+ vcc4-supply = <&vcc3v3_sys>;
|
|
+ vcc6-supply = <&vcc3v3_sys>;
|
|
+ vcc7-supply = <&vcc3v3_sys>;
|
|
+ vcc8-supply = <&vcc3v3_sys>;
|
|
+ vcc9-supply = <&vcc3v3_sys>;
|
|
+ vcc10-supply = <&vcc3v3_sys>;
|
|
+ vcc11-supply = <&vcc3v3_sys>;
|
|
+ vcc12-supply = <&vcc3v3_sys>;
|
|
+ vddio-supply = <&vcc1v8_pmu>;
|
|
+
|
|
+ regulators {
|
|
+ vdd_center: DCDC_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <750000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-name = "vdd_center";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_cpu_l: DCDC_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <750000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-name = "vdd_cpu_l";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_ddr: DCDC_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-name = "vcc_ddr";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v8: DCDC_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc_1v8";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcca1v8_codec: LDO_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcca1v8_codec";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc1v8_hdmi: LDO_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc1v8_hdmi";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc1v8_pmu: LDO_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc1v8_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_sd: LDO_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "vccio_sd";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcca3v0_codec: LDO_REG5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3000000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "vcca3v0_codec";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v5: LDO_REG6 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1500000>;
|
|
+ regulator-max-microvolt = <1500000>;
|
|
+ regulator-name = "vcc_1v5";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1500000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcca0v9_hdmi: LDO_REG7 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vcca0v9_hdmi";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_3v0: LDO_REG8 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3000000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "vcc_3v0";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc3v3_s3: SWITCH_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-name = "vcc3v3_s3";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc3v3_s0: SWITCH_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-name = "vcc3v3_s0";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ status = "okay";
|
|
+ i2c-scl-rising-time-ns = <300>;
|
|
+ i2c-scl-falling-time-ns = <15>;
|
|
+ clock-frequency = <100000>;
|
|
+
|
|
+ ov13850: ov13850@36 {
|
|
+ compatible = "ovti,ov13850";
|
|
+ status = "disabled";
|
|
+ reg = <0x36>;
|
|
+ clocks = <&cru SCLK_CIF_OUT>;
|
|
+ clock-names = "xvclk";
|
|
+
|
|
+ /* conflict with csi-ctl-gpios */
|
|
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; /*GPIO0_B0 MIP_RST*/
|
|
+ pwdn-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; /*GPIO2_A2 DVP_PDN0*/
|
|
+ pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
|
|
+ //pinctrl-0 = <&cif_clkout>;
|
|
+ pinctrl-0 = <&pwdn_cam0 &mipi_rst>;
|
|
+ pinctrl-1 = <&cam0_default_pins>;
|
|
+ pinctrl-2 = <&cam0_sleep_pins>;
|
|
+ rockchip,camera-module-index = <0>;
|
|
+ rockchip,camera-module-facing = "back";
|
|
+ rockchip,camera-module-name = "CMK-CT0116";
|
|
+ rockchip,camera-module-lens-name = "Largan-50013A1";
|
|
+
|
|
+ avdd-supply = <&vcc_mipi>; /* GPIO1_C6 CIF_PWR AGND*/
|
|
+ dovdd-supply = <&vcc_mipi>; /* GPIO1_C6 CIF_PWR AGND */
|
|
+ dvdd-supply = <&dvdd_1v2>; /* GPIO1_C7 DVP_PWR DVDD_1V2 */
|
|
+
|
|
+ port {
|
|
+ ucam_out0: endpoint {
|
|
+ remote-endpoint = <&mipi_in_ucam0>;
|
|
+ data-lanes = <1 2>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ov13850_1: ov13850@46 {
|
|
+ compatible = "ovti,ov13850";
|
|
+ status = "disabled";
|
|
+ reg = <0x46>;
|
|
+ clocks = <&cru SCLK_CIF_OUT>;
|
|
+ clock-names = "xvclk";
|
|
+
|
|
+ /* conflict with csi-ctl-gpios */
|
|
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; /*GPIO0_B0 MIP_RST*/
|
|
+ pwdn-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; /*GPIO2_A3 DVP_PDN0*/
|
|
+ pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
|
|
+ //pinctrl-0 = <&cif_clkout>;
|
|
+ pinctrl-0 = <&pwdn_cam1>;
|
|
+ pinctrl-1 = <&cam0_default_pins>;
|
|
+ pinctrl-2 = <&cam0_sleep_pins>;
|
|
+ rockchip,camera-module-index = <1>;
|
|
+ rockchip,camera-module-facing = "back";
|
|
+ rockchip,camera-module-name = "CMK-CT0116";
|
|
+ rockchip,camera-module-lens-name = "Largan-50013A1";
|
|
+
|
|
+ avdd-supply = <&vcc_mipi>; /* VCC28_MIPI */
|
|
+ dovdd-supply = <&vcc_mipi>; /* VCC18_MIPI */
|
|
+ dvdd-supply = <&dvdd_1v2>; /* DVDD_1V2 */
|
|
+
|
|
+ port {
|
|
+ ucam_out1: endpoint {
|
|
+ remote-endpoint = <&mipi_in_ucam1>;
|
|
+ data-lanes = <1 2>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ status = "okay";
|
|
+ cw2015@62 {
|
|
+ status = "okay";
|
|
+ compatible = "cw201x";
|
|
+ reg = <0x62>;
|
|
+ bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48
|
|
+ 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24
|
|
+ 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45
|
|
+ 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E
|
|
+ 0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D
|
|
+ 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52
|
|
+ 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB
|
|
+ 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
|
|
+ monitor_sec = <5>;
|
|
+ virtual_power = <0>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c4 {
|
|
+ status = "okay";
|
|
+ i2c-scl-rising-time-ns = <475>;
|
|
+ i2c-scl-falling-time-ns = <26>;
|
|
+
|
|
+ gsl3680: gsl3680@40 {
|
|
+ status = "disabled";
|
|
+ compatible = "gslX680";
|
|
+ reg = <0x40>;
|
|
+ screen_max_x = <1536>;
|
|
+ screen_max_y = <2048>;
|
|
+ revert_xy = <0>;
|
|
+ revert_x = <0>;
|
|
+ revert_y = <0>;
|
|
+ touch-gpio = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
|
|
+ reset-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ fusb1: fusb30x@22 {
|
|
+ compatible = "fairchild,fusb302";
|
|
+ reg = <0x22>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&fusb1_int &typec1_vbus_drv>;
|
|
+ int-n-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
|
+ vbus-5v-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+};
|
|
+
|
|
+&i2c7 {
|
|
+ status = "okay";
|
|
+ i2c-scl-rising-time-ns = <345>;
|
|
+ i2c-scl-falling-time-ns = <11>;
|
|
+ clock-frequency = <400000>;
|
|
+
|
|
+ fusb0: fusb30x@22 {
|
|
+ compatible = "fairchild,fusb302";
|
|
+ reg = <0x22>;
|
|
+ //charge-dev = <&mp8859>;
|
|
+ power-dev = <&mp8859>;
|
|
+ pinctrl-names = "default";
|
|
+ //pinctrl-0 = <&fusb0_int &vcc_chargen_h>;
|
|
+ pinctrl-0 = <&fusb0_int>;
|
|
+ int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
|
+ //charge-en-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ mp8859: mp8859@66 {
|
|
+ compatible = "mps,mp8859";
|
|
+ reg = <0x66>;
|
|
+ status = "okay";
|
|
+ extcon = <&fusb0>;
|
|
+ max-input-voltage = <15000000>;
|
|
+ max-input-current = <3000000>;
|
|
+ //charge-en-gpios =<&gpio0 1 GPIO_ACTIVE_HIGH>;
|
|
+ //pinctrl-names = "default";
|
|
+ //pinctrl-0 = <&vcc_chargen_h>;
|
|
+ //mp,register-power-supply;
|
|
+
|
|
+ regulators {
|
|
+ sys_12v: mp8859_dcdc1 {
|
|
+ regulator-name = "sys_12v";
|
|
+ regulator-min-microvolt = <12300000>;
|
|
+ regulator-max-microvolt = <12300000>;
|
|
+ regulator-ramp-delay = <8000>;
|
|
+ //regulator-always-on;
|
|
+ //regulator-boot-on;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2s1 {
|
|
+ status = "okay";
|
|
+ rockchip,i2s-broken-burst-len;
|
|
+ rockchip,playback-channels = <2>;
|
|
+ rockchip,capture-channels = <2>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ assigned-clocks = <&cru SCLK_I2S1_DIV>, <&cru SCLK_I2S_8CH>;
|
|
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru SCLK_I2S1_8CH>;
|
|
+};
|
|
+
|
|
+&i2s2 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ dmas = <&dmac_bus 4>;
|
|
+ dma-names = "tx";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&io_domains {
|
|
+ status = "okay";
|
|
+ bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */
|
|
+ audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
|
|
+ sdmmc-supply = <&vccio_sd>; /* sdmmc_gpio4b_ms */
|
|
+ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
|
|
+};
|
|
+
|
|
+&pcie_phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie0 {
|
|
+ ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
|
|
+ num-lanes = <4>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pmu_io_domains {
|
|
+ status = "okay";
|
|
+ pmu1830-supply = <&vcc_3v0>;
|
|
+};
|
|
+
|
|
+/* HACK: keep MALI version on linux */
|
|
+&gpu_power_model {
|
|
+ // for DDK r14.
|
|
+ voltage = <900>;
|
|
+ frequency = <500>;
|
|
+ static-power = <300>;
|
|
+ dynamic-power = <396>;
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ cam0 {
|
|
+ cif_pwr: cif-pwr {
|
|
+ rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ dvp_pwr: dvp-pwr {
|
|
+ rockchip,pins = <1 22 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ lcd-panel {
|
|
+ lcd_panel_reset: lcd-panel-reset {
|
|
+ rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ lcd_en: lcd-en {
|
|
+ rockchip,pins = <1 24 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ vsel1_gpio: vsel1-gpio {
|
|
+ rockchip,pins =
|
|
+ <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ vsel2_gpio: vsel2-gpio {
|
|
+ rockchip,pins =
|
|
+ <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ led_power: led-power {
|
|
+ rockchip,pins =
|
|
+ <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ led_user: led-user {
|
|
+ rockchip,pins =
|
|
+ <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int_l: pmic-int-l {
|
|
+ rockchip,pins =
|
|
+ <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ pmic_dvs2: pmic-dvs2 {
|
|
+ rockchip,pins =
|
|
+ <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h: wifi-enable-h {
|
|
+ rockchip,pins =
|
|
+ <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wireless-bluetooth {
|
|
+ uart0_gpios: uart0-gpios {
|
|
+ rockchip,pins =
|
|
+ <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2 {
|
|
+ host_vbus_drv: host-vbus-drv {
|
|
+ rockchip,pins =
|
|
+ <1 0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ hub_rst_en: hub-rst-en {
|
|
+ rockchip,pins =
|
|
+ <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fusb30x {
|
|
+ fusb1_int: fusb1-int {
|
|
+ rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ fusb0_int: fusb0-int {
|
|
+ rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ typec1_vbus_drv: typec1-vbus-drv {
|
|
+ rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc5v0_sys {
|
|
+ vcc_5v0_h: vcc-5v0-h {
|
|
+ rockchip,pins = <2 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_sd {
|
|
+ vcc_sd_h: vcc-sd-h {
|
|
+ rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+ wifi {
|
|
+ vcc_wifi_h: vcc-wifi-h {
|
|
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie {
|
|
+ vcc_pcie_h: vcc-pcie-h {
|
|
+ rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ buttons {
|
|
+ pwrbtn: pwrbtn {
|
|
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ chargen {
|
|
+ vcc_chargen_h: vcc-chargen-h {
|
|
+ rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ bat_int_h: bat-int-h {
|
|
+ rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ cur_ctl_h: cur-ctl-h {
|
|
+ rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none_20ma>;
|
|
+ };
|
|
+ poe_det_h: poe-det-h {
|
|
+ rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cam_pins {
|
|
+ cam0_default_pins: cam0-default-pins {
|
|
+ rockchip,pins =
|
|
+ // <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ cam0_sleep_pins: cam0-sleep-pins {
|
|
+ rockchip,pins =
|
|
+ <4 27 RK_FUNC_3 &pcfg_pull_none>,
|
|
+ <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pwdn_cam0: pwdn-cma0 {
|
|
+ rockchip,pins =
|
|
+ <2 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pwdn_cam1: pwdn-cma1 {
|
|
+ rockchip,pins =
|
|
+ <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ mipi_rst: mipi-rst {
|
|
+ rockchip,pins =
|
|
+ <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwm1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwm2 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "active";
|
|
+ pinctrl-0 = <&pwm2_pin_pull_down>;
|
|
+};
|
|
+
|
|
+&rkvdec {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rockchip_suspend {
|
|
+ rockchip,power-ctrl =
|
|
+ <&gpio1 18 GPIO_ACTIVE_LOW>,
|
|
+ <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
|
+};
|
|
+
|
|
+&dp_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hdmi_sound {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&cdn_dp {
|
|
+ status = "okay";
|
|
+ extcon = <&fusb0 &fusb1>;
|
|
+ phys = <&tcphy0_dp &tcphy1_dp>;
|
|
+};
|
|
+
|
|
+&hdmi_in_vopl {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&dp_in_vopb {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dp_in_vopl {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&saradc {
|
|
+ status = "okay";
|
|
+ vref-supply = <&vccadc_ref>;
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ bus-width = <8>;
|
|
+ mmc-hs400-1_8v;
|
|
+ supports-emmc;
|
|
+ non-removable;
|
|
+ mmc-hs400-enhanced-strobe;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ clock-frequency = <100000000>;
|
|
+ clock-freq-min-max = <100000 100000000>;
|
|
+ supports-sd;
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ disable-wp;
|
|
+ num-slots = <1>;
|
|
+ //sd-uhs-sdr104;
|
|
+ vqmmc-supply = <&vcc_sd>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
|
+ card-detect-delay = <800>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdio0 {
|
|
+ max-frequency = <100000000>;
|
|
+ supports-sdio;
|
|
+ bus-width = <4>;
|
|
+ disable-wp;
|
|
+ cap-sd-highspeed;
|
|
+ keep-power-in-suspend;
|
|
+ mmc-pwrseq = <&sdio_pwrseq>;
|
|
+ non-removable;
|
|
+ num-slots = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
|
+ sd-uhs-sdr104;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tcphy0 {
|
|
+ extcon = <&fusb0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tcphy1 {
|
|
+ extcon = <&fusb1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ /* tshut mode 0:CRU 1:GPIO */
|
|
+ rockchip,hw-tshut-mode = <1>;
|
|
+ /* tshut polarity 0:LOW 1:HIGH */
|
|
+ rockchip,hw-tshut-polarity = <1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0 {
|
|
+ status = "okay";
|
|
+ extcon = <&fusb0>;
|
|
+
|
|
+ u2phy0_otg: otg-port {
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ u2phy0_host: host-port {
|
|
+ phy-supply = <&vcc5v0_host>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&u2phy1 {
|
|
+ status = "okay";
|
|
+ extcon = <&fusb1>;
|
|
+
|
|
+ u2phy1_otg: otg-port {
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ u2phy1_host: host-port {
|
|
+ phy-supply = <&vcc5v0_host>;
|
|
+ status = "okay";
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd3_0 {
|
|
+ status = "okay";
|
|
+ extcon = <&fusb0>;
|
|
+};
|
|
+
|
|
+&usbdrd3_1 {
|
|
+ status = "okay";
|
|
+ extcon = <&fusb1>;
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3_0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3_1 {
|
|
+ status = "okay";
|
|
+ dr_mode = "host";
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_ohci {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ status = "okay";
|
|
+ max-freq = <48000000>;
|
|
+ dev-port = <0>;
|
|
+
|
|
+ spidev0: spidev@00 {
|
|
+ status = "okay";
|
|
+ //compatible = "linux,spidev";
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0x00>;
|
|
+ spi-max-frequency = <48000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm3 {
|
|
+ status = "okay";
|
|
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ compatible = "rockchip,remotectl-pwm";
|
|
+ pinctrl-names = "default";
|
|
+ remote_pwm_id = <3>;
|
|
+ handle_cpu_id = <0>;
|
|
+ remote_support_psci = <1>;
|
|
+
|
|
+ ir_key1 {
|
|
+ rockchip,usercode = <0x4040>;
|
|
+ rockchip,key_table =
|
|
+ <0xf2 KEY_REPLY>,
|
|
+ <0xba KEY_BACK>,
|
|
+ <0xf4 KEY_UP>,
|
|
+ <0xf1 KEY_DOWN>,
|
|
+ <0xef KEY_LEFT>,
|
|
+ <0xee KEY_RIGHT>,
|
|
+ <0xbd KEY_HOME>,
|
|
+ <0xea KEY_VOLUMEUP>,
|
|
+ <0xe3 KEY_VOLUMEDOWN>,
|
|
+ <0xe2 KEY_SEARCH>,
|
|
+ <0xb2 KEY_POWER>,
|
|
+ <0xbc KEY_MUTE>,
|
|
+ <0xec KEY_MENU>,
|
|
+ <0xbf 0x190>,
|
|
+ <0xe0 0x191>,
|
|
+ <0xe1 0x192>,
|
|
+ <0xe9 183>,
|
|
+ <0xe6 248>,
|
|
+ <0xe8 185>,
|
|
+ <0xe7 186>,
|
|
+ <0xf0 388>,
|
|
+ <0xbe 0x175>;
|
|
+ };
|
|
+
|
|
+ ir_key2 {
|
|
+ rockchip,usercode = <0xff00>;
|
|
+ rockchip,key_table =
|
|
+ <0xeb KEY_POWER>,
|
|
+ <0xec KEY_COMPOSE>,
|
|
+ <0xfe KEY_BACK>,
|
|
+ <0xb7 KEY_HOME>,
|
|
+ <0xa3 KEY_WWW>,
|
|
+ <0xf4 KEY_VOLUMEUP>,
|
|
+ <0xa7 KEY_VOLUMEDOWN>,
|
|
+ <0xf8 KEY_ENTER>,
|
|
+ <0xfc KEY_UP>,
|
|
+ <0xfd KEY_DOWN>,
|
|
+ <0xf1 KEY_LEFT>,
|
|
+ <0xe5 KEY_RIGHT>;
|
|
+ };
|
|
+
|
|
+ ir_key3 {
|
|
+ rockchip,usercode = <0x1dcc>;
|
|
+ rockchip,key_table =
|
|
+ <0xee KEY_REPLY>,
|
|
+ <0xf0 KEY_BACK>,
|
|
+ <0xf8 KEY_UP>,
|
|
+ <0xbb KEY_DOWN>,
|
|
+ <0xef KEY_LEFT>,
|
|
+ <0xed KEY_RIGHT>,
|
|
+ <0xfc KEY_HOME>,
|
|
+ <0xf1 KEY_VOLUMEUP>,
|
|
+ <0xfd KEY_VOLUMEDOWN>,
|
|
+ <0xb7 KEY_SEARCH>,
|
|
+ <0xff KEY_POWER>,
|
|
+ <0xf3 KEY_MUTE>,
|
|
+ <0xbf KEY_MENU>,
|
|
+ <0xf9 0x191>,
|
|
+ <0xf5 0x192>,
|
|
+ <0xb3 388>,
|
|
+ <0xbe KEY_1>,
|
|
+ <0xba KEY_2>,
|
|
+ <0xb2 KEY_3>,
|
|
+ <0xbd KEY_4>,
|
|
+ <0xf9 KEY_5>,
|
|
+ <0xb1 KEY_6>,
|
|
+ <0xfc KEY_7>,
|
|
+ <0xf8 KEY_8>,
|
|
+ <0xb0 KEY_9>,
|
|
+ <0xb6 KEY_0>,
|
|
+ <0xb5 KEY_BACKSPACE>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&vopb {
|
|
+ status = "okay";
|
|
+};
|
|
+&vopb_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+&vopl {
|
|
+ status = "okay";
|
|
+};
|
|
+&vopl_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+&vpu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif {
|
|
+ status = "okay";
|
|
+ pinctrl-0 = <&spdif_bus_1>;
|
|
+ i2c-scl-rising-time-ns = <450>;
|
|
+ i2c-scl-falling-time-ns = <15>;
|
|
+ #sound-dai-cells = <0>;
|
|
+};
|
|
+
|
|
+&mipi_dphy_rx0 {
|
|
+ status = "okay";
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mipi_in_ucam0: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&ucam_out0>;
|
|
+ data-lanes = <1 2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dphy_rx0_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&isp0_mipi_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&mipi_dphy_tx1rx1 {
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ mipi_in_ucam1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&ucam_out1>;
|
|
+ data-lanes = <1 2>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dphy_tx1rx1_out: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&isp1_mipi_in>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+
|
|
+&rkisp1_0 {
|
|
+ status = "disabled";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ isp0_mipi_in: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dphy_rx0_out>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&rkisp1_1 {
|
|
+ status = "disabled";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ isp1_mipi_in: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&dphy_tx1rx1_out>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cam0_default_pins {
|
|
+ rockchip,pins =
|
|
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
|
|
+};
|
|
+
|
|
+&vcc_mipi {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&dvdd_1v2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ov13850 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ov13850_1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkisp1_0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mipi_dphy_rx0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&isp0_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&rkisp1_1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mipi_dphy_tx1rx1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&isp1_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
--
|
|
Armbian
|
|
|