105 lines
3.5 KiB
Diff
105 lines
3.5 KiB
Diff
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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index d91df1cde736..75fbf7992a6a 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -23,6 +23,76 @@ qos_sata0: qos@fe190200 {
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reg = <0x0 0xfe190200 0x0 0x20>;
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};
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+ pcie3x2: pcie@fe280000 {
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+ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x20 0x2f>;
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+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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+ <&cru CLK_PCIE30X2_AUX_NDFT>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk", "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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+ <0 0 0 2 &pcie3x2_intc 1>,
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+ <0 0 0 3 &pcie3x2_intc 2>,
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+ <0 0 0 4 &pcie3x2_intc 3>;
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+ linux,pci-domain = <2>;
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+ num-ib-windows = <6>;
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+ num-ob-windows = <2>;
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+ max-link-speed = <3>;
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+ msi-map = <0x2000 &its 0x2000 0x1000>;
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+ num-lanes = <2>;
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+ phys = <&pcie30phy>;
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+ phy-names = "pcie-phy";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
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+ <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
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+ reg = <0x3 0xc0800000 0x0 0x400000>,
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+ <0x0 0xfe280000 0x0 0x10000>,
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+ <0x3 0x80000000 0x0 0x100000>;
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+ reg-names = "dbi", "apb", "config";
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+ resets = <&cru SRST_PCIE30X2_POWERUP>;
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+ reset-names = "pipe";
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+ /* rockchip,bifurcation; lane0 when using 1+1 */
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+ status = "disabled";
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+
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+ pcie3x2_intc: legacy-interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
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+ };
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+ };
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+
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+ pcie30phy: phy@fe8c0000 {
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+ compatible = "rockchip,rk3568-pcie3-phy";
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+ reg = <0x0 0xfe8c0000 0x0 0x20000>;
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+ #phy-cells = <0>;
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+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
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+ <&cru PCLK_PCIE30PHY>;
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+ clock-names = "refclk_m", "refclk_n", "pclk";
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+ resets = <&cru SRST_PCIE30PHY>;
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+ reset-names = "phy";
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+ rockchip,phy-grf = <&pcie30_phy_grf>;
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+ status = "disabled";
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+ };
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+
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+ pcie30_phy_grf: syscon@fdcb8000 {
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+ compatible = "rockchip,pcie30-phy-grf", "syscon";
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+ reg = <0x0 0xfdcb8000 0x0 0x10000>;
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+ };
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+
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gmac0: ethernet@fe2a0000 {
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compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe2a0000 0x0 0x10000>;
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 688e3585525a..5274a34c0fbf 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -199,9 +199,18 @@ gic: interrupt-controller@fd400000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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mbi-alias = <0x0 0xfd410000>;
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mbi-ranges = <296 24>;
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msi-controller;
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+ its: interrupt-controller@fd440000 {
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+ compatible = "arm,gic-v3-its";
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+ msi-controller;
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+ #msi-cells = <1>;
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+ reg = <0x0 0xfd440000 0x0 0x20000>;
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+ };
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};
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pmugrf: syscon@fdc20000 {
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