181 lines
4.3 KiB
Diff
181 lines
4.3 KiB
Diff
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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index 63a08f3f321d..4d6bfae0653c 100644
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--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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@@ -159,6 +159,21 @@ allOf:
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power-domains:
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maxItems: 1
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sram-supply: false
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ const: rockchip,rk3568-mali
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+ then:
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+ properties:
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+ clocks:
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+ minItems: 2
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+ clock-names:
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+ items:
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+ - const: gpu
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+ - const: bus
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+ required:
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+ - clock-names
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examples:
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- |
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index ff1689283996..50bbea862a6a 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -144,6 +144,40 @@ scmi_clk: protocol@14 {
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};
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};
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+ gpu_opp_table: opp-table-1 {
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+ compatible = "operating-points-v2";
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+
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ opp-microvolt = <825000>;
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+ };
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+
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+ opp-300000000 {
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+ opp-hz = /bits/ 64 <300000000>;
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+ opp-microvolt = <825000>;
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+ };
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+
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+ opp-400000000 {
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+ opp-hz = /bits/ 64 <400000000>;
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+ opp-microvolt = <825000>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <825000>;
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+ };
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+
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+ opp-700000000 {
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+ opp-hz = /bits/ 64 <700000000>;
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+ opp-microvolt = <900000>;
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+ };
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1000000>;
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+ };
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+ };
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+
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
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@@ -444,6 +478,21 @@ power-domain@RK3568_PD_RKVENC {
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};
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};
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+ gpu: gpu@fde60000 {
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+ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
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+ reg = <0x0 0xfde60000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "job", "mmu", "gpu";
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+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
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+ clock-names = "gpu", "bus";
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+ #cooling-cells = <2>;
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+ operating-points-v2 = <&gpu_opp_table>;
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+ power-domains = <&power RK3568_PD_GPU>;
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+ status = "disabled";
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+ };
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+
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sdmmc2: mmc@fe000000 {
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compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe000000 0x0 0x4000>;
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 50bbea862a6a..37194d735028 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -1093,6 +1093,33 @@ gpu_thermal: gpu-thermal {
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&tsadc 1>;
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+
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+ trips {
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+ gpu_threshold: gpu-threshold {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ gpu_target: gpu-target {
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+ temperature = <75000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ gpu_crit: gpu-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&gpu_target>;
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+ cooling-device =
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+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+
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};
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};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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index 3e65465ac7d5..b048db6cff3a 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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@@ -221,6 +221,11 @@ &gmac1m0_clkinout
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status = "okay";
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};
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+&gpu {
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+ mali-supply = <&vdd_gpu>;
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+ status = "okay";
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+};
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+
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&i2c0 {
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status = "okay";
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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index d8a4f7a9f562..39c495ff0157 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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@@ -140,6 +140,11 @@ &gmac1m1_rgmii_clk
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status = "okay";
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};
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+&gpu {
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+ mali-supply = <&vdd_gpu>;
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+ status = "okay";
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+};
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+
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&i2c0 {
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status = "okay";
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@@ -462,6 +467,12 @@ &sdmmc0 {
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status = "okay";
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};
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+&tsadc {
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+ rockchip,hw-tshut-mode = <1>;
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+ rockchip,hw-tshut-polarity = <0>;
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+ status = "okay";
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+};
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+
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&uart2 {
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status = "okay";
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};
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