231 lines
6.1 KiB
Diff
231 lines
6.1 KiB
Diff
Add the documentation for the rk3568-usb2phy-grf node, which is separate
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from the usb2phy node on this chip.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Acked-by: Rob Herring <robh@kernel.org>
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---
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Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
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index dfebf425ca49..b2ba7bed89b2 100644
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--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
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+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
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@@ -15,6 +15,7 @@ properties:
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- items:
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- enum:
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- rockchip,rk3288-sgrf
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+ - rockchip,rk3568-usb2phy-grf
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- rockchip,rv1108-usbgrf
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- const: syscon
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- items:
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 46d9552f6028..2c2b1014e53b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -204,6 +204,50 @@ gic: interrupt-controller@fd400000 {
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msi-controller;
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};
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+ usb_host0_ehci: usb@fd800000 {
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+ compatible = "generic-ehci";
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+ reg = <0x0 0xfd800000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_otg>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ usb_host0_ohci: usb@fd840000 {
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+ compatible = "generic-ohci";
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+ reg = <0x0 0xfd840000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_otg>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ehci: usb@fd880000 {
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+ compatible = "generic-ehci";
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+ reg = <0x0 0xfd880000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_host>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ohci: usb@fd8c0000 {
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+ compatible = "generic-ohci";
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+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_host>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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pmugrf: syscon@fdc20000 {
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compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc20000 0x0 0x10000>;
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@@ -219,6 +263,16 @@ grf: syscon@fdc60000 {
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reg = <0x0 0xfdc60000 0x0 0x10000>;
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};
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+ usb2phy0_grf: syscon@fdca0000 {
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+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
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+ reg = <0x0 0xfdca0000 0x0 0x8000>;
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+ };
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+
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+ usb2phy1_grf: syscon@fdca8000 {
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+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
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+ reg = <0x0 0xfdca8000 0x0 0x8000>;
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+ };
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+
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pipe_phy_grf1: syscon@fdc80000 {
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compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
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reg = <0x0 0xfdc80000 0x0 0x1000>;
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@@ -1077,6 +1131,50 @@ pwm15: pwm@fe700030 {
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status = "disabled";
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};
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+ u2phy0: usb2phy@fe8a0000 {
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+ compatible = "rockchip,rk3568-usb2phy";
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+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
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+ clocks = <&pmucru CLK_USBPHY0_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "clk_usbphy0_480m";
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+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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+ rockchip,usbgrf = <&usb2phy0_grf>;
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy0_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ u2phy0_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ u2phy1: usb2phy@fe8b0000 {
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+ compatible = "rockchip,rk3568-usb2phy";
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+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
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+ clocks = <&pmucru CLK_USBPHY1_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "clk_usbphy1_480m";
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+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ rockchip,usbgrf = <&usb2phy1_grf>;
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy1_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ u2phy1_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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pinctrl: pinctrl {
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compatible = "rockchip,rk3568-pinctrl";
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rockchip,grf = <&grf>;
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Add the nodes and regulators to enable usb2 support on the Quartz64
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Model A.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
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---
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.../boot/dts/rockchip/rk3566-quartz64-a.dts | 52 +++++++++++++++++++
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1 file changed, 52 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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index 4d4b2a301b1a..e5a70ff4e920 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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@@ -124,6 +124,22 @@ vcc5v0_usb: vcc5v0_usb {
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vin-supply = <&vcc12v_dcin>;
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};
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+ /* all four ports are controlled by one gpio
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+ * the host ports are sourced from vcc5v0_usb
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+ * the otg port is sourced from vcc5v0_midu
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+ */
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+ vcc5v0_usb20_host: vcc5v0_usb20_host {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb20_host";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_usb20_host_en>;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc5v0_usb>;
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+ };
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+
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vcc3v3_sd: vcc3v3_sd {
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compatible = "regulator-fixed";
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enable-active-low;
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@@ -477,6 +493,12 @@ pmic_int_l: pmic-int-l {
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};
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};
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+ usb2 {
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+ vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
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+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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vcc_sd {
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vcc_sd_h: vcc-sd-h {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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@@ -546,3 +568,33 @@ bluetooth {
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&uart2 {
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status = "okay";
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};
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+
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+&u2phy1_host {
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+ phy-supply = <&vcc5v0_usb20_host>;
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+ status = "okay";
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+};
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+
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+&u2phy1_otg {
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+ phy-supply = <&vcc5v0_usb20_host>;
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+ status = "okay";
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+};
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+
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+&u2phy1 {
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+ status = "okay";
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+};
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+
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+&usb_host0_ehci {
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+ status = "okay";
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+};
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+
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+&usb_host0_ohci {
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+ status = "okay";
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+};
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+
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+&usb_host1_ehci {
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+ status = "okay";
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+};
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+
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+&usb_host1_ohci {
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+ status = "okay";
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+};
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