70 lines
2.0 KiB
Diff
70 lines
2.0 KiB
Diff
From 8df7b4537dfb4c0a2a42de603927f5818cee0274 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Date: Mon, 30 Aug 2021 16:13:17 +0200
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Subject: [PATCH 062/478] arm64: dts: rockchip: add isp node for px30
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Add the rkisp1 node and iommu for the px30 soc.
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Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
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Link: https://lore.kernel.org/r/20210830141318.66744-1-heiko@sntech.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/px30.dtsi | 41 ++++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
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index 64f643145688..500ef3af2a49 100644
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--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
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@@ -1189,6 +1189,47 @@ vopl_mmu: iommu@ff470f00 {
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status = "disabled";
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};
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+ isp: isp@ff4a0000 {
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+ compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
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+ reg = <0x0 0xff4a0000 0x0 0x8000>;
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+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "isp", "mi", "mipi";
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+ clocks = <&cru SCLK_ISP>,
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+ <&cru ACLK_ISP>,
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+ <&cru HCLK_ISP>,
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+ <&cru PCLK_ISP>;
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+ clock-names = "isp", "aclk", "hclk", "pclk";
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+ iommus = <&isp_mmu>;
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+ phys = <&csi_dphy>;
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+ phy-names = "dphy";
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+ power-domains = <&power PX30_PD_VI>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+ };
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+
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+ isp_mmu: iommu@ff4a8000 {
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+ compatible = "rockchip,iommu";
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+ reg = <0x0 0xff4a8000 0x0 0x100>;
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+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
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+ clock-names = "aclk", "iface";
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+ power-domains = <&power PX30_PD_VI>;
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+ rockchip,disable-mmu-reset;
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+ #iommu-cells = <0>;
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+ };
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+
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qos_gmac: qos@ff518000 {
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compatible = "rockchip,px30-qos", "syscon";
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reg = <0x0 0xff518000 0x0 0x20>;
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--
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2.35.3
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