83 lines
2.8 KiB
Diff
83 lines
2.8 KiB
Diff
From 6e23e13f2778fe521aacb108c9a881f2521ce76f Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Thu, 22 Jul 2021 13:02:47 -0400
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Subject: [PATCH 091/478] arm64: dts: rockchip: add rk3568 pcie2x1 controller
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The pcie2x1 controller is commong between the rk3568 and rk3566. It is a
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single lane pcie2 compliant controller.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 55 ++++++++++++++++++++++++
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1 file changed, 55 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 340827747f5e..72e388212040 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -641,6 +641,61 @@ qos_vop_m1: qos@fe1a8100 {
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reg = <0x0 0xfe1a8100 0x0 0x20>;
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};
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+ pcie2x1: pcie@fe260000 {
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+ compatible = "rockchip,rk3568-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ bus-range = <0x0 0xf>;
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+ assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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+ <&cru CLK_PCIE20_AUX_NDFT>;
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+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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+ <&cru CLK_PCIE20_AUX_NDFT>;
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+ clock-names = "aclk_mst", "aclk_slv",
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+ "aclk_dbi", "pclk", "aux";
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+ device_type = "pci";
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+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "sys", "pmc", "msi", "legacy", "err";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
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+ <0 0 0 2 &pcie_intc 1>,
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+ <0 0 0 3 &pcie_intc 2>,
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+ <0 0 0 4 &pcie_intc 3>;
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+ linux,pci-domain = <0>;
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+ num-ib-windows = <6>;
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+ num-ob-windows = <2>;
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+ max-link-speed = <2>;
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+ msi-map = <0x0 &gic 0x0 0x1000>;
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+ num-lanes = <1>;
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+ phys = <&combphy2_psq PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ reg = <0x3 0xc0000000 0x0 0x400000>,
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+ <0x0 0xfe260000 0x0 0x10000>,
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+ <0x3 0x3f800000 0x0 0x800000>;
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+ ranges = <0x1000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000
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+ 0x2000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>;
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+ reg-names = "dbi", "apb", "config";
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+ resets = <&cru SRST_PCIE20_POWERUP>;
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+ reset-names = "pipe";
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+ status = "disabled";
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+
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+ pcie_intc: legacy-interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
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+ };
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+
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+ };
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+
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sdmmc0: mmc@fe2b0000 {
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compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe2b0000 0x0 0x4000>;
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--
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2.35.3
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