69 lines
2.5 KiB
Diff
69 lines
2.5 KiB
Diff
From 3d9170c3ea221f495902cc42fcea1c072c0af7c7 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 28 Jul 2021 14:00:29 -0400
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Subject: [PATCH 046/478] arm64: dts: rockchip: add rk356x gpio debounce clocks
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The rk356x added a debounce clock to the gpio devices. This clock is
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necessary for the new v2 gpio driver to bind.
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Add the clocks to the rk356x device tree.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 13b185e1dc5f..499a0c778a02 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -804,7 +804,7 @@ gpio0: gpio@fdd60000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xfdd60000 0x0 0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&pmucru PCLK_GPIO0>;
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+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -815,7 +815,7 @@ gpio1: gpio@fe740000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xfe740000 0x0 0x100>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&cru PCLK_GPIO1>;
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+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -826,7 +826,7 @@ gpio2: gpio@fe750000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xfe750000 0x0 0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&cru PCLK_GPIO2>;
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+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -837,7 +837,7 @@ gpio3: gpio@fe760000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xfe760000 0x0 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&cru PCLK_GPIO3>;
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+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -848,7 +848,7 @@ gpio4: gpio@fe770000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xfe770000 0x0 0x100>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&cru PCLK_GPIO4>;
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+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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--
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2.35.3
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