142 lines
3.9 KiB
Diff
142 lines
3.9 KiB
Diff
From 4626750340117573cc3cb30fa7b2eaffeb331336 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Mon, 12 Jul 2021 09:20:21 -0400
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Subject: [PATCH 087/478] arm64: dts: rockchip: add usb2 nodes to rk3568 device
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tree
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Add the requisite nodes to the rk3568 device tree to enable the usb2
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device controllers.
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Includes the usb2phy nodes, usb2phy grf nodes, and usb2 controller
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nodes.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 97 ++++++++++++++++++++++++
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1 file changed, 97 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 46d9552f6028..1767461d7b6d 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -204,6 +204,50 @@ gic: interrupt-controller@fd400000 {
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msi-controller;
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};
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+ usb_host0_ehci: usb@fd800000 {
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+ compatible = "generic-ehci";
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+ reg = <0x0 0xfd800000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_otg>;
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+ phy-names = "usb2-phy";
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+ status = "disabled";
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+ };
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+
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+ usb_host0_ohci: usb@fd840000 {
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+ compatible = "generic-ohci";
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+ reg = <0x0 0xfd840000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_otg>;
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+ phy-names = "usb2-phy";
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ehci: usb@fd880000 {
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+ compatible = "generic-ehci";
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+ reg = <0x0 0xfd880000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_host>;
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+ phy-names = "usb2-phy";
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ohci: usb@fd8c0000 {
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+ compatible = "generic-ohci";
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+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
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+ <&cru PCLK_USB>;
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+ phys = <&u2phy1_host>;
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+ phy-names = "usb2-phy";
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+ status = "disabled";
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+ };
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+
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pmugrf: syscon@fdc20000 {
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compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc20000 0x0 0x10000>;
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@@ -219,6 +263,16 @@ grf: syscon@fdc60000 {
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reg = <0x0 0xfdc60000 0x0 0x10000>;
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};
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+ usb2phy0_grf: syscon@fdca0000 {
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+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
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+ reg = <0x0 0xfdca0000 0x0 0x8000>;
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+ };
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+
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+ usb2phy1_grf: syscon@fdca8000 {
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+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
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+ reg = <0x0 0xfdca8000 0x0 0x8000>;
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+ };
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+
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pmucru: clock-controller@fdd00000 {
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compatible = "rockchip,rk3568-pmucru";
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reg = <0x0 0xfdd00000 0x0 0x1000>;
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@@ -1077,6 +1131,49 @@ pwm15: pwm@fe700030 {
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status = "disabled";
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};
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+ usb2phy0: usb2-phy@fe8a0000 {
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+ compatible = "rockchip,rk3568-usb2phy";
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+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
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+ clocks = <&pmucru CLK_USBPHY0_REF>;
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+ clock-names = "phyclk";
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+ #clock-cells = <0>;
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+ clock-output-names = "usb480m_phy";
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+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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+ rockchip,usbgrf = <&usb2phy0_grf>;
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+ status = "disabled";
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+
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+ u2phy0_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ u2phy0_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ usb2phy1: usb2-phy@fe8b0000 {
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+ compatible = "rockchip,rk3568-usb2phy";
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+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
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+ clocks = <&pmucru CLK_USBPHY1_REF>;
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+ clock-names = "phyclk";
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+ #clock-cells = <0>;
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+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ rockchip,usbgrf = <&usb2phy1_grf>;
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+ status = "disabled";
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+
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+ u2phy1_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ u2phy1_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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pinctrl: pinctrl {
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compatible = "rockchip,rk3568-pinctrl";
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rockchip,grf = <&grf>;
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--
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2.35.3
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