88 lines
2.3 KiB
Diff
88 lines
2.3 KiB
Diff
From c3dd497fbb272ba5446f52dcf75616398016ec29 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 28 Jul 2021 14:00:33 -0400
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Subject: [PATCH 034/478] arm64: dts: rockchip: enable gmac node on quartz64-a
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Enable the gmac controller on the Pine64 Quartz64 Model A.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20210728180034.717953-8-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3566-quartz64-a.dts | 38 +++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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index a3cdb6c2bec6..b239f314b38a 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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@@ -11,6 +11,7 @@ / {
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compatible = "pine64,quartz64-a", "rockchip,rk3566";
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aliases {
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+ ethernet0 = &gmac1;
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mmc0 = &sdmmc0;
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mmc1 = &sdhci;
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};
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@@ -19,6 +20,13 @@ chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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+ gmac1_clkin: external-gmac1-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac1_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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leds {
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compatible = "gpio-leds";
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@@ -116,6 +124,29 @@ &cpu3 {
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cpu-supply = <&vdd_cpu>;
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};
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+&gmac1 {
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+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
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+ clock_in_out = "input";
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+ phy-supply = <&vcc_3v3>;
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+ phy-mode = "rgmii";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac1m0_miim
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+ &gmac1m0_tx_bus2
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+ &gmac1m0_rx_bus2
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+ &gmac1m0_rgmii_clk
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+ &gmac1m0_clkinout
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+ &gmac1m0_rgmii_bus>;
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+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ /* Reset time is 20ms, 100ms for rtl8211f */
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+ snps,reset-delays-us = <0 20000 100000>;
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+ tx_delay = <0x30>;
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+ rx_delay = <0x10>;
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+ phy-handle = <&rgmii_phy1>;
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+ status = "okay";
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+};
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+
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&i2c0 {
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status = "okay";
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@@ -336,6 +367,13 @@ regulator-state-mem {
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};
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};
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+&mdio1 {
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+ rgmii_phy1: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ };
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+};
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+
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&pinctrl {
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bt {
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bt_enable_h: bt-enable-h {
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--
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2.35.3
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