84 lines
2.0 KiB
Diff
84 lines
2.0 KiB
Diff
From 7bc59fd74a28123a2c1751fcbb9e7f4b9dff142b Mon Sep 17 00:00:00 2001
|
|
From: Peter Geis <pgwipeout@gmail.com>
|
|
Date: Thu, 22 Jul 2021 13:51:30 -0400
|
|
Subject: [PATCH 092/478] arm64: dts: rockchip: enable pcie controller on
|
|
quartz64-a
|
|
|
|
Add the nodes to enable the pcie controller on the quartz64 model a
|
|
board.
|
|
|
|
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
|
---
|
|
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++
|
|
1 file changed, 34 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
|
|
index d83230cddf28..c07e8cb9e971 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
|
|
@@ -152,6 +152,18 @@ vcc5v0_usb20_host: vcc5v0_usb20_host {
|
|
vin-supply = <&vcc5v0_usb>;
|
|
};
|
|
|
|
+ vcc3v3_pcie_p: vcc3v3_pcie_p {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_enable_h>;
|
|
+ regulator-name = "vcc3v3_pcie_p";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ vin-supply = <&vcc_3v3>;
|
|
+ };
|
|
+
|
|
vcc3v3_sd: vcc3v3_sd {
|
|
compatible = "regulator-fixed";
|
|
enable-active-low;
|
|
@@ -188,6 +200,10 @@ vcc_wl: vcc_wl {
|
|
};
|
|
};
|
|
|
|
+&combphy2_psq {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&cpu0 {
|
|
cpu-supply = <&vdd_cpu>;
|
|
};
|
|
@@ -485,6 +501,14 @@ rgmii_phy1: ethernet-phy@0 {
|
|
};
|
|
};
|
|
|
|
+&pcie2x1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_reset_h>;
|
|
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie_p>;
|
|
+};
|
|
+
|
|
&pinctrl {
|
|
bt {
|
|
bt_enable_h: bt-enable-h {
|
|
@@ -510,6 +534,16 @@ diy_led_enable_h: diy-led-enable-h {
|
|
};
|
|
};
|
|
|
|
+ pcie {
|
|
+ pcie_enable_h: pcie-enable-h {
|
|
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie_reset_h: pcie-reset-h {
|
|
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
pmic {
|
|
pmic_int_l: pmic-int-l {
|
|
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
--
|
|
2.35.3
|
|
|