273 lines
7.3 KiB
Diff
273 lines
7.3 KiB
Diff
From b22ce8f1db276a0bc23c20a800e3f438df60737c Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Fri, 16 Aug 2019 16:38:57 +0200
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Subject: [PATCH 010/170] drv:net:phy: Add support for AC200 EPHY
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/net/phy/Kconfig | 7 ++
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/ac200.c | 220 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 228 insertions(+)
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create mode 100644 drivers/net/phy/ac200.c
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diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
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index 9fee639ee..cb9ad6790 100644
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -63,6 +63,13 @@ config SFP
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comment "MII PHY device drivers"
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+config AC200_PHY
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+ tristate "AC200 EPHY"
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+ depends on NVMEM
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+ depends on OF
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+ help
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+ Fast ethernet PHY as found in X-Powers AC200 multi-function device.
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+
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config AMD_PHY
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tristate "AMD PHYs"
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help
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diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
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index b12b1d86f..e3469be6f 100644
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -30,6 +30,7 @@ obj-$(CONFIG_SFP) += sfp.o
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sfp-obj-$(CONFIG_SFP) += sfp-bus.o
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obj-y += $(sfp-obj-y) $(sfp-obj-m)
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+obj-$(CONFIG_AC200_PHY) += ac200.o
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obj-$(CONFIG_ADIN_PHY) += adin.o
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obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
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obj-$(CONFIG_AMD_PHY) += amd.o
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diff --git a/drivers/net/phy/ac200.c b/drivers/net/phy/ac200.c
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new file mode 100644
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index 000000000..cb713188f
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--- /dev/null
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+++ b/drivers/net/phy/ac200.c
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@@ -0,0 +1,220 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/**
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+ * Driver for AC200 Ethernet PHY
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+ *
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+ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/mfd/ac200.h>
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+#include <linux/nvmem-consumer.h>
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+#include <linux/of.h>
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+#include <linux/phy.h>
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+#include <linux/platform_device.h>
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+
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+#define AC200_EPHY_ID 0x00441400
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+#define AC200_EPHY_ID_MASK 0x0ffffff0
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+
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+/* macros for system ephy control 0 register */
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+#define AC200_EPHY_RESET_INVALID BIT(0)
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+#define AC200_EPHY_SYSCLK_GATING BIT(1)
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+
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+/* macros for system ephy control 1 register */
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+#define AC200_EPHY_E_EPHY_MII_IO_EN BIT(0)
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+#define AC200_EPHY_E_LNK_LED_IO_EN BIT(1)
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+#define AC200_EPHY_E_SPD_LED_IO_EN BIT(2)
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+#define AC200_EPHY_E_DPX_LED_IO_EN BIT(3)
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+
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+/* macros for ephy control register */
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+#define AC200_EPHY_SHUTDOWN BIT(0)
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+#define AC200_EPHY_LED_POL BIT(1)
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+#define AC200_EPHY_CLK_SEL BIT(2)
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+#define AC200_EPHY_ADDR(x) (((x) & 0x1F) << 4)
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+#define AC200_EPHY_XMII_SEL BIT(11)
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+#define AC200_EPHY_CALIB(x) (((x) & 0xF) << 12)
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+
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+struct ac200_ephy_dev {
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+ struct clk *clk;
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+ struct phy_driver *ephy;
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+ struct regmap *regmap;
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+};
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+
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+static char *ac200_phy_name = "AC200 EPHY";
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+
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+static int ac200_ephy_config_init(struct phy_device *phydev)
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+{
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+ const struct ac200_ephy_dev *priv = phydev->drv->driver_data;
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+ unsigned int value;
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+ int ret;
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+
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+ phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
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+ phy_write(phydev, 0x12, 0x4824); /* Disable APS */
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+
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+ phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
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+ phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
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+
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+ phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
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+ phy_write(phydev, 0x14, 0x708f); /* PHYAFE TX optimization */
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+ phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */
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+ phy_write(phydev, 0x15, 0x1530);
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+
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+ phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 6 */
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+ phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
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+
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+ phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
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+ phy_clear_bits(phydev, 0x17, BIT(3)); /* disable intelligent IEEE */
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+
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+ /* next two blocks disable 802.3az IEEE */
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+ phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */
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+ phy_write(phydev, 0x18, 0x0000);
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+
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+ phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
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+ phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RMII)
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+ value = AC200_EPHY_XMII_SEL;
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+ else
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+ value = 0;
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+
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+ ret = regmap_update_bits(priv->regmap, AC200_EPHY_CTL,
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+ AC200_EPHY_XMII_SEL, value);
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+ if (ret)
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+ return ret;
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+
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+ /* FIXME: This is H6 specific */
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+ phy_set_bits(phydev, 0x13, BIT(12));
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+
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+ return 0;
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+}
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+
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+static int ac200_ephy_probe(struct platform_device *pdev)
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+{
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+ struct ac200_dev *ac200 = dev_get_drvdata(pdev->dev.parent);
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+ struct device *dev = &pdev->dev;
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+ struct ac200_ephy_dev *priv;
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+ struct nvmem_cell *calcell;
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+ struct phy_driver *ephy;
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+ u16 *caldata, calib;
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+ size_t callen;
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+ int ret;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
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+ if (!ephy)
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+ return -ENOMEM;
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+
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+ priv->clk = devm_clk_get(dev, NULL);
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+ if (IS_ERR(priv->clk)) {
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+ dev_err(dev, "Can't obtain the clock!\n");
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+ return PTR_ERR(priv->clk);
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+ }
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+
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+ calcell = devm_nvmem_cell_get(dev, "calibration");
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+ if (IS_ERR(calcell)) {
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+ dev_err(dev, "Unable to find calibration data!\n");
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+ return PTR_ERR(calcell);
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+ }
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+
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+ caldata = nvmem_cell_read(calcell, &callen);
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+ if (IS_ERR(caldata)) {
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+ dev_err(dev, "Unable to read calibration data!\n");
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+ return PTR_ERR(caldata);
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+ }
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+
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+ if (callen != 2) {
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+ dev_err(dev, "Calibration data has wrong length: 2 != %zu\n",
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+ callen);
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+ kfree(caldata);
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+ return -EINVAL;
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+ }
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+
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+ calib = *caldata + 3;
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+ kfree(caldata);
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+
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+ ret = clk_prepare_enable(priv->clk);
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+ if (ret)
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+ return ret;
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+
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+ ephy->phy_id = AC200_EPHY_ID;
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+ ephy->phy_id_mask = AC200_EPHY_ID_MASK;
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+ ephy->name = ac200_phy_name;
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+ ephy->driver_data = priv;
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+ ephy->soft_reset = genphy_soft_reset;
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+ ephy->config_init = ac200_ephy_config_init;
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+ ephy->suspend = genphy_suspend;
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+ ephy->resume = genphy_resume;
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+
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+ priv->ephy = ephy;
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+ priv->regmap = ac200->regmap;
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+ platform_set_drvdata(pdev, priv);
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+
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+ ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL0,
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+ AC200_EPHY_RESET_INVALID |
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+ AC200_EPHY_SYSCLK_GATING);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL1,
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+ AC200_EPHY_E_EPHY_MII_IO_EN |
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+ AC200_EPHY_E_LNK_LED_IO_EN |
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+ AC200_EPHY_E_SPD_LED_IO_EN |
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+ AC200_EPHY_E_DPX_LED_IO_EN);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(ac200->regmap, AC200_EPHY_CTL,
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+ AC200_EPHY_LED_POL |
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+ AC200_EPHY_CLK_SEL |
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+ AC200_EPHY_ADDR(1) |
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+ AC200_EPHY_CALIB(calib));
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+ if (ret)
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+ return ret;
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+
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+ ret = phy_driver_register(priv->ephy, THIS_MODULE);
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+ if (ret) {
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+ dev_err(dev, "Unable to register phy\n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int ac200_ephy_remove(struct platform_device *pdev)
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+{
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+ struct ac200_ephy_dev *priv = platform_get_drvdata(pdev);
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+
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+ phy_driver_unregister(priv->ephy);
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+
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+ regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
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+ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
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+ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
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+
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+ clk_disable_unprepare(priv->clk);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id ac200_ephy_match[] = {
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+ { .compatible = "x-powers,ac200-ephy" },
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+ { /* sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(of, ac200_ephy_match);
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+
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+static struct platform_driver ac200_ephy_driver = {
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+ .probe = ac200_ephy_probe,
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+ .remove = ac200_ephy_remove,
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+ .driver = {
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+ .name = "ac200-ephy",
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+ .of_match_table = ac200_ephy_match,
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+ },
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+};
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+module_platform_driver(ac200_ephy_driver);
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+
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+MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
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+MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
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+MODULE_LICENSE("GPL");
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--
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2.35.3
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