71 lines
2.7 KiB
Diff
71 lines
2.7 KiB
Diff
From 1e08b7c4205020df61237a6ce756e55da5ad9a92 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Sat, 24 Sep 2022 21:59:07 +0200
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Subject: [PATCH 186/389] arm64: dts: rockchip: rk356x: Fix PCIe register map
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and ranges
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I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge
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to Quartz64-A. The cards fail to work, when nvme SSD is connected at the
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same time to the bridge. Without nvme connected, cards work fine. The
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issue seems to be related to mixed use of devices which make use of I/O
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ranges and memory ranges.
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This patch changes I/O, MEM and config mappings so that config and I/O
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mappings use the 0xf4000000 outbound address space, and MEM range uses
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the whole 0x300000000 outbound space.
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These values were suggested by pgwipeout:
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https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10
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This is identical to how BSP does the mappings.
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This change to the regs/ranges makes the issue go away and both nvme and
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wifi cards work when connected at the same time to the bridge. I tested
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the nvme with large amount of reads/writes, both behind the PCIe bridge
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and when directly connected to Quartz64-A board.
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++----
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1 file changed, 7 insertions(+), 4 deletions(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 164708f1eb67..726c948ccbf0 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -951,7 +951,8 @@ pcie2x1: pcie@fe260000 {
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0000000 0x0 0x00400000>,
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<0x0 0xfe260000 0x0 0x00010000>,
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- <0x3 0x3f000000 0x0 0x01000000>;
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+ <0x0 0xf4000000 0x0 0x00100000>;
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+
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reg-names = "dbi", "apb", "config";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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@@ -973,15 +974,17 @@ pcie2x1: pcie@fe260000 {
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<0 0 0 4 &pcie_intc 3>;
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linux,pci-domain = <0>;
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num-ib-windows = <6>;
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- num-ob-windows = <2>;
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+ num-ob-windows = <8>;
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max-link-speed = <2>;
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msi-map = <0x0 &gic 0x0 0x1000>;
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num-lanes = <1>;
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
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- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
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+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
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+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
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+
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resets = <&cru SRST_PCIE20_POWERUP>;
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reset-names = "pipe";
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#address-cells = <3>;
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--
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2.35.3
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