87 lines
2.3 KiB
Diff
87 lines
2.3 KiB
Diff
From e5fa6fb0cf7f46011b23c867156d3332d269a113 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Thu, 4 May 2023 23:06:48 +0300
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Subject: [PATCH 452/469] arm64: dts: rockchip: Add rk3588 OTP node
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Add DT node for Rockchip RK3588/RK3588S OTP memory.
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Co-developed-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
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[moved cpu-version subnode down, to be sorted by address]
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Link: https://lore.kernel.org/r/20230504200648.1119866-9-cristian.ciocaltea@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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index 67cc3341e198..a33e646af647 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -2551,6 +2551,60 @@ spi4: spi@fecb0000 {
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status = "disabled";
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};
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+ otp: efuse@fecc0000 {
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+ compatible = "rockchip,rk3588-otp";
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+ reg = <0x0 0xfecc0000 0x0 0x400>;
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+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
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+ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
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+ clock-names = "otp", "apb_pclk", "phy", "arb";
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+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
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+ <&cru SRST_OTPC_ARB>;
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+ reset-names = "otp", "apb", "arb";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpu_code: cpu-code@2 {
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+ reg = <0x02 0x2>;
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+ };
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+
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+ otp_id: id@7 {
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+ reg = <0x07 0x10>;
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+ };
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+
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+ cpub0_leakage: cpu-leakage@17 {
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+ reg = <0x17 0x1>;
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+ };
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+
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+ cpub1_leakage: cpu-leakage@18 {
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+ reg = <0x18 0x1>;
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+ };
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+
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+ cpul_leakage: cpu-leakage@19 {
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+ reg = <0x19 0x1>;
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+ };
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+
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+ log_leakage: log-leakage@1a {
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+ reg = <0x1a 0x1>;
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+ };
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+
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+ gpu_leakage: gpu-leakage@1b {
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+ reg = <0x1b 0x1>;
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+ };
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+
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+ otp_cpu_version: cpu-version@1c {
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+ reg = <0x1c 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ npu_leakage: npu-leakage@28 {
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+ reg = <0x28 0x1>;
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+ };
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+
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+ codec_leakage: codec-leakage@29 {
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+ reg = <0x29 0x1>;
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+ };
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+ };
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+
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dmac2: dma-controller@fed10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xfed10000 0x0 0x4000>;
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--
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2.34.1
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