117 lines
3.6 KiB
Diff
117 lines
3.6 KiB
Diff
From f765feb2cdf487c6f644f05a2a7868d0c4cc7420 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Thu, 6 Apr 2023 17:14:19 +0200
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Subject: [PATCH 427/469] arm64: dts: rockchip: rk3588: add SATA support
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Add all three SATA IP blocks to the RK3588 DT.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++
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2 files changed, 71 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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index 9d8539b5309b..b9508cea34f1 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -129,6 +129,29 @@ gmac0_mtl_tx_setup: tx-queues-config {
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};
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};
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+ sata1: sata@fe220000 {
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+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
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+ reg = <0 0xfe220000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
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+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
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+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
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+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
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+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
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+ ports-implemented = <0x1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ sata-port@0 {
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+ reg = <0>;
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+ hba-port-cap = <HBA_PORT_FBSCP>;
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+ phys = <&combphy1_ps PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ snps,rx-ts-max = <32>;
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+ snps,tx-ts-max = <32>;
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+ };
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+ };
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+
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combphy1_ps: phy@fee10000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee10000 0x0 0x100>;
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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index 45ae457a22a4..00a91b08e3bb 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -9,6 +9,8 @@
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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#include <dt-bindings/thermal/thermal.h>
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+#include <dt-bindings/phy/phy.h>
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+#include <dt-bindings/ata/ahci.h>
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/ {
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compatible = "rockchip,rk3588";
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@@ -1717,6 +1719,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
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};
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};
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+ sata0: sata@fe210000 {
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+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
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+ reg = <0 0xfe210000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
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+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
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+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
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+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
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+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
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+ ports-implemented = <0x1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ sata-port@0 {
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+ reg = <0>;
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+ hba-port-cap = <HBA_PORT_FBSCP>;
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+ phys = <&combphy0_ps PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ snps,rx-ts-max = <32>;
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+ snps,tx-ts-max = <32>;
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+ };
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+ };
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+
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+ sata2: sata@fe230000 {
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+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
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+ reg = <0 0xfe230000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
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+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
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+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
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+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
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+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
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+ ports-implemented = <0x1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ sata-port@0 {
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+ reg = <0>;
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+ hba-port-cap = <HBA_PORT_FBSCP>;
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+ phys = <&combphy2_psu PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ snps,rx-ts-max = <32>;
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+ snps,tx-ts-max = <32>;
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+ };
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+ };
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+
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sdmmc: mmc@fe2c0000 {
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compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe2c0000 0x0 0x4000>;
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--
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2.34.1
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