127 lines
4.0 KiB
Diff
127 lines
4.0 KiB
Diff
From f76fd583988b4720c93c4fbbb0c77ede756cda13 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Thu, 12 Jan 2023 19:20:37 +0100
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Subject: [PATCH 421/469] arm64: dts: rockchip: rk3588: add USB2 support
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This adds USB2 (EHCI & OHCI) ports including the related PHYs
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and GRF modules to the rk3588(s) device tree.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 94 +++++++++++++++++++++++
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1 file changed, 94 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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index 8658d9b96e5e..01058fed8f96 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -830,11 +830,105 @@ scmi_shmem: sram@0 {
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};
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};
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+ usb_host0_ehci: usb@fc800000 {
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+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
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+ reg = <0x0 0xfc800000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host0_ohci: usb@fc840000 {
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+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
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+ reg = <0x0 0xfc840000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ehci: usb@fc880000 {
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+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
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+ reg = <0x0 0xfc880000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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+ usb_host1_ohci: usb@fc8c0000 {
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+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
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+ reg = <0x0 0xfc8c0000 0x0 0x40000>;
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+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb";
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+ power-domains = <&power RK3588_PD_USB>;
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+ status = "disabled";
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+ };
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+
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sys_grf: syscon@fd58c000 {
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compatible = "rockchip,rk3588-sys-grf", "syscon";
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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};
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+ usb2phy2_grf: syscon@fd5d8000 {
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+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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+ reg = <0x0 0xfd5d8000 0x0 0x4000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ u2phy2: usb2-phy@8000 {
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+ compatible = "rockchip,rk3588-usb2phy";
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+ reg = <0x8000 0x10>;
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+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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+ reset-names = "phy", "apb";
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "usb480m_phy2";
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy2_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ usb2phy3_grf: syscon@fd5dc000 {
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+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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+ reg = <0x0 0xfd5dc000 0x0 0x4000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ u2phy3: usb2-phy@c000 {
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+ compatible = "rockchip,rk3588-usb2phy";
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+ reg = <0xc000 0x10>;
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+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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+ reset-names = "phy", "apb";
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "usb480m_phy3";
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy3_host: host-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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bigcore0_grf: syscon@fd590000 {
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compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
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reg = <0x0 0xfd590000 0x0 0x100>;
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--
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2.34.1
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