115 lines
3.7 KiB
Diff
115 lines
3.7 KiB
Diff
From ef434c0b80978f59424e12da6f29f516b5751cc8 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Thu, 6 Apr 2023 16:54:11 +0200
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Subject: [PATCH 426/469] arm64: dts: rockchip: rk3588: add combo PHYs
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Add all 3 combo PHYs that can be found in RK3588.
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They are used for SATA, PCIe or USB3.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++
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2 files changed, 63 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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index 8be75556af8f..9d8539b5309b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -7,6 +7,11 @@
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#include "rk3588-pinctrl.dtsi"
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/ {
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+ pipe_phy1_grf: syscon@fd5c0000 {
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+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfd5c0000 0x0 0x100>;
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+ };
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+
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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@@ -123,4 +128,20 @@ gmac0_mtl_tx_setup: tx-queues-config {
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queue1 {};
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};
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};
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+
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+ combphy1_ps: phy@fee10000 {
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+ compatible = "rockchip,rk3588-naneng-combphy";
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+ reg = <0x0 0xfee10000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
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+ <&cru PCLK_PHP_ROOT>;
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+ clock-names = "ref", "apb", "pipe";
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+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
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+ assigned-clock-rates = <100000000>;
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+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
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+ reset-names = "phy", "apb";
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+ rockchip,pipe-grf = <&php_grf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
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+ status = "disabled";
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+ };
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};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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index 01058fed8f96..45ae457a22a4 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -944,6 +944,16 @@ php_grf: syscon@fd5b0000 {
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reg = <0x0 0xfd5b0000 0x0 0x1000>;
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};
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+ pipe_phy0_grf: syscon@fd5bc000 {
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+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfd5bc000 0x0 0x100>;
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+ };
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+
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+ pipe_phy2_grf: syscon@fd5c4000 {
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+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfd5c4000 0x0 0x100>;
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+ };
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+
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ioc: syscon@fd5f0000 {
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compatible = "rockchip,rk3588-ioc", "syscon";
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reg = <0x0 0xfd5f0000 0x0 0x10000>;
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@@ -2371,6 +2381,38 @@ dmac2: dma-controller@fed10000 {
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#dma-cells = <1>;
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};
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+ combphy0_ps: phy@fee00000 {
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+ compatible = "rockchip,rk3588-naneng-combphy";
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+ reg = <0x0 0xfee00000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
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+ <&cru PCLK_PHP_ROOT>;
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+ clock-names = "ref", "apb", "pipe";
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+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
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+ assigned-clock-rates = <100000000>;
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+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
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+ reset-names = "phy", "apb";
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+ rockchip,pipe-grf = <&php_grf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
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+ status = "disabled";
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+ };
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+
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+ combphy2_psu: phy@fee20000 {
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+ compatible = "rockchip,rk3588-naneng-combphy";
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+ reg = <0x0 0xfee20000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
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+ <&cru PCLK_PHP_ROOT>;
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+ clock-names = "ref", "apb", "pipe";
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+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
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+ assigned-clock-rates = <100000000>;
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+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
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+ reset-names = "phy", "apb";
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+ rockchip,pipe-grf = <&php_grf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
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+ status = "disabled";
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+ };
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+
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system_sram2: sram@ff001000 {
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compatible = "mmio-sram";
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reg = <0x0 0xff001000 0x0 0xef000>;
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--
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2.34.1
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