135 lines
4.0 KiB
Diff
135 lines
4.0 KiB
Diff
From a38cf956cfe7f113fadf8788c604f1935843bedd Mon Sep 17 00:00:00 2001
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From: Simon Xue <xxm@rock-chips.com>
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Date: Thu, 25 May 2023 00:23:34 +0530
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Subject: [PATCH 437/469] iio: adc: rockchip_saradc: Add support for RK3588
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Add new start and read functions to support rk3588 device.
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Also, add a device compatible string for the same.
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Signed-off-by: Simon Xue <xxm@rock-chips.com>
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Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++
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1 file changed, 70 insertions(+)
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diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
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index 21f9d92a6af4..257f0a80c08d 100644
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--- a/drivers/iio/adc/rockchip_saradc.c
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+++ b/drivers/iio/adc/rockchip_saradc.c
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@@ -4,6 +4,7 @@
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*/
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+#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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@@ -38,6 +39,22 @@
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#define SARADC_TIMEOUT msecs_to_jiffies(100)
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#define SARADC_MAX_CHANNELS 8
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+/* v2 registers */
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+#define SARADC2_CONV_CON 0x000
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+#define SARADC_T_PD_SOC 0x004
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+#define SARADC_T_DAS_SOC 0x00c
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+#define SARADC2_END_INT_EN 0x104
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+#define SARADC2_ST_CON 0x108
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+#define SARADC2_STATUS 0x10c
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+#define SARADC2_END_INT_ST 0x110
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+#define SARADC2_DATA_BASE 0x120
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+
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+#define SARADC2_EN_END_INT BIT(0)
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+#define SARADC2_START BIT(4)
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+#define SARADC2_SINGLE_MODE BIT(5)
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+
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+#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
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+
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struct rockchip_saradc;
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struct rockchip_saradc_data {
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@@ -76,6 +93,25 @@ static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
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SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
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}
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+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
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+{
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+ int val;
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+
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+ if (info->reset)
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+ rockchip_saradc_reset_controller(info->reset);
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+
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+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
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+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
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+ val = FIELD_PREP(SARADC2_EN_END_INT, 1);
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+ val |= val << 16;
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+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
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+ val = FIELD_PREP(SARADC2_START, 1) |
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+ FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
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+ FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
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+ val |= val << 16;
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+ writel(val, info->regs + SARADC2_CONV_CON);
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+}
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+
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static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
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{
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info->data->start(info, chn);
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@@ -86,6 +122,18 @@ static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
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return readl_relaxed(info->regs + SARADC_DATA);
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}
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+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
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+{
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+ int offset;
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+
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+ /* Clear irq */
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+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
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+
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+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
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+
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+ return readl_relaxed(info->regs + offset);
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+}
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+
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static int rockchip_saradc_read(struct rockchip_saradc *info)
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{
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return info->data->read(info);
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@@ -248,6 +296,25 @@ static const struct rockchip_saradc_data rk3568_saradc_data = {
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.power_down = rockchip_saradc_power_down_v1,
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};
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+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
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+ SARADC_CHANNEL(0, "adc0", 12),
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+ SARADC_CHANNEL(1, "adc1", 12),
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+ SARADC_CHANNEL(2, "adc2", 12),
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+ SARADC_CHANNEL(3, "adc3", 12),
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+ SARADC_CHANNEL(4, "adc4", 12),
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+ SARADC_CHANNEL(5, "adc5", 12),
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+ SARADC_CHANNEL(6, "adc6", 12),
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+ SARADC_CHANNEL(7, "adc7", 12),
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+};
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+
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+static const struct rockchip_saradc_data rk3588_saradc_data = {
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+ .channels = rockchip_rk3588_saradc_iio_channels,
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+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
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+ .clk_rate = 1000000,
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+ .start = rockchip_saradc_start_v2,
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+ .read = rockchip_saradc_read_v2,
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+};
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+
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static const struct of_device_id rockchip_saradc_match[] = {
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{
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.compatible = "rockchip,saradc",
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@@ -261,6 +328,9 @@ static const struct of_device_id rockchip_saradc_match[] = {
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}, {
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.compatible = "rockchip,rk3568-saradc",
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.data = &rk3568_saradc_data,
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+ }, {
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+ .compatible = "rockchip,rk3588-saradc",
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+ .data = &rk3588_saradc_data,
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},
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{},
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};
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--
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2.34.1
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