153 lines
4.8 KiB
Diff
153 lines
4.8 KiB
Diff
From 5e4e66f0c2d623ef547c0547af7475124fdb367b Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Mon, 3 Apr 2023 20:24:06 +0200
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Subject: [PATCH 417/469] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning
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support
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On RK3588 some registers need to be tweaked to support waking up from
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suspend when a USB device is plugged into a port from a suspended PHY.
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Without this change USB devices only work when they are plugged at
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boot time.
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Apart from that it optimizes settings to avoid devices toggling
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between fullspeed and highspeed mode.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++
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1 file changed, 63 insertions(+)
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diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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index 101b46939f0b..aa8c55609c0d 100644
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--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@@ -33,6 +33,8 @@
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#define SCHEDULE_DELAY (60 * HZ)
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#define OTG_SCHEDULE_DELAY (2 * HZ)
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+struct rockchip_usb2phy;
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+
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enum rockchip_usb2phy_port_id {
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USB2PHY_PORT_OTG,
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USB2PHY_PORT_HOST,
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@@ -163,6 +165,7 @@ struct rockchip_usb2phy_port_cfg {
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* struct rockchip_usb2phy_cfg - usb-phy configuration.
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* @reg: the address offset of grf for usb-phy config.
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* @num_ports: specify how many ports that the phy has.
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+ * @phy_tuning: phy default parameters tuning.
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* @clkout_ctl: keep on/turn off output clk of phy.
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* @port_cfgs: usb-phy port configurations.
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* @chg_det: charger detection registers.
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@@ -170,6 +173,7 @@ struct rockchip_usb2phy_port_cfg {
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struct rockchip_usb2phy_cfg {
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unsigned int reg;
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unsigned int num_ports;
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+ int (*phy_tuning)(struct rockchip_usb2phy *rphy);
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struct usb2phy_reg clkout_ctl;
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const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
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const struct rockchip_chg_det_reg chg_det;
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@@ -1400,6 +1404,12 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
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goto disable_clks;
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}
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+ if (rphy->phy_cfg->phy_tuning) {
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+ ret = rphy->phy_cfg->phy_tuning(rphy);
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+ if (ret)
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+ goto disable_clks;
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+ }
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+
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index = 0;
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for_each_available_child_of_node(np, child_np) {
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struct rockchip_usb2phy_port *rport = &rphy->ports[index];
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@@ -1468,6 +1478,55 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
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return ret;
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}
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+static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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+{
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+ int ret;
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+ bool usb3otg = false;
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+ /*
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+ * utmi_termselect = 1'b1 (en FS terminations)
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+ * utmi_xcvrselect = 2'b01 (FS transceiver)
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+ */
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+ int suspend_cfg = 0x14;
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+
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+ if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
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+ /* USB2 config for USB3_0 and USB3_1 */
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+ suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */
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+ usb3otg = true;
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+ } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {
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+ /* USB2 config for USB2_0 and USB2_1 */
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+ suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */
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+ } else {
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+ return -EINVAL;
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+ }
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+
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+ /* Deassert SIDDQ to power on analog block */
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+ ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);
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+ if (ret)
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+ return ret;
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+
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+ /* Do reset after exit IDDQ mode */
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+ ret = rockchip_usb2phy_reset(rphy);
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+ if (ret)
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+ return ret;
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+
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+ /* suspend configuration */
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+ ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);
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+
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+ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
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+ ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);
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+
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+ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
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+ ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);
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+
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+ if (!usb3otg)
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+ return ret;
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+
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+ /* Pullup iddig pin for USB3_0 OTG mode */
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+ ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);
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+
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+ return ret;
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+}
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+
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static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
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{
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.reg = 0x760,
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@@ -1785,6 +1844,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
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{
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.reg = 0x0000,
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.num_ports = 1,
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+ .phy_tuning = rk3588_usb2phy_tuning,
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.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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@@ -1821,6 +1881,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
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{
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.reg = 0x4000,
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.num_ports = 1,
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+ .phy_tuning = rk3588_usb2phy_tuning,
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.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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@@ -1857,6 +1918,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
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{
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.reg = 0x8000,
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.num_ports = 1,
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+ .phy_tuning = rk3588_usb2phy_tuning,
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.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_HOST] = {
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@@ -1877,6 +1939,7 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
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{
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.reg = 0xc000,
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.num_ports = 1,
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+ .phy_tuning = rk3588_usb2phy_tuning,
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.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_HOST] = {
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--
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2.34.1
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