build/patch/kernel/archive/rk322x-4.4/board-rk322x-box.patch

275 lines
6.7 KiB
Diff

diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
new file mode 100644
index 00000000..fbd19649
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+++ b/arch/arm/boot/dts/rk322x-box.dts
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3228a-box.dtsi"
+
+/ {
+
+ model = "Generic RK322x TV Box board";
+
+ gpio_leds: gpio-leds {
+
+ compatible = "gpio-leds";
+
+ working {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_working>;
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+ label = "working";
+ default-state = "on";
+ linux,default-trigger = "timer";
+ };
+
+ };
+
+ gpio_keys: gpio-keys {
+
+ compatible = "gpio-keys";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
+ };
+
+};
+
+/** Integration to pin controller */
+&pinctrl {
+
+ pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+ drive-strength = <12>;
+ bias-pull-up;
+ };
+
+ pcfg_pull_down_12ma: pcfg-pull-down-12ma {
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+
+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ pcfg_pull_down_8ma: pcfg-pull-down-8ma {
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcfg_pull_down_2ma: pcfg-pull-down-2ma {
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcfg_pull_none_2ma: pcfg-pull-none-2ma {
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /*
+ * Some rk322x electrical schemes report this kind of pull-up/down
+ * pin configurations. We set them here, but we don't use it in this
+ * device tree. These instead are useful for overlays, because they seem
+ * to increase stability on at least one board I got here
+ */
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_down>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>,
+ <1 19 RK_FUNC_1 &pcfg_pull_up>,
+ <1 20 RK_FUNC_1 &pcfg_pull_up>,
+ <1 21 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ /*
+ * Same as above, decreasing strength of SDIO pins seems to be benefical
+ * to stability
+ */
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_down_2ma>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_up_2ma>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up_2ma>,
+ <3 3 RK_FUNC_1 &pcfg_pull_up_2ma>,
+ <3 4 RK_FUNC_1 &pcfg_pull_up_2ma>,
+ <3 5 RK_FUNC_1 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ /*
+ * Same drill as above, electrical schemes also report this pull-up/down
+ * configurations.
+ */
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_up>,
+ <1 25 RK_FUNC_2 &pcfg_pull_up>,
+ <1 26 RK_FUNC_2 &pcfg_pull_up>,
+ <1 27 RK_FUNC_2 &pcfg_pull_up>,
+ <1 28 RK_FUNC_2 &pcfg_pull_up>,
+ <1 29 RK_FUNC_2 &pcfg_pull_up>,
+ <1 30 RK_FUNC_2 &pcfg_pull_up>,
+ <1 31 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_pwr: emmc-pwr {
+ rockchip,pins = <2 RK_PA5 RK_FUNC_2 &pcfg_pull_down>;
+ };
+
+ emmc_rst: emmc-rst {
+ rockchip,pins = <1 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ };
+
+ gpio {
+ gpio_led_working: gpio-led-working {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+/** MMC and NAND controller and interfaces */
+
+&emmc {
+ status = "okay";
+};
+
+&sdio {
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+};
+
+&sdmmc {
+ cd-debounce-delay-ms = <500>;
+ status = "okay";
+};
+
+&nandc {
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+};
+
+// GPU voltages are raised a bit to raise logic voltage
+// that has to handle DDR3@660 Mhz from ddrbin.
+&gpu_opp_table {
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ opp-microvolt-L0 = <1150000>;
+ opp-microvolt-L1 = <1100000>;
+ };
+
+};