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build/patch/kernel/archive/rk322x-5.10/01-linux-1002-v4l-wip.patch

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From 322d662f2a0a2b807da3978eedc234b93dbf53c2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 10:18:16 +0000
Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding
finish
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 1013d1aba59a..f3d788f90fed 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1090,7 +1090,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
state = (status & RKVDEC_RDY_STA) ?
VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
- writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
if (cancel_delayed_work(&rkvdec->watchdog_work)) {
struct rkvdec_ctx *ctx;
@@ -1111,7 +1112,8 @@ static void rkvdec_watchdog_func(struct work_struct *work)
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
if (ctx) {
dev_err(rkvdec->dev, "Frame processing timed out!\n");
- writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR);
}
From 819ed8a7ae45790f45ee62a769d7f50092b7d2e4 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 10:16:01 +0000
Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before
disable and cleanup
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index f3d788f90fed..e1eec79fe9a2 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1211,9 +1211,9 @@ static int rkvdec_remove(struct platform_device *pdev)
{
struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev);
- rkvdec_v4l2_cleanup(rkvdec);
- pm_runtime_disable(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ rkvdec_v4l2_cleanup(rkvdec);
return 0;
}
From f2a417e4106f6a07116d74a99194c89cfa8858f1 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 11:23:04 +0000
Subject: [PATCH] WIP: media: rkvdec: h264: return early when no reference
pictures
NOTE: also change from a switch statement to access reflists from a pointer array,
should simplify once we add support for field reference list
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index c115cd362a7f..d9a2fd9386e2 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -734,6 +734,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
const struct v4l2_ctrl_h264_sps *sps = run->sps;
struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
u32 max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4);
+ u8 *reflists[3] = { h264_ctx->reflists.p, h264_ctx->reflists.b0, h264_ctx->reflists.b1 };
u32 *hw_rps = priv_tbl->rps;
u32 i, j;
@@ -741,6 +742,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
memset(hw_rps, 0, sizeof(priv_tbl->rps));
+ if (!h264_ctx->reflists.num_valid)
+ return;
+
/*
* Assign an invalid pic_num if DPB entry at that position is inactive.
* If we assign 0 in that position hardware will treat that as a real
@@ -763,19 +767,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
u8 dpb_valid = 0;
- u8 idx = 0;
-
- switch (j) {
- case 0:
- idx = h264_ctx->reflists.p[i];
- break;
- case 1:
- idx = h264_ctx->reflists.b0[i];
- break;
- case 2:
- idx = h264_ctx->reflists.b1[i];
- break;
- }
+ u8 idx = reflists[j][i];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
From 918eabd2461d3394689c85d0b0df3711392eb699 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 14:42:27 +0000
Subject: [PATCH] WIP: media: rkvdec: h264: add field decoding support
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 79 ++++++++++++++++++----
1 file changed, 64 insertions(+), 15 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index d9a2fd9386e2..d4f27ef7addd 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -737,7 +737,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 *reflists[3] = { h264_ctx->reflists.p, h264_ctx->reflists.b0, h264_ctx->reflists.b1 };
u32 *hw_rps = priv_tbl->rps;
- u32 i, j;
+ u32 i, j, k;
u16 *p = (u16 *)hw_rps;
memset(hw_rps, 0, sizeof(priv_tbl->rps));
@@ -764,18 +764,71 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
p[i] = dpb[i].frame_num - max_frame_num;
}
- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
- u8 dpb_valid = 0;
- u8 idx = reflists[j][i];
+ if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) {
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ for (i = 0; i < h264_ctx->reflists.num_valid; i++) {
+ u8 dpb_valid = 0;
+ u8 idx = reflists[j][i];
- if (idx >= ARRAY_SIZE(dec_params->dpb))
- continue;
- dpb_valid = !!(dpb[idx].flags &
- V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ dpb_valid = !!(dpb[idx].flags &
+ V4L2_H264_DPB_ENTRY_FLAG_ACTIVE);
- set_ps_field(hw_rps, DPB_INFO(i, j),
- idx | dpb_valid << 4);
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | dpb_valid << 4);
+ }
+ }
+ return;
+ }
+
+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
+ enum v4l2_h264_field_reference a_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
+ enum v4l2_h264_field_reference b_parity =
+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
+ ? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
+ u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
+ i = 0;
+
+ for (k = 0; k < 2; k++) {
+ u8 a = 0;
+ u8 b = 0;
+ u32 long_term = k ? V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM : 0;
+
+ while (a < h264_ctx->reflists.num_valid || b < h264_ctx->reflists.num_valid) {
+ for (; a < h264_ctx->reflists.num_valid; a++) {
+ u8 idx = reflists[j][a];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & a_parity) == a_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ a_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ a++;
+ break;
+ }
+ }
+ for (; b < h264_ctx->reflists.num_valid; b++) {
+ u8 idx = reflists[j][b];
+ if (idx >= ARRAY_SIZE(dec_params->dpb))
+ continue;
+ if ((dpb[idx].reference & b_parity) == b_parity &&
+ (dpb[idx].flags & flags) == long_term) {
+ set_ps_field(hw_rps, DPB_INFO(i, j),
+ idx | (1 << 4));
+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j),
+ b_parity == V4L2_H264_BOTTOM_FIELD_REF);
+ i++;
+ b++;
+ break;
+ }
+ }
+ }
}
}
}
@@ -968,10 +1021,6 @@ static void config_registers(struct rkvdec_ctx *ctx,
rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15);
}
- /*
- * Since support frame mode only
- * top_field_order_cnt is the same as bottom_field_order_cnt
- */
reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt);
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
From 7b7488414b5d1c23b39bb9b9de376e28c287661d Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Sat, 26 Oct 2019 13:55:15 +0200
Subject: [PATCH] media: uapi: hevc: Add scaling matrix control
HEVC has a scaling matrix concept. Add support for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../media/v4l/ext-ctrls-codec.rst | 41 +++++++++++++++++++
.../media/v4l/pixfmt-compressed.rst | 1 +
drivers/media/v4l2-core/v4l2-ctrls.c | 10 +++++
include/media/hevc-ctrls.h | 11 +++++
4 files changed, 63 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
index 456488f2b5ca..81529b1d8d69 100644
--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
@@ -4866,6 +4866,47 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
- ``padding[6]``
- Applications and drivers must set this to zero.
+``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)``
+ Specifies the scaling matrix (as extracted from the bitstream) for
+ the associated HEVC slice data. The bitstream parameters are
+ defined according to :ref:`hevc`, section 7.4.5 "Scaling list
+ data semantics". For further documentation, refer to the above
+ specification, unless there is an explicit comment stating
+ otherwise.
+
+ .. note::
+
+ This compound control is not yet part of the public kernel API and
+ it is expected to change.
+
+.. c:type:: v4l2_ctrl_hevc_scaling_matrix
+
+.. cssclass:: longtable
+
+.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix
+ :header-rows: 0
+ :stub-columns: 0
+ :widths: 1 1 2
+
+ * - __u8
+ - ``scaling_list_4x4[6][16]``
+ -
+ * - __u8
+ - ``scaling_list_8x8[6][64]``
+ -
+ * - __u8
+ - ``scaling_list_16x16[6][64]``
+ -
+ * - __u8
+ - ``scaling_list_32x32[2][64]``
+ -
+ * - __u8
+ - ``scaling_list_dc_coef_16x16[6]``
+ -
+ * - __u8
+ - ``scaling_list_dc_coef_32x32[2]``
+ -
+
``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)``
Specifies the decoding mode to use. Currently exposes slice-based and
frame-based decoding but new modes might be added later on.
diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst
index d585909bc4e2..f817c643761b 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst
@@ -200,6 +200,7 @@ Compressed Formats
* ``V4L2_CID_MPEG_VIDEO_HEVC_SPS``
* ``V4L2_CID_MPEG_VIDEO_HEVC_PPS``
* ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``
+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX``
See the :ref:`associated Codec Control IDs <v4l2-mpeg-hevc>`.
Buffers associated with this pixel format must contain the appropriate
number of macroblocks to decode a full corresponding frame.
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index a88e962ac8a1..4267ba536013 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -1026,6 +1026,7 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set";
case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set";
case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters";
+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix";
case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode";
case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code";
@@ -1475,6 +1476,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS:
*type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS;
break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX:
+ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX;
+ break;
case V4L2_CID_UNIT_CELL_SIZE:
*type = V4L2_CTRL_TYPE_AREA;
*flags |= V4L2_CTRL_FLAG_READ_ONLY;
@@ -2167,6 +2171,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
zero_padding(*p_hevc_slice_params);
break;
+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:
+ break;
+
case V4L2_CTRL_TYPE_AREA:
area = p;
if (!area->width || !area->height)
@@ -2865,6 +2872,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params);
break;
+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:
+ elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix);
+ break;
case V4L2_CTRL_TYPE_AREA:
elem_size = sizeof(struct v4l2_area);
break;
diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
index 1009cf0891cc..1592e52c3614 100644
--- a/include/media/hevc-ctrls.h
+++ b/include/media/hevc-ctrls.h
@@ -19,6 +19,7 @@
#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008)
#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009)
#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010)
+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011)
#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015)
#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016)
@@ -26,6 +27,7 @@
#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123
enum v4l2_mpeg_video_hevc_decode_mode {
V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
@@ -209,4 +211,13 @@ struct v4l2_ctrl_hevc_slice_params {
__u64 flags;
};
+struct v4l2_ctrl_hevc_scaling_matrix {
+ __u8 scaling_list_4x4[6][16];
+ __u8 scaling_list_8x8[6][64];
+ __u8 scaling_list_16x16[6][64];
+ __u8 scaling_list_32x32[2][64];
+ __u8 scaling_list_dc_coef_16x16[6];
+ __u8 scaling_list_dc_coef_32x32[2];
+};
+
#endif
From 39fccad1853d319b5d6de0352b6106f5a2f9e7eb Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Sat, 26 Oct 2019 15:42:28 +0200
Subject: [PATCH] media: uapi: hevc: Add segment address field
If HEVC frame consists of multiple slices, segment address has to be
known in order to properly decode it.
Add segment address field to slice parameters.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 5 ++++-
include/media/hevc-ctrls.h | 5 ++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
index 81529b1d8d69..817773791888 100644
--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
@@ -4661,6 +4661,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
* - __u32
- ``data_bit_offset``
- Offset (in bits) to the video data in the current slice data.
+ * - __u32
+ - ``slice_segment_addr``
+ -
* - __u8
- ``nal_unit_type``
-
@@ -4738,7 +4741,7 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
- ``num_rps_poc_lt_curr``
- The number of reference pictures in the long-term set.
* - __u8
- - ``padding[7]``
+ - ``padding[5]``
- Applications and drivers must set this to zero.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
index 1592e52c3614..3e2e32098312 100644
--- a/include/media/hevc-ctrls.h
+++ b/include/media/hevc-ctrls.h
@@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params {
__u32 bit_size;
__u32 data_bit_offset;
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
+ __u32 slice_segment_addr;
+
/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
__u8 nal_unit_type;
__u8 nuh_temporal_id_plus1;
@@ -200,7 +203,7 @@ struct v4l2_ctrl_hevc_slice_params {
__u8 num_rps_poc_st_curr_after;
__u8 num_rps_poc_lt_curr;
- __u8 padding;
+ __u8 padding[5];
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
From 393a4406b1b88ebb97b04586f27b0334136aede1 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 15:03:46 +0000
Subject: [PATCH] WIP: media: uapi: hevc: add fields needed for rkvdec
NOTE: these fields are used by rkvdec hevc backend
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
include/media/hevc-ctrls.h | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
index 3e2e32098312..3cc3b47e1417 100644
--- a/include/media/hevc-ctrls.h
+++ b/include/media/hevc-ctrls.h
@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code {
/* The controls are not stable at the moment and will likely be reworked. */
struct v4l2_ctrl_hevc_sps {
/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
+ __u8 video_parameter_set_id;
+ __u8 seq_parameter_set_id;
+ __u8 chroma_format_idc;
__u16 pic_width_in_luma_samples;
__u16 pic_height_in_luma_samples;
__u8 bit_depth_luma_minus8;
@@ -76,9 +79,8 @@ struct v4l2_ctrl_hevc_sps {
__u8 log2_diff_max_min_pcm_luma_coding_block_size;
__u8 num_short_term_ref_pic_sets;
__u8 num_long_term_ref_pics_sps;
- __u8 chroma_format_idc;
- __u8 padding;
+ __u8 padding[7];
__u64 flags;
};
@@ -105,7 +107,10 @@ struct v4l2_ctrl_hevc_sps {
struct v4l2_ctrl_hevc_pps {
/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
+ __u8 pic_parameter_set_id;
__u8 num_extra_slice_header_bits;
+ __u8 num_ref_idx_l0_default_active_minus1;
+ __u8 num_ref_idx_l1_default_active_minus1;
__s8 init_qp_minus26;
__u8 diff_cu_qp_delta_depth;
__s8 pps_cb_qp_offset;
@@ -118,7 +123,7 @@ struct v4l2_ctrl_hevc_pps {
__s8 pps_tc_offset_div2;
__u8 log2_parallel_merge_level_minus2;
- __u8 padding[4];
+ __u8 padding;
__u64 flags;
};
@@ -203,7 +208,10 @@ struct v4l2_ctrl_hevc_slice_params {
__u8 num_rps_poc_st_curr_after;
__u8 num_rps_poc_lt_curr;
- __u8 padding[5];
+ __u16 short_term_ref_pic_set_size;
+ __u16 long_term_ref_pic_set_size;
+
+ __u8 padding;
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
From 6b50e1d090acfd964a80c3821d4cac909b38693c Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 15:07:15 +0000
Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices
---
include/media/hevc-ctrls.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
index 3cc3b47e1417..b33e1a8141e1 100644
--- a/include/media/hevc-ctrls.h
+++ b/include/media/hevc-ctrls.h
@@ -80,7 +80,8 @@ struct v4l2_ctrl_hevc_sps {
__u8 num_short_term_ref_pic_sets;
__u8 num_long_term_ref_pics_sps;
- __u8 padding[7];
+ __u8 num_slices;
+ __u8 padding[6];
__u64 flags;
};
@@ -174,6 +175,7 @@ struct v4l2_ctrl_hevc_slice_params {
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
__u32 slice_segment_addr;
+ __u32 num_entry_point_offsets;
/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
__u8 nal_unit_type;
@@ -211,7 +213,9 @@ struct v4l2_ctrl_hevc_slice_params {
__u16 short_term_ref_pic_set_size;
__u16 long_term_ref_pic_set_size;
- __u8 padding;
+ __u8 padding[5];
+
+ __u32 entry_point_offset_minus1[256];
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
From b34391e007c6f8bd42396d954d270457a50ac84c Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 23 May 2020 15:17:45 +0000
Subject: [PATCH] WIP: media: rkvdec: add HEVC backend
NOTE: cabac table and scailing list code is copied 1:1 from mpp
TODO: fix lowdelay flag and rework the scaling list part
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 70 +
drivers/staging/media/rkvdec/rkvdec.h | 1 +
5 files changed, 2595 insertions(+), 1 deletion(-)
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
index cb86b429cfaa..a77122641d14 100644
--- a/drivers/staging/media/rkvdec/Makefile
+++ b/drivers/staging/media/rkvdec/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
new file mode 100644
index 000000000000..03ba848411c6
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -0,0 +1,2522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Boris Brezillon <boris.brezillon@collabora.com>
+ *
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
+ * Jeffy Chen <jeffy.chen@rock-chips.com>
+ */
+
+#include <media/v4l2-mem2mem.h>
+
+#include "rkvdec.h"
+#include "rkvdec-regs.h"
+
+/* Size in u8/u32 units. */
+#define RKV_CABAC_TABLE_SIZE 27456
+#define RKV_SCALING_LIST_SIZE 1360
+#define RKV_PPS_SIZE (80 / 4)
+#define RKV_PPS_LEN 64
+#define RKV_RPS_SIZE (32 / 4)
+#define RKV_RPS_LEN 600
+
+struct rkvdec_sps_pps_packet {
+ u32 info[RKV_PPS_SIZE];
+};
+
+struct rkvdec_rps_packet {
+ u32 info[RKV_RPS_SIZE];
+};
+
+struct rkvdec_ps_field {
+ u16 offset;
+ u8 len;
+};
+
+#define PS_FIELD(_offset, _len) \
+ ((struct rkvdec_ps_field){ _offset, _len })
+
+/* SPS */
+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
+/* PPS */
+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
+#define NUM_TILE_ROWS PS_FIELD(217, 5)
+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8)
+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8)
+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
+
+/* Data structure describing auxiliary buffer format. */
+struct rkvdec_hevc_priv_tbl {
+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
+};
+
+struct rkvdec_hevc_run {
+ struct rkvdec_run base;
+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
+ int num_slices;
+};
+
+struct rkvdec_hevc_ctx {
+ struct rkvdec_aux_buf priv_tbl;
+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
+};
+
+// TODO: refactor scaling list code, was copied 1:1 from mpp
+
+typedef struct ScalingList {
+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
+ * and size ID 3 only has 2 arrays, not 6. */
+ u8 sl[4][6][64];
+ u8 sl_dc[2][6];
+} scalingList_t;
+
+typedef struct ScalingFactor_Model {
+ u8 scalingfactor0[1248];
+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
+ u8 reserverd[4]; /*16Bytes align*/
+} scalingFactor_t;
+
+#define SCALING_LIST_SIZE_NUM 4
+
+static void
+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out,
+ scalingList_t *pScalingList)
+{
+ int i;
+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model
+ u32 nIndex = 0;
+ u32 sizeId, matrixId, listId;
+ u8 *p = pScalingFactor_out->scalingfactor0;
+ u8 tmpBuf[8 * 8];
+
+ //output non-default scalingFactor Table (1248 BYTES)
+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) {
+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) {
+ if (sizeId < 3) {
+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
+ }
+ } else {
+ for (i = 0; i < 64; i ++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
+ }
+ for (i = 0; i < 128; i ++) {
+ pScalingFactor_out->scalingfactor0[nIndex++] = 0;
+ }
+ }
+ }
+ }
+ //output non-default scalingFactor Table Rotation(96 Bytes)
+ nIndex = 0;
+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) {
+ u8 temp16[16] = {0};
+ for (i = 0; i < 16; i ++) {
+ temp16[i] = (u8)pScalingList->sl[0][listId][i];
+ }
+ for (i = 0; i < 4; i ++) {
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8];
+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12];
+ }
+ }
+ //output non-default ScalingList_DC_Coeff (12 BYTES)
+ nIndex = 0;
+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2
+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
+ }
+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3
+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
+ pScalingFactor_out->scalingdc[nIndex++] = 0;
+ pScalingFactor_out->scalingdc[nIndex++] = 0;
+ }
+
+ //align 16X address
+ nIndex = 0;
+ for (i = 0; i < 4; i ++) {
+ pScalingFactor_out->reserverd[nIndex++] = 0;
+ }
+
+ //----------------------All above code show the normal store way in HM--------------------------
+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90'
+
+ //sizeId == 0
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16;
+
+ for (i = 0; i < 4; i++) {
+ tmpBuf[4 * 0 + i] = p[i * 4 + 0];
+ tmpBuf[4 * 1 + i] = p[i * 4 + 1];
+ tmpBuf[4 * 2 + i] = p[i * 4 + 2];
+ tmpBuf[4 * 3 + i] = p[i * 4 + 3];
+ }
+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
+ }
+ //sizeId == 1
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+ //sizeId == 2
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+ //sizeId == 3
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64;
+
+ for (i = 0; i < 8; i++) {
+ tmpBuf[8 * 0 + i] = p[i * 8 + 0];
+ tmpBuf[8 * 1 + i] = p[i * 8 + 1];
+ tmpBuf[8 * 2 + i] = p[i * 8 + 2];
+ tmpBuf[8 * 3 + i] = p[i * 8 + 3];
+ tmpBuf[8 * 4 + i] = p[i * 8 + 4];
+ tmpBuf[8 * 5 + i] = p[i * 8 + 5];
+ tmpBuf[8 * 6 + i] = p[i * 8 + 6];
+ tmpBuf[8 * 7 + i] = p[i * 8 + 7];
+ }
+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
+ }
+
+ //sizeId == 0
+ for (matrixId = 0; matrixId < 6; matrixId++) {
+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16;
+
+ for (i = 0; i < 4; i++) {
+ tmpBuf[4 * 0 + i] = p[i * 4 + 0];
+ tmpBuf[4 * 1 + i] = p[i * 4 + 1];
+ tmpBuf[4 * 2 + i] = p[i * 4 + 2];
+ tmpBuf[4 * 3 + i] = p[i * 4 + 3];
+ }
+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
+ }
+}
+
+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68,
+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68,
+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58,
+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60,
+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68,
+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58,
+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50,
+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40,
+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f,
+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66,
+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67,
+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57,
+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66,
+ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57,
+ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f,
+ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40,
+ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f,
+ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64,
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+ 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
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+ 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
+ 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c,
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+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
+ 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40,
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+ 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d,
+ 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d,
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+ 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e,
+ 0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
+ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07,
+ 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e,
+ 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e,
+ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26,
+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
+ 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
+ 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
+ 0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07,
+ 0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f,
+ 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f,
+ 0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
+ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+{
+ u8 bit = field.offset % 32, word = field.offset / 32;
+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
+ u64 val = ((u64)value << bit) & mask;
+
+ buf[word] &= ~mask;
+ buf[word] |= val;
+ if (bit + field.len > 32) {
+ buf[word + 1] &= ~(mask >> 32);
+ buf[word + 1] |= val >> 32;
+ }
+}
+
+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_sps_pps_packet *hw_ps;
+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
+ u32 log2_min_cu_qp_delta_size;
+ dma_addr_t scaling_list_address;
+ u32 scaling_distance;
+ int i;
+
+ /*
+ * HW read the SPS/PPS information from PPS packet index by PPS id.
+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
+ * packet unit for HW accessing.
+ */
+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
+ ctb_log2_size_y = min_cb_log2_size_y +
+ sps->log2_diff_max_min_luma_coding_block_size;
+ ctb_size_y = 1 << ctb_log2_size_y;
+
+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ /* write sps */
+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(1, CHROMA_FORMAT_IDC);
+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
+ LOG2_MAX_PIC_ORDER_CNT_LSB);
+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
+ SCALING_LIST_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
+ AMP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
+ WRITE_PPS(1, PCM_ENABLED_FLAG);
+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
+ PCM_LOOP_FILTER_DISABLED_FLAG);
+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ }
+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
+ LONG_TERM_REF_PICS_PRESENT_FLAG);
+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
+ //WRITE_PPS(0, PS_FIELD(100, 7));
+ //WRITE_PPS(0x1fffff, PS_FIELD(107, 21));
+
+ /* write pps */
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
+ OUTPUT_FLAG_PRESENT_FLAG);
+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
+ SIGN_DATA_HIDING_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
+ CABAC_INIT_PRESENT_FLAG);
+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
+ CONSTRAINED_INTRA_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
+ TRANSFORM_SKIP_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
+ CU_QP_DELTA_ENABLED_FLAG);
+
+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
+
+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
+ WEIGHTED_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
+ WEIGHTED_BIPRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
+ TRANSQUANT_BYPASS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
+ TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
+ LISTS_MODIFICATION_PRESENT_FLAG);
+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
+ //WRITE_PPS(0, PS_FIELD(209, 3));
+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
+ //WRITE_PPS(0x2, PS_FIELD(222, 2));
+ //WRITE_PPS(0xffffffff, PS_FIELD(224, 32));
+
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
+ } else {
+ WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1,
+ COLUMN_WIDTH(0));
+ WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1,
+ ROW_HEIGHT(0));
+ }
+
+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
+ //WRITE_PPS(0xffff, PS_FIELD(624, 16));
+}
+
+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ const struct v4l2_hevc_dpb_entry *dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_rps_packet *hw_ps;
+ int i, j;
+
+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
+
+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1)
+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4)
+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1)
+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
+
+#define LOWDELAY PS_FIELD(182, 1)
+#define SHORT_TERM_REF_PIC_SET_SIZE PS_FIELD(183, 10)
+#define LONG_TERM_REF_PIC_SET_SIZE PS_FIELD(193, 9)
+#define NUM_RPS_POC PS_FIELD(202, 4)
+
+ for (j = 0; j < run->num_slices; j++) {
+ sl_params = &run->slices_params[j];
+ dpb = sl_params->dpb;
+
+ hw_ps = &priv_tbl->rps[j];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
+ REF_PIC_LONG_TERM_L0(i));
+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+ }
+
+ for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
+ REF_PIC_LONG_TERM_L1(i));
+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
+ }
+
+ //WRITE_RPS(0xffffffff, PS_FIELD(96, 32));
+
+ // TODO: lowdelay
+ WRITE_RPS(0, LOWDELAY);
+
+ // NOTE: these two differs from mpp
+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ SHORT_TERM_REF_PIC_SET_SIZE);
+ WRITE_RPS(sl_params->long_term_ref_pic_set_size,
+ LONG_TERM_REF_PIC_SET_SIZE);
+
+ WRITE_RPS(sl_params->num_rps_poc_st_curr_before +
+ sl_params->num_rps_poc_st_curr_after +
+ sl_params->num_rps_poc_lt_curr,
+ NUM_RPS_POC);
+
+ //WRITE_RPS(0x3ffff, PS_FIELD(206, 18));
+ //WRITE_RPS(0xffffffff, PS_FIELD(224, 32));
+ }
+}
+
+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
+ u8 *dst;
+ scalingList_t sl;
+ int i, j;
+
+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
+ return;
+
+ memset(&sl, 0, sizeof(scalingList_t));
+
+ for (i = 0; i < 6; i++) {
+ for (j = 0; j < 16; j++)
+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j];
+ for (j = 0; j < 64; j++) {
+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j];
+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j];
+ if (i < 2)
+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j];
+ }
+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i];
+ if (i < 2)
+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i];
+ }
+
+ dst = tbl->scaling_list;
+ hal_record_scaling_list((scalingFactor_t *)dst, &sl);
+
+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
+}
+
+static struct vb2_buffer *
+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
+ unsigned int dpb_idx)
+{
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
+ int buf_idx = -1;
+
+ if (dpb_idx < sl_params->num_active_dpb_entries)
+ buf_idx = vb2_find_timestamp(cap_q,
+ dpb[dpb_idx].timestamp, 0);
+
+ /*
+ * If a DPB entry is unused or invalid, address of current destination
+ * buffer is returned.
+ */
+ if (buf_idx < 0)
+ return &run->base.bufs.dst->vb2_buf;
+
+ return vb2_get_buffer(cap_q, buf_idx);
+}
+
+static void config_registers(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
+ const struct v4l2_pix_format_mplane *dst_fmt;
+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
+ const struct v4l2_format *f;
+ dma_addr_t rlc_addr;
+ dma_addr_t refer_addr;
+ u32 rlc_len;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
+ u32 uv_virstride;
+ u32 yuv_virstride;
+ u32 offset;
+ dma_addr_t dst_addr;
+ u32 reg, i;
+
+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+
+ f = &ctx->decoded_fmt;
+ dst_fmt = &f->fmt.pix_mp;
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
+ y_virstride = hor_virstride * ver_virstride;
+ uv_virstride = y_virstride / 2;
+ yuv_virstride = y_virstride + uv_virstride;
+
+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
+
+ /* config rlc base address */
+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
+
+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
+
+ /* config cabac table */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
+
+ /* config output base address */
+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
+
+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
+
+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
+
+ /* config ref pic address */
+ for (i = 0; i < 15; i++) {
+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
+
+ if (i < 4 && sl_params->num_active_dpb_entries) {
+ reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0);
+ reg = (reg >> (i * 4)) & 0xf;
+ } else
+ reg = 0;
+
+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
+ writel_relaxed(refer_addr | reg,
+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
+
+ reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0);
+ writel_relaxed(reg,
+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
+ }
+
+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
+
+ /* config hw pps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_PPS_BASE);
+
+ /* config hw rps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_RPS_BASE);
+
+ reg = RKVDEC_AXI_DDR_RDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
+
+ reg = RKVDEC_AXI_DDR_WDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
+}
+
+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
+
+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
+
+ fmt->num_planes = 1;
+ if (!fmt->plane_fmt[0].sizeimage)
+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
+ return 0;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_priv_tbl *priv_tbl;
+ struct rkvdec_hevc_ctx *hevc_ctx;
+ int ret;
+
+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
+ if (!hevc_ctx)
+ return -ENOMEM;
+
+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
+ if (!priv_tbl) {
+ ret = -ENOMEM;
+ goto err_free_ctx;
+ }
+
+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
+ hevc_ctx->priv_tbl.cpu = priv_tbl;
+ memset(priv_tbl, 0, sizeof(*priv_tbl));
+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
+ sizeof(rkvdec_hevc_cabac_table));
+
+ ctx->priv = hevc_ctx;
+ return 0;
+
+err_free_ctx:
+ kfree(hevc_ctx);
+ return ret;
+}
+
+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_dev *rkvdec = ctx->dev;
+
+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
+ kfree(hevc_ctx);
+}
+
+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_MPEG_VIDEO_HEVC_SPS);
+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_MPEG_VIDEO_HEVC_PPS);
+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX);
+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
+
+ rkvdec_run_preamble(ctx, &run->base);
+
+ // HACK: we need num slices from somewhere
+ run->num_slices = run->sps->num_slices;
+}
+
+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_run run;
+
+ rkvdec_hevc_run_preamble(ctx, &run);
+
+ assemble_hw_scaling_list(ctx, &run);
+ assemble_hw_pps(ctx, &run);
+ assemble_hw_rps(ctx, &run);
+ config_registers(ctx, &run);
+
+ rkvdec_run_postamble(ctx, &run.base);
+
+ // sw_cabac_error_e - cabac error enable
+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+ // slice end error enable = BIT(28)
+ // frame end error enable = BIT(29)
+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
+
+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
+
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+
+ /* Start decoding! */
+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+
+ return 0;
+}
+
+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .start = rkvdec_hevc_start,
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 15b9bee92016..83bf790ed9b7 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -43,6 +43,7 @@
#define RKVDEC_RLC_MODE BIT(11)
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
+#define RKVDEC_MODE_HEVC 0
#define RKVDEC_MODE_H264 1
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index e1eec79fe9a2..880a70c9291e 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -159,6 +159,61 @@ static const u32 rkvdec_h264_decoded_fmts[] = {
V4L2_PIX_FMT_NV20,
};
+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
+ {
+ .mandatory = true,
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,
+ // HACK: match ffmpeg v4l2 request api hwaccel size,
+ // we should support variable length up to 600 slices
+ .cfg.dims = { 16 },
+ },
+ {
+ .mandatory = true,
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
+ },
+ {
+ .mandatory = true,
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
+ },
+ {
+ .mandatory = true,
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+};
+
+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
+ .ctrls = rkvdec_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
+};
+
+static const u32 rkvdec_hevc_decoded_fmts[] = {
+ V4L2_PIX_FMT_NV12,
+ V4L2_PIX_FMT_NV15,
+};
+
static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
{
.mandatory = true,
@@ -209,6 +264,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
.decoded_fmts = rkvdec_h264_decoded_fmts,
},
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ },
{
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
.frmsize = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 5f66f07acac5..d5600c6a4c17 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -123,6 +123,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
#endif /* RKVDEC_H_ */
From a9609c4fd9f76a35c3f84e32002a26ff857940f8 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 1 Aug 2020 12:24:58 +0000
Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 11 +++++++++++
drivers/staging/media/rkvdec/rkvdec.c | 23 +++++++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 03ba848411c6..b8ad7fc2271c 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -2415,6 +2415,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
return 0;
}
+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (sps->bit_depth_luma_minus8 == 2)
+ return V4L2_PIX_FMT_NV15;
+ else
+ return V4L2_PIX_FMT_NV12;
+}
+
static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
{
struct rkvdec_dev *rkvdec = ctx->dev;
@@ -2516,6 +2526,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
.adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .valid_fmt = rkvdec_hevc_valid_fmt,
.start = rkvdec_hevc_start,
.stop = rkvdec_hevc_stop,
.run = rkvdec_hevc_run,
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 880a70c9291e..5eec0ed710b2 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -76,6 +76,26 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
if (width > ctx->coded_fmt.fmt.pix_mp.width ||
height > ctx->coded_fmt.fmt.pix_mp.height)
return -EINVAL;
+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (sps->chroma_format_idc > 1)
+ /* Only 4:0:0 and 4:2:0 are supported */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ /* Luma and chroma bit depth mismatch */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
+ return -EINVAL;
+
+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
+ /* Only current valid format */
+ return -EINVAL;
+
+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
+ return -EINVAL;
}
return 0;
}
@@ -84,7 +104,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
- if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS && !ctx->valid_fmt) {
+ if (!ctx->valid_fmt) {
ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
if (ctx->valid_fmt) {
struct v4l2_pix_format_mplane *pix_mp;
@@ -170,6 +190,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
{
.mandatory = true,
.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
},
{
.mandatory = true,
From b0827a52d53f0f561e658eb77ed446738d5e12ea Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 29 Oct 2019 01:26:02 +0000
Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded
content
This still need code cleanup and formatting
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../staging/media/hantro/hantro_g1_h264_dec.c | 17 +---
drivers/staging/media/hantro/hantro_h264.c | 81 ++++++++++++++++---
drivers/staging/media/hantro/hantro_hw.h | 2 +
3 files changed, 74 insertions(+), 26 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
index 845bef73d218..869ee261a5db 100644
--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
@@ -130,25 +130,12 @@ static void set_ref(struct hantro_ctx *ctx)
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
const u8 *b0_reflist, *b1_reflist, *p_reflist;
struct hantro_dev *vpu = ctx->dev;
- u32 dpb_longterm = 0;
- u32 dpb_valid = 0;
int reg_num;
u32 reg;
int i;
- /*
- * Set up bit maps of valid and long term DPBs.
- * NOTE: The bits are reversed, i.e. MSb is DPB 0.
- */
- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
-
- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
- }
- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
/*
* Set up reference frame picture numbers.
diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
index b1bdc00ac262..bc2af450a94c 100644
--- a/drivers/staging/media/hantro/hantro_h264.c
+++ b/drivers/staging/media/hantro/hantro_h264.c
@@ -227,17 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx)
{
const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
+ const struct v4l2_ctrl_h264_sps *sps = ctrls->sps;
struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ u32 dpb_longterm = 0;
+ u32 dpb_valid = 0;
int i;
+ /*
+ * Set up bit maps of valid and long term DPBs.
+ * NOTE: The bits are reversed, i.e. MSb is DPB 0.
+ */
+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
+ for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
+ // check for correct reference use
+ enum v4l2_h264_field_reference parity = (i & 0x1) ?
+ V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE &&
+ dpb[i / 2].reference & parity)
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
+
+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
+ }
+
+ ctx->h264_dec.dpb_valid = dpb_valid;
+ ctx->h264_dec.dpb_longterm = dpb_longterm;
+ } else {
+ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+ }
+
+ ctx->h264_dec.dpb_valid = dpb_valid << 16;
+ ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
+ }
+
for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
- tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
+ tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
+ tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
+ } else {
+ tbl->poc[i * 2] = 0;
+ tbl->poc[i * 2 + 1] = 0;
+ }
}
- tbl->poc[32] = dec_param->top_field_order_cnt;
- tbl->poc[33] = dec_param->bottom_field_order_cnt;
+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC))
+ tbl->poc[32] = (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ?
+ dec_param->bottom_field_order_cnt :
+ dec_param->top_field_order_cnt;
+ else
+ tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
+ tbl->poc[33] = 0;
+ } else {
+ tbl->poc[32] = dec_param->top_field_order_cnt;
+ tbl->poc[33] = dec_param->bottom_field_order_cnt;
+ }
assemble_scaling_list(ctx);
}
@@ -245,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx)
static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
const struct v4l2_h264_dpb_entry *b)
{
- return a->top_field_order_cnt == b->top_field_order_cnt &&
- a->bottom_field_order_cnt == b->bottom_field_order_cnt;
+ return a->reference_ts == b->reference_ts;
}
static void update_dpb(struct hantro_ctx *ctx)
@@ -260,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx)
/* Disable all entries by default. */
for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
- ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
+ ctx->h264_dec.dpb[i].flags = 0;
/* Try to match new DPB entries with existing ones by their POCs. */
for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
- if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
+ if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
continue;
/*
@@ -277,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx)
struct v4l2_h264_dpb_entry *cdpb;
cdpb = &ctx->h264_dec.dpb[j];
- if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
- !dpb_entry_match(cdpb, ndpb))
+ if (!dpb_entry_match(cdpb, ndpb))
continue;
*cdpb = *ndpb;
@@ -314,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
unsigned int dpb_idx)
{
struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
dma_addr_t dma_addr = 0;
+ s32 cur_poc;
+ u32 flags;
if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
@@ -332,7 +383,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
dma_addr = hantro_get_dec_buf_addr(ctx, buf);
}
- return dma_addr;
+ cur_poc = dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD ?
+ dec_param->bottom_field_order_cnt :
+ dec_param->top_field_order_cnt;
+ flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD ? 0x2 : 0;
+ flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
+ abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
+ 0x1 : 0;
+
+ return dma_addr | flags;
}
int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 219283a06f52..7e35140a4f22 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -90,6 +90,8 @@ struct hantro_h264_dec_hw_ctx {
struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
struct hantro_h264_dec_reflists reflists;
struct hantro_h264_dec_ctrls ctrls;
+ u32 dpb_longterm;
+ u32 dpb_valid;
};
/**
From 9d86dd7c5559c7f2e1cf8f7bcab79720aeb09703 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 6 Jan 2019 01:48:37 +0800
Subject: [PATCH] soc: rockchip: power-domain: export idle request
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/soc/rockchip/pm_domains.c | 23 +++++++++++++++++++++++
include/linux/rockchip_pmu.h | 15 +++++++++++++++
include/soc/rockchip/pm_domains.h | 18 ++++++++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 include/linux/rockchip_pmu.h
create mode 100644 include/soc/rockchip/pm_domains.h
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index c6b33f7c43df..3688e9e67872 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -197,6 +197,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
return 0;
}
+int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int ret;
+
+ if (IS_ERR_OR_NULL(dev))
+ return -EINVAL;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return -EINVAL;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ pd = to_rockchip_pd(genpd);
+
+ mutex_lock(&pd->pmu->mutex);
+ ret = rockchip_pmu_set_idle_request(pd, idle);
+ mutex_unlock(&pd->pmu->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_pmu_idle_request);
+
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
int i;
diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
new file mode 100644
index 000000000000..720b3314e71a
--- /dev/null
+++ b/include/linux/rockchip_pmu.h
@@ -0,0 +1,15 @@
+/*
+ * pm_domain.h - Definitions and headers related to device power domains.
+ *
+ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#ifndef _LINUX_ROCKCHIP_PM_H
+#define _LINUX_ROCKCHIP_PM_H
+#include <linux/device.h>
+
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+
+#endif /* _LINUX_ROCKCHIP_PM_H */
diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h
new file mode 100644
index 000000000000..690db6118636
--- /dev/null
+++ b/include/soc/rockchip/pm_domains.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H
+#define __SOC_ROCKCHIP_PM_DOMAINS_H
+
+#include <linux/errno.h>
+
+struct device;
+
+#ifdef CONFIG_ROCKCHIP_PM_DOMAINS
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+#else
+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ return -ENOTSUPP;
+}
+#endif
+
+#endif
From e34147ff2737bf9ba728c42c7968f10574e127ca Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 20 May 2020 17:04:47 +0200
Subject: [PATCH] media: rkvdec: implement reset controls
---
.../bindings/media/rockchip,vdec.yaml | 19 ++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++
drivers/staging/media/rkvdec/rkvdec.c | 60 +++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec.h | 11 +++-
4 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
index 8d35c327018b..dfafdb671798 100644
--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
@@ -43,6 +43,18 @@ properties:
iommus:
maxItems: 1
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: video_h
+ - const: video_a
+ - const: video_core
+ - const: video_cabac
+ - const: niu_a
+ - const: niu_h
+
required:
- compatible
- reg
@@ -50,6 +62,8 @@ required:
- clocks
- clock-names
- power-domains
+ - resets
+ - reset-names
additionalProperties: false
@@ -68,6 +82,11 @@ examples:
clock-names = "axi", "ahb", "cabac", "core";
power-domains = <&power RK3399_PD_VDU>;
iommus = <&vdec_mmu>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
...
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 83bf790ed9b7..4addfaefdfb4 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -28,6 +28,11 @@
#define RKVDEC_SOFTRST_EN_P BIT(20)
#define RKVDEC_FORCE_SOFTRESET_VALID BIT(21)
#define RKVDEC_SOFTRESET_RDY BIT(22)
+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \
+ | RKVDEC_ERR_STA \
+ | RKVDEC_TIMEOUT_STA \
+ | RKVDEC_BUF_EMPTY_STA \
+ | RKVDEC_COLMV_REF_ERR_STA )
#define RKVDEC_REG_SYSCTRL 0x008
#define RKVDEC_IN_ENDIAN BIT(0)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 5eec0ed710b2..b736d7ad5558 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -10,12 +10,15 @@
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/rockchip_pmu.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
@@ -882,6 +885,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx,
pm_runtime_mark_last_busy(rkvdec->dev);
pm_runtime_put_autosuspend(rkvdec->dev);
+
+ if (result == VB2_BUF_STATE_ERROR &&
+ rkvdec->reset_mask == RESET_NONE)
+ rkvdec->reset_mask |= RESET_SOFT;
+
rkvdec_job_finish_no_pm(ctx, result);
}
@@ -919,6 +927,40 @@ static void rkvdec_device_run(void *priv)
if (WARN_ON(!desc))
return;
+ if (rkvdec->reset_mask != RESET_NONE) {
+
+ if (rkvdec->reset_mask & RESET_SOFT) {
+ writel(RKVDEC_SOFTRST_EN_P,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+ udelay(RKVDEC_RESET_DELAY);
+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT)
+ & RKVDEC_SOFTRESET_RDY)
+ dev_info_ratelimited(rkvdec->dev,
+ "softreset failed\n");
+ else
+ dev_notice_ratelimited(rkvdec->dev,
+ "softreset done\n");
+ }
+
+ if (rkvdec->reset_mask & RESET_HARD) {
+ pm_runtime_suspend(rkvdec->dev);
+ rockchip_pmu_idle_request(rkvdec->dev, true);
+ ret = reset_control_assert(rkvdec->rstc);
+ if (!ret) {
+ udelay(RKVDEC_RESET_DELAY);
+ ret = reset_control_deassert(rkvdec->rstc);
+ }
+ rockchip_pmu_idle_request(rkvdec->dev, false);
+ if (ret)
+ dev_notice_ratelimited(rkvdec->dev,
+ "hardreset failed\n");
+ else
+ dev_notice_ratelimited(rkvdec->dev,
+ "hardreset done\n");
+ }
+
+ rkvdec->reset_mask = RESET_NONE;
+ }
ret = pm_runtime_get_sync(rkvdec->dev);
if (ret < 0) {
@@ -1186,6 +1228,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv)
if (cancel_delayed_work(&rkvdec->watchdog_work)) {
struct rkvdec_ctx *ctx;
+ if (state == VB2_BUF_STATE_ERROR) {
+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ?
+ RESET_HARD : RESET_SOFT;
+ }
+
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
rkvdec_job_finish(ctx, state);
}
@@ -1203,6 +1250,7 @@ static void rkvdec_watchdog_func(struct work_struct *work)
ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev);
if (ctx) {
dev_err(rkvdec->dev, "Frame processing timed out!\n");
+ rkvdec->reset_mask |= RESET_HARD;
writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS,
rkvdec->regs + RKVDEC_REG_INTERRUPT);
writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL);
@@ -1282,6 +1330,18 @@ static int rkvdec_probe(struct platform_device *pdev)
return ret;
}
+
+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true);
+ if (IS_ERR(rkvdec->rstc)) {
+ dev_err(&pdev->dev,
+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc));
+ return PTR_ERR(rkvdec->rstc);
+ } else {
+ dev_dbg(&pdev->dev,
+ "requested %d resets\n",
+ reset_control_get_count(&pdev->dev));
+ }
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index d5600c6a4c17..975fe4b5dd68 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -11,10 +11,11 @@
#ifndef RKVDEC_H_
#define RKVDEC_H_
+#include <linux/clk.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/videodev2.h>
#include <linux/wait.h>
-#include <linux/clk.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
@@ -22,6 +23,12 @@
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
+#define RESET_NONE 0
+#define RESET_SOFT BIT(0)
+#define RESET_HARD BIT(1)
+
+#define RKVDEC_RESET_DELAY 5
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -95,6 +102,8 @@ struct rkvdec_dev {
void __iomem *regs;
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
+ struct reset_control *rstc;
+ u8 reset_mask;
};
struct rkvdec_ctx {
From 6261fb0dde9dfddc3cfed72c8445946993314ff6 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 18 Aug 2020 11:38:04 +0200
Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 3e44bf8eac5c..81b4b8714e3f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1284,6 +1284,11 @@ vdec: video-codec@ff660000 {
clock-names = "axi", "ahb", "cabac", "core";
iommus = <&vdec_mmu>;
power-domains = <&power RK3399_PD_VDU>;
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
};
vdec_mmu: iommu@ff660480 {
From c2a32797230aece341856e09b0139cf3d259e07b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Fri, 24 Apr 2020 12:36:13 +0200
Subject: [PATCH] media: hantro: add Rockchip RK3228
RK3228 has the same VPU IP-Block as RK3399 has and at the current state
the driver can be taken as is.
This adds just a new compatible string to bindings file if any future
ajustment for this SoC is necessary.
---
Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
index c81dbc3e8960..ddbda080950e 100644
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
+ - rockchip,rk3228-vpu
- rockchip,rk3288-vpu
- rockchip,rk3328-vpu
- rockchip,rk3399-vpu
From 86ac3c31aadac54e5c4a941ae25147b8e1045676 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Fri, 24 Apr 2020 12:38:24 +0200
Subject: [PATCH] ARM: dts: rockchip: add vpu node for RK322x
This adds VPU node to RK3228. While at it also add the required power-domain
controller and qos node to make the VPU work on this SoC.
---
arch/arm/boot/dts/rk322x.dtsi | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index f98a945c68d3..b233baeb20ef 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -680,6 +680,18 @@ opp-500000000 {
};
};
+ vpu: video-codec@20020000 {
+ compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
+ reg = <0x20020000 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3228_PD_VPU>;
+ };
+
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
From 2542e122786d27dfcf4bf2a60b2d91a4ae3a48dd Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 26 May 2020 14:11:57 +0200
Subject: [PATCH] media: hantro: add support for RK3188
RK3188s VPU IP-Block is the predecessor from what RK3288 has.
While most of the registers match in the current state of the driver
there are some HW differences:
- supports resultion up to 1920x1088 only
- has one aclk and one hclk per vdpu/vepu
- doesn't have the 'G1_REG_SOFT_RESET' register
- ACLKs can be clocked up to 300 MHz only
- no MMU for VPU
These make it necessary to add another variant to the driver.
This should be also reuseable for RK3066 but has not been tested,
so I'm not adding it here.
---
.../bindings/media/rockchip-vpu.yaml | 7 +-
drivers/staging/media/hantro/hantro_drv.c | 1 +
drivers/staging/media/hantro/hantro_hw.h | 1 +
drivers/staging/media/hantro/rk3288_vpu_hw.c | 116 ++++++++++++++++++
4 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
index ddbda080950e..1f0b3685fa85 100644
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
+ - rockchip,rk3188-vpu
- rockchip,rk3228-vpu
- rockchip,rk3288-vpu
- rockchip,rk3328-vpu
@@ -36,12 +37,16 @@ properties:
- const: vdpu
clocks:
- maxItems: 2
+ maxItems: 4
clock-names:
items:
- const: aclk
+ - const: aclk_vdpu
+ - const: aclk_vepu
- const: hclk
+ - const: hclk_vdpu
+ - const: hclk_vepu
power-domains:
maxItems: 1
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index 3cd00cc0a364..ecc0938b7f35 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -475,6 +475,7 @@ static const struct of_device_id of_hantro_match[] = {
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
+ { .compatible = "rockchip,rk3188-vpu", .data = &rk3188_vpu_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 7e35140a4f22..22b0ed01f673 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -152,6 +152,7 @@ enum hantro_enc_fmt {
RK3288_VPU_ENC_FMT_UYVY422 = 3,
};
+extern const struct hantro_variant rk3188_vpu_variant;
extern const struct hantro_variant rk3399_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
extern const struct hantro_variant rk3288_vpu_variant;
diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c
index 7b299ee3e93d..1ac00695a864 100644
--- a/drivers/staging/media/hantro/rk3288_vpu_hw.c
+++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c
@@ -13,6 +13,7 @@
#include "hantro_g1_regs.h"
#include "hantro_h1_regs.h"
+#define RK3188_ACLK_MAX_FREQ (300 * 1000 * 1000)
#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
/*
@@ -63,6 +64,52 @@ static const struct hantro_fmt rk3288_vpu_postproc_fmts[] = {
},
};
+static const struct hantro_fmt rk3188_vpu_dec_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .codec_mode = HANTRO_MODE_NONE,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_H264_SLICE,
+ .codec_mode = HANTRO_MODE_H264_DEC,
+ .max_depth = 2,
+ .frmsize = {
+ .min_width = 48,
+ .max_width = 1920,
+ .step_width = MB_DIM,
+ .min_height = 48,
+ .max_height = 1088,
+ .step_height = MB_DIM,
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
+ .codec_mode = HANTRO_MODE_MPEG2_DEC,
+ .max_depth = 2,
+ .frmsize = {
+ .min_width = 48,
+ .max_width = 1920,
+ .step_width = MB_DIM,
+ .min_height = 48,
+ .max_height = 1088,
+ .step_height = MB_DIM,
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_VP8_FRAME,
+ .codec_mode = HANTRO_MODE_VP8_DEC,
+ .max_depth = 2,
+ .frmsize = {
+ .min_width = 48,
+ .max_width = 1920,
+ .step_width = MB_DIM,
+ .min_height = 48,
+ .max_height = 1088,
+ .step_height = MB_DIM,
+ },
+ },
+};
+
static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12,
@@ -145,6 +192,14 @@ static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static int rk3188_vpu_hw_init(struct hantro_dev *vpu)
+{
+ /* Bump ACLKs to max. possible freq. to improve performance. */
+ clk_set_rate(vpu->clocks[0].clk, RK3188_ACLK_MAX_FREQ);
+ clk_set_rate(vpu->clocks[2].clk, RK3188_ACLK_MAX_FREQ);
+ return 0;
+}
+
static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLK to max. possible freq. to improve performance. */
@@ -161,6 +216,15 @@ static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx)
vepu_write(vpu, 0, H1_REG_AXI_CTRL);
}
+
+static void rk3188_vpu_dec_reset(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+
+ vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
+ vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
+}
+
static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
@@ -174,6 +238,33 @@ static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx)
* Supported codec ops.
*/
+static const struct hantro_codec_ops rk3188_vpu_codec_ops[] = {
+ [HANTRO_MODE_JPEG_ENC] = {
+ .run = hantro_h1_jpeg_enc_run,
+ .reset = rk3288_vpu_enc_reset,
+ .init = hantro_jpeg_enc_init,
+ .exit = hantro_jpeg_enc_exit,
+ },
+ [HANTRO_MODE_H264_DEC] = {
+ .run = hantro_g1_h264_dec_run,
+ .reset = rk3188_vpu_dec_reset,
+ .init = hantro_h264_dec_init,
+ .exit = hantro_h264_dec_exit,
+ },
+ [HANTRO_MODE_MPEG2_DEC] = {
+ .run = hantro_g1_mpeg2_dec_run,
+ .reset = rk3188_vpu_dec_reset,
+ .init = hantro_mpeg2_dec_init,
+ .exit = hantro_mpeg2_dec_exit,
+ },
+ [HANTRO_MODE_VP8_DEC] = {
+ .run = hantro_g1_vp8_dec_run,
+ .reset = rk3188_vpu_dec_reset,
+ .init = hantro_vp8_dec_init,
+ .exit = hantro_vp8_dec_exit,
+ },
+};
+
static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
[HANTRO_MODE_JPEG_ENC] = {
.run = hantro_h1_jpeg_enc_run,
@@ -211,10 +302,35 @@ static const struct hantro_irq rk3288_irqs[] = {
{ "vdpu", rk3288_vdpu_irq },
};
+static const char * const rk3188_clk_names[] = {
+ "aclk_vdpu", "hclk_vdpu",
+ "aclk_vepu", "hclk_vepu",
+};
+
static const char * const rk3288_clk_names[] = {
"aclk", "hclk"
};
+const struct hantro_variant rk3188_vpu_variant = {
+ .enc_offset = 0x0,
+ .enc_fmts = rk3288_vpu_enc_fmts,
+ .num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts),
+ .dec_offset = 0x400,
+ .dec_fmts = rk3188_vpu_dec_fmts,
+ .num_dec_fmts = ARRAY_SIZE(rk3188_vpu_dec_fmts),
+ .postproc_fmts = rk3288_vpu_postproc_fmts,
+ .num_postproc_fmts = ARRAY_SIZE(rk3288_vpu_postproc_fmts),
+ .postproc_regs = &hantro_g1_postproc_regs,
+ .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
+ .codec_ops = rk3188_vpu_codec_ops,
+ .irqs = rk3288_irqs,
+ .num_irqs = ARRAY_SIZE(rk3288_irqs),
+ .init = rk3188_vpu_hw_init,
+ .clk_names = rk3188_clk_names,
+ .num_clocks = ARRAY_SIZE(rk3188_clk_names)
+};
+
const struct hantro_variant rk3288_vpu_variant = {
.enc_offset = 0x0,
.enc_fmts = rk3288_vpu_enc_fmts,
From d99de1ed4674749d5c52b0acd9e22e04a08cf28b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 26 May 2020 14:12:35 +0200
Subject: [PATCH] ARM: dts: rockchip: add vpu node for RK3188
Add VPU node to RK3188s dtsi.
---
arch/arm/boot/dts/rk3188.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 79742ea997eb..74bb2525715c 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -141,6 +141,19 @@ smp-sram@0 {
};
};
+ vpu: video-codec@10104000 {
+ compatible = "rockchip,rk3188-vpu";
+ reg = <0x10104000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
+ clock-names = "aclk_vdpu", "hclk_vdpu",
+ "aclk_vepu", "hclk_vepu";
+ power-domains = <&power RK3188_PD_VIDEO>;
+ };
+
vop0: vop@1010c000 {
compatible = "rockchip,rk3188-vop";
reg = <0x1010c000 0x1000>;
From 0c4979901a6b29b3033b0c961d33cb8be9f7d46b Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 26 May 2020 17:24:12 +0200
Subject: [PATCH] media: hantro: add support for Rockchip RK3036
RK3036 shares the hantro VPU IP Block with RK3288.
HW differences are:
- supports decoding up to 1920x1088 only
- ACLK can be clocked at max. 300MHz
This makes adding another variant to the driver necessary here also.
However RK3036 TRM does not mention that it has an encoder also. I verfied
this on my devices and it worked for JPEG encoding. Since the identification
register share the id with RK3288 and the fact that it has an interrupt for
video encoding, makes me think that the encoding IP is the same.
This variant could also be used for RK312x, but has not been tested.
---
drivers/staging/media/hantro/hantro_drv.c | 1 +
drivers/staging/media/hantro/hantro_hw.h | 1 +
drivers/staging/media/hantro/rk3288_vpu_hw.c | 27 ++++++++++++++++++++
3 files changed, 29 insertions(+)
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index ecc0938b7f35..ee59fad9a2f3 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -476,6 +476,7 @@ static const struct of_device_id of_hantro_match[] = {
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
{ .compatible = "rockchip,rk3188-vpu", .data = &rk3188_vpu_variant, },
+ { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 22b0ed01f673..ede7acec5e9f 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -152,6 +152,7 @@ enum hantro_enc_fmt {
RK3288_VPU_ENC_FMT_UYVY422 = 3,
};
+extern const struct hantro_variant rk3036_vpu_variant;
extern const struct hantro_variant rk3188_vpu_variant;
extern const struct hantro_variant rk3399_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c
index 1ac00695a864..b5887fdae250 100644
--- a/drivers/staging/media/hantro/rk3288_vpu_hw.c
+++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c
@@ -192,6 +192,13 @@ static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
+{
+ /* Bump ACLK to max. possible freq. to improve performance. */
+ clk_set_rate(vpu->clocks[0].clk, RK3188_ACLK_MAX_FREQ);
+ return 0;
+}
+
static int rk3188_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLKs to max. possible freq. to improve performance. */
@@ -311,6 +318,26 @@ static const char * const rk3288_clk_names[] = {
"aclk", "hclk"
};
+const struct hantro_variant rk3036_vpu_variant = {
+ .enc_offset = 0x0,
+ .enc_fmts = rk3288_vpu_enc_fmts,
+ .num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts),
+ .dec_offset = 0x400,
+ .dec_fmts = rk3188_vpu_dec_fmts,
+ .num_dec_fmts = ARRAY_SIZE(rk3188_vpu_dec_fmts),
+ .postproc_fmts = rk3288_vpu_postproc_fmts,
+ .num_postproc_fmts = ARRAY_SIZE(rk3288_vpu_postproc_fmts),
+ .postproc_regs = &hantro_g1_postproc_regs,
+ .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
+ .codec_ops = rk3288_vpu_codec_ops,
+ .irqs = rk3288_irqs,
+ .num_irqs = ARRAY_SIZE(rk3288_irqs),
+ .init = rk3036_vpu_hw_init,
+ .clk_names = rk3288_clk_names,
+ .num_clocks = ARRAY_SIZE(rk3288_clk_names)
+};
+
const struct hantro_variant rk3188_vpu_variant = {
.enc_offset = 0x0,
.enc_fmts = rk3288_vpu_enc_fmts,
From 3d1b0b0c9d0188fa39b42e24bf973bb051c032b1 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 26 May 2020 17:42:55 +0200
Subject: [PATCH] ARM: dts: rockchip: add vpu node for RK3036
This adds VPU node to RK3036. While at it also add the required mmu,
power-domain controller and qos node to make the VPU work on this SoC.
---
arch/arm/boot/dts/rk3036.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index a86e1dc7fb5b..ef8ceed78f73 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -136,6 +136,29 @@ gpu: gpu@10090000 {
status = "disabled";
};
+ vpu: video-codec@10108000 {
+ compatible = "rockchip,rk3036-vpu";
+ reg = <0x10108000 0x800>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3036_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@10108800 {
+ compatible = "rockchip,iommu";
+ reg = <0x10108800 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3036_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
From 996f741a44faecc4b9485ee0b8258b3e3441474e Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 26 May 2020 17:54:22 +0200
Subject: [PATCH] media: hantro: adapt Kconfig help text
Add RK3036, RK3066, RK3188 and RK322x to Kconfig help
text
---
drivers/staging/media/hantro/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
index 5b6cf9f62b1a..ef8bd5067be8 100644
--- a/drivers/staging/media/hantro/Kconfig
+++ b/drivers/staging/media/hantro/Kconfig
@@ -30,4 +30,5 @@ config VIDEO_HANTRO_ROCKCHIP
depends on ARCH_ROCKCHIP || COMPILE_TEST
default y
help
- Enable support for RK3288, RK3328, and RK3399 SoCs.
+ Enable support for RK3036, RK3066, RK3188, RK322x
+ RK3288, RK3328 and RK3399 SoCs.
From 839059f221d04ef0a6c7e03bcade1e50148d06cd Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sat, 23 May 2020 14:22:54 +0200
Subject: [PATCH] ARM: dts: rockchip: add vdec node for RK322x
RK322x has the same VDEC IP block as RK3399 has and the driver in its
current state can be used as is.
Other than RK3399 its SCLKs have also to set to a fixed value to make it
work correctly. Rather than doing this in the driver it is done via
"assigned-clocks" in the vdec node.
---
arch/arm/boot/dts/rk322x.dtsi | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index b233baeb20ef..de5727e0bc94 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -703,6 +703,27 @@ vpu_mmu: iommu@20020800 {
power-domains = <&power RK3228_PD_VPU>;
};
+ vdec: video-codec@20030000 {
+ compatible = "rockchip,rk322x-vdec", "rockchip,rk3399-vdec";
+ reg = <0x20030000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <500000000>, <300000000>,
+ <300000000>;
+ resets = <&cru SRST_RKVDEC_H>, <&cru SRST_RKVDEC_A>,
+ <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_CABAC>,
+ <&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>;
+ reset-names = "video_h", "video_a",
+ "video_core", "video_cabac",
+ "niu_a", "niu_h";
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ iommus = <&vdec_mmu>;
+ };
+
vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
From 7123c3d575df39ea102be56374fbc82a02d59ff2 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 19 Aug 2020 21:12:54 +0200
Subject: [PATCH] arm64: dts: rockchip: add rkvdec node for RK3328
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 26 +++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index abe7f1573825..9a7a5c1adaa8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -327,6 +327,10 @@ pd_hevc@RK3328_PD_HEVC {
};
pd_video@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
};
pd_vpu@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
@@ -672,6 +676,26 @@ vpu_mmu: iommu@ff350800 {
power-domains = <&power RK3328_PD_VPU>;
};
+ rkvdec: video-codec@ff360000 {
+ compatible = "rockchip,rk3399-vdec";
+ reg = <0x0 0xff360000 0x0 0x480>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu";
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <500000000>, <300000000>, <250000000>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ iommus = <&rkvdec_mmu>;
+ power-domains = <&power RK3328_PD_VIDEO>;
+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
+ reset-names = "video_h", "video_a",
+ "video_core", "video_cabac",
+ "niu_a", "niu_h";
+ }
+
rkvdec_mmu: iommu@ff360480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
@@ -680,7 +704,7 @@ rkvdec_mmu: iommu@ff360480 {
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3328_PD_VIDEO>;
};
vop: vop@ff370000 {
From e6885f7f00a88d6b7c7938b77874e466e48ba9d9 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 13:27:12 +0200
Subject: [PATCH] media: hantro: adapt to match 5.11 H.264 uapi changes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/hantro/hantro_h264.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
index bc2af450a94c..7bdefcc2fc77 100644
--- a/drivers/staging/media/hantro/hantro_h264.c
+++ b/drivers/staging/media/hantro/hantro_h264.c
@@ -241,10 +241,10 @@ static void prepare_table(struct hantro_ctx *ctx)
if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
// check for correct reference use
- enum v4l2_h264_field_reference parity = (i & 0x1) ?
+ u8 parity = (i & 0x1) ?
V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE &&
- dpb[i / 2].reference & parity)
+ dpb[i / 2].fields & parity)
dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
From 133d19f65874d3a3c7302ea7e2c1423e4b574545 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 13:42:01 +0200
Subject: [PATCH] media: rkvdec: adapt to match 5.11 H.264 uapi changes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index d4f27ef7addd..627cd4efabef 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
}
for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
- enum v4l2_h264_field_reference a_parity =
+ u8 a_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF;
- enum v4l2_h264_field_reference b_parity =
+ u8 b_parity =
(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)
? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF;
u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM;
@@ -802,7 +802,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][a];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & a_parity) == a_parity &&
+ if ((dpb[idx].fields & a_parity) == a_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
@@ -817,7 +817,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
u8 idx = reflists[j][b];
if (idx >= ARRAY_SIZE(dec_params->dpb))
continue;
- if ((dpb[idx].reference & b_parity) == b_parity &&
+ if ((dpb[idx].fields & b_parity) == b_parity &&
(dpb[idx].flags & flags) == long_term) {
set_ps_field(hw_rps, DPB_INFO(i, j),
idx | (1 << 4));
From 44db6f132cfe12d3042e521d55d01e71b3b68f92 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Thu, 23 Jul 2020 17:25:12 +0200
Subject: [PATCH] ARM: dts: add vpu node for RK3066
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rk3066a.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index f71529e6949f..d9984d0f8f23 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -194,6 +194,19 @@ smp-sram@0 {
};
};
+ vpu: video-codec@10104000 {
+ compatible = "rockchip,rk3188-vpu";
+ reg = <0x10104000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
+ clock-names = "aclk_vdpu", "hclk_vdpu",
+ "aclk_vepu", "hclk_vepu";
+ power-domains = <&power RK3066_PD_VIDEO>;
+ };
+
vop0: vop@1010c000 {
compatible = "rockchip,rk3066-vop";
reg = <0x1010c000 0x19c>;
From 4b90b0c9d234efda1e91a2a4ffb8fd01882225ea Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 17:03:12 +0200
Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding
* Add some meaningful message here *
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
.../bindings/media/rockchip-iep.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml
diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
new file mode 100644
index 000000000000..0be78de932db
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-iep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Image Enhancement Processor (IEP)
+
+description:
+ Rockchip IEP supports various image enhancement operations for YUV and RGB domains.
+ Deinterlacing, spatial and temporal sampling noise reduction are supported by the
+ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in
+ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for
+ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB.
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3228-iep
+ - items:
+ - enum:
+ - rockchip,rk3288-iep
+ - rockchip,rk3328-iep
+ - rockchip,rk3368-iep
+ - rockchip,rk3399-iep
+ - const: rockchip,rk3228-iep
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: axi
+ - const: ahb
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: axi
+ - const: ahb
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3228-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3228-power.h>
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_IEP_A>,
+ <&cru SRST_IEP_H>;
+ reset-names = "axi", "ahb";
+ power-domains = <&power RK3228_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
From 76673c3abd13bcdb53915d9c0e909d287a13b41d Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 21:24:10 +0200
Subject: [PATCH] media: rockchip: Add Rockchip IEP driver
* Add some meaningful message here *
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
drivers/media/platform/Kconfig | 14 +
drivers/media/platform/Makefile | 1 +
drivers/media/platform/rockchip/iep/Makefile | 5 +
.../media/platform/rockchip/iep/iep-regs.h | 291 +++++
drivers/media/platform/rockchip/iep/iep.c | 1121 +++++++++++++++++
drivers/media/platform/rockchip/iep/iep.h | 114 ++
6 files changed, 1546 insertions(+)
create mode 100644 drivers/media/platform/rockchip/iep/Makefile
create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h
create mode 100644 drivers/media/platform/rockchip/iep/iep.c
create mode 100644 drivers/media/platform/rockchip/iep/iep.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 7e152bbb4fa6..eee78b20c791 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -462,6 +462,20 @@ config VIDEO_RENESAS_VSP1
To compile this driver as a module, choose M here: the module
will be called vsp1.
+config VIDEO_ROCKCHIP_IEP
+ tristate "Rockchip Image Enhancement Processor"
+ depends on VIDEO_DEV && VIDEO_V4L2
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_MEM2MEM_DEV
+ help
+ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
+ found in most Rockchip RK3xxx SoCs.
+ Rockchip IEP supports various enhancement operations for RGB and YUV
+ images. The driver currently implements YUV deinterlacing only.
+ To compile this driver as a module, choose M here: the module
+ will be called rockchip-iep
+
config VIDEO_ROCKCHIP_RGA
tristate "Rockchip Raster 2d Graphic Acceleration Unit"
depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 62b6cdc8c730..f99a873818d5 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o
obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o
obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/
+obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip/iep/
obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/
obj-y += omap/
diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile
new file mode 100644
index 000000000000..5c89b3277469
--- /dev/null
+++ b/drivers/media/platform/rockchip/iep/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+rockchip-iep-objs := iep.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o
diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h
new file mode 100644
index 000000000000..a68685ef3604
--- /dev/null
+++ b/drivers/media/platform/rockchip/iep/iep-regs.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ */
+
+#ifndef __IEP_REGS_H__
+#define __IEP_REGS_H__
+
+/* IEP Registers addresses */
+#define IEP_CONFIG0 0x000 /* Configuration register0 */
+#define IEP_VOP_DIRECT_PATH BIT(0)
+#define IEP_DEIN_HIGH_FREQ_SHFT 1
+#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT)
+#define IEP_DEIN_MODE_SHFT 8
+#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT)
+#define IEP_DEIN_HIGH_FREQ_EN BIT(11)
+#define IEP_DEIN_EDGE_INTPOL_EN BIT(12)
+#define IEP_YUV_DENOISE_EN BIT(13)
+#define IEP_YUV_ENHNC_EN BIT(14)
+#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15)
+#define IEP_RGB_CLR_ENHNC_EN BIT(16)
+#define IEP_RGB_CNTRST_ENHNC_EN BIT(17)
+#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18)
+#define IEP_RGB_ENHNC_MODE_DNS BIT(18)
+#define IEP_RGB_ENHNC_MODE_DTL (2 << 18)
+#define IEP_RGB_ENHNC_MODE_EDG (3 << 18)
+#define IEP_RGB_ENHNC_MODE_MASK (3 << 18)
+#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20)
+#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21
+#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
+#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23)
+
+#define IEP_CONFIG1 0x004 /* Configuration register1 */
+#define IEP_SRC_FMT_SHFT 0
+#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT)
+#define IEP_SRC_RGB_SWP_SHFT 2
+#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT)
+#define IEP_SRC_YUV_SWP_SHFT 4
+#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT)
+#define IEP_DST_FMT_SHFT 8
+#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT)
+#define IEP_DST_RGB_SWP_SHFT 10
+#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT)
+#define IEP_DST_YUV_SWP_SHFT 12
+#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT)
+#define IEP_DTH_UP_EN BIT(14)
+#define IEP_DTH_DWN_EN BIT(15)
+#define IEP_YUV2RGB_COE_BT601_1 (0 << 16)
+#define IEP_YUV2RGB_COE_BT601_F BIT(16)
+#define IEP_YUV2RGB_COE_BT709_1 (2 << 16)
+#define IEP_YUV2RGB_COE_BT709_F (3 << 16)
+#define IEP_YUV2RGB_COE_MASK (3 << 16)
+#define IEP_RGB2YUV_COE_BT601_1 (0 << 18)
+#define IEP_RGB2YUV_COE_BT601_F BIT(18)
+#define IEP_RGB2YUV_COE_BT709_1 (2 << 18)
+#define IEP_RGB2YUV_COE_BT709_F (3 << 18)
+#define IEP_RGB2YUV_COE_MASK (3 << 18)
+#define IEP_YUV2RGB_EN BIT(20)
+#define IEP_RGB2YUV_EN BIT(21)
+#define IEP_YUV2RGB_CLIP_EN BIT(22)
+#define IEP_RGB2YUV_CLIP_EN BIT(23)
+#define IEP_GLB_ALPHA_SHFT 24
+#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT)
+
+#define IEP_STATUS 0x008 /* Status register */
+#define IEP_STATUS_YUV_DNS BIT(0)
+#define IEP_STATUS_SCL BIT(1)
+#define IEP_STATUS_DIL BIT(2)
+#define IEP_STATUS_DDE BIT(3)
+#define IEP_STATUS_DMA_WR_YUV BIT(4)
+#define IEP_STATUS_DMA_RE_YUV BIT(5)
+#define IEP_STATUS_DMA_WR_RGB BIT(6)
+#define IEP_STATUS_DMA_RE_RGB BIT(7)
+#define IEP_STATUS_VOP_DIRECT_PATH BIT(8)
+#define IEP_STATUS_DMA_IA_WR_YUV BIT(16)
+#define IEP_STATUS_DMA_IA_RE_YUV BIT(17)
+#define IEP_STATUS_DMA_IA_WR_RGB BIT(18)
+#define IEP_STATUS_DMA_IA_RE_RGB BIT(19)
+
+#define IEP_INT 0x00c /* Interrupt register*/
+#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */
+#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */
+#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */
+
+#define IEP_FRM_START 0x010 /* Frame start */
+#define IEP_SRST 0x014 /* Soft reset */
+#define IEP_CONFIG_DONE 0x018 /* Configuration done */
+#define IEP_FRM_CNT 0x01c /* Frame counter */
+
+#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */
+#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */
+#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */
+#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */
+#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */
+#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */
+#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */
+#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */
+
+#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */
+#define IEP_YUV_BRIGHTNESS_SHFT 0
+#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT)
+#define IEP_YUV_CONTRAST_SHFT 8
+#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT)
+#define IEP_YUV_SATURATION_SHFT 16
+#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT)
+
+#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */
+#define IEP_YUV_COS_HUE_SHFT 0
+#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT)
+#define IEP_YUV_SIN_HUE_SHFT 8
+#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT)
+
+#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */
+#define IEP_YUV_COLOR_BAR_Y_SHFT 0
+#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT)
+#define IEP_YUV_COLOR_BAR_U_SHFT 8
+#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT)
+#define IEP_YUV_COLOR_BAR_V_SHFT 16
+#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT)
+#define IEP_YUV_VIDEO_MODE_SHFT 24
+#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT)
+
+#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */
+#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */
+
+#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */
+#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */
+#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */
+#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */
+#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */
+#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */
+#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */
+#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */
+#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */
+#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */
+
+#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */
+#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */
+#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */
+#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */
+#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */
+#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */
+#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */
+#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */
+#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */
+#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */
+#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */
+#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */
+
+#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */
+#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */
+#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */
+#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */
+#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */
+#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */
+#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */
+#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/
+#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */
+#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */
+#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */
+#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/
+
+#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */
+#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */
+#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */
+#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */
+#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */
+#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */
+#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */
+#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */
+
+#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */
+#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */
+#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */
+
+#define IEP_INT_MASK (IEP_INT_FRAME_DONE)
+
+/* IEP colorformats */
+#define IEP_COLOR_FMT_XRGB 0U
+#define IEP_COLOR_FMT_RGB565 1U
+#define IEP_COLOR_FMT_YUV422 2U
+#define IEP_COLOR_FMT_YUV420 3U
+
+/* IEP YUV color swaps */
+#define IEP_YUV_SWP_SP_UV 0U
+#define IEP_YUV_SWP_SP_VU 1U
+#define IEP_YUV_SWP_P 2U
+
+/* IEP XRGB color swaps */
+#define XRGB_SWP_XRGB 0U
+#define XRGB_SWP_XBGR 1U
+#define XRGB_SWP_BGRX 2U
+
+/* IEP RGB565 color swaps */
+#define RGB565_SWP_RGB 0U
+#define RGB565_SWP_BGR 1U
+
+#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1)
+
+#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \
+ ((h - 1) & 0x1fff) << 16)
+
+#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \
+ ((dst_w / 4) & 0x1fff) << 16)
+
+#define IEP_Y_STRIDE(w, h) (w * h)
+#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac)
+
+#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK)
+#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK)
+
+#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \
+ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT)))
+#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \
+ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT)))
+
+/* IEP DEINTERLACE MODES */
+#define IEP_DEIN_MODE_YUV 0U
+#define IEP_DEIN_MODE_I4O2 1U
+#define IEP_DEIN_MODE_I4O1B 2U
+#define IEP_DEIN_MODE_I4O1T 3U
+#define IEP_DEIN_MODE_I2O1B 4U
+#define IEP_DEIN_MODE_I2O1T 5U
+#define IEP_DEIN_MODE_BYPASS 6U
+
+#define IEP_DEIN_IN_FIELDS_2 2U
+#define IEP_DEIN_IN_FIELDS_4 4U
+
+#define IEP_DEIN_OUT_FRAMES_1 1U
+#define IEP_DEIN_OUT_FRAMES_2 2U
+
+/* values taken from BSP driver */
+static const u32 default_dein_motion_tbl[][2] = {
+ { IEP_DEIN_MTN_TAB0, 0x40404040 },
+ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f },
+ { IEP_DEIN_MTN_TAB2, 0x3336393b },
+ { IEP_DEIN_MTN_TAB3, 0x272a2d31 },
+ { IEP_DEIN_MTN_TAB4, 0x181c2023 },
+ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 },
+ { IEP_DEIN_MTN_TAB6, 0x03040609 },
+ { IEP_DEIN_MTN_TAB7, 0x00000001 },
+
+};
+
+#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1)
+#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1)
+#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1)
+#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff))
+#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff))
+#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff))
+
+#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB)
+#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR)
+#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR)
+#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff))
+#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff))
+#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff))
+
+#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT)
+
+#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \
+ || m == IEP_DEIN_MODE_I4O2) \
+ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2)
+
+#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \
+ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1)
+
+#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \
+ ? 1 : 0)
+
+#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT)
+
+#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT)
+
+/* YUV Enhance video modes */
+#define VIDEO_MODE_BLACK_SCREEN 0U
+#define VIDEO_MODE_BLUE_SCREEN 1U
+#define VIDEO_MODE_COLOR_BARS 2U
+#define VIDEO_MODE_NORMAL_VIDEO 3U
+
+#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK)
+#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK)
+#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK)
+#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK)
+#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK)
+#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK)
+
+#endif
diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c
new file mode 100644
index 000000000000..93954e6c4c4d
--- /dev/null
+++ b/drivers/media/platform/rockchip/iep/iep.c
@@ -0,0 +1,1121 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+#include <linux/videodev2.h>
+
+#include "iep-regs.h"
+#include "iep.h"
+
+static struct iep_fmt formats[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .color_swap = IEP_YUV_SWP_SP_UV,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .color_swap = IEP_YUV_SWP_SP_VU,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .color_swap = IEP_YUV_SWP_SP_UV,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .color_swap = IEP_YUV_SWP_SP_VU,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .color_swap = IEP_YUV_SWP_P,
+ .hw_format = IEP_COLOR_FMT_YUV420,
+ .depth = 12,
+ .uv_factor = 4,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .color_swap = IEP_YUV_SWP_P,
+ .hw_format = IEP_COLOR_FMT_YUV422,
+ .depth = 16,
+ .uv_factor = 2,
+ },
+};
+
+static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++) {
+ if (formats[i].fourcc == pix_fmt->pixelformat)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+static bool iep_check_pix_format(u32 pixelformat)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++)
+ if (formats[i].fourcc == pixelformat)
+ return true;
+
+ return false;
+}
+
+static struct vb2_v4l2_buffer *iep_m2m_next_src_buf(struct iep_ctx *ctx)
+{
+ struct vb2_v4l2_buffer *src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+
+ /* applcication has set a sequence: take it as start point */
+ if (ctx->src_sequence == 0 && src_buf->sequence > 0)
+ ctx->src_sequence = src_buf->sequence;
+
+ src_buf->sequence = ctx->src_sequence++;
+
+ return src_buf;
+}
+
+static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx)
+{
+ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+
+ /* applcication has set a sequence: take it as start point */
+ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0)
+ ctx->dst_sequence = dst_buf->sequence;
+
+ dst_buf->sequence = ctx->dst_sequence++;
+
+ return dst_buf;
+}
+
+static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state)
+{
+ if (ctx->dst0_buf) {
+ v4l2_m2m_buf_done(ctx->dst0_buf, state);
+ ctx->dst_buffs_done++;
+ ctx->dst0_buf = NULL;
+ }
+
+ if (ctx->dst1_buf) {
+ v4l2_m2m_buf_done(ctx->dst1_buf, state);
+ ctx->dst_buffs_done++;
+ ctx->dst1_buf = NULL;
+ }
+}
+
+static void iep_setup_formats(struct iep_ctx *ctx)
+{
+ /* setup src dimensions */
+ iep_write(ctx->iep, IEP_SRC_IMG_SIZE,
+ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height));
+
+ /* setup dst dimensions */
+ iep_write(ctx->iep, IEP_DST_IMG_SIZE,
+ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height));
+
+ /* setup virtual width */
+ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH,
+ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width));
+
+ /* setup src format */
+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
+ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format),
+ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format,
+ ctx->src_fmt.hw_fmt->color_swap));
+ /* setup dst format */
+ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1,
+ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format),
+ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format,
+ ctx->dst_fmt.hw_fmt->color_swap));
+
+ ctx->fmt_changed = false;
+}
+
+static void iep_dein_init(struct rockchip_iep *iep)
+{
+ unsigned int i;
+
+ /* values taken from BSP driver */
+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
+ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK |
+ IEP_DEIN_HIGH_FREQ_EN |
+ IEP_DEIN_HIGH_FREQ_MASK),
+ (IEP_DEIN_EDGE_INTPOL_SMTH_EN |
+ IEP_DEIN_EDGE_INTPOL_RADIUS(3) |
+ IEP_DEIN_HIGH_FREQ_EN |
+ IEP_DEIN_HIGH_FREQ(64)));
+
+ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++)
+ iep_write(iep, default_dein_motion_tbl[i][0],
+ default_dein_motion_tbl[i][1]);
+}
+
+static void iep_init(struct rockchip_iep *iep)
+{
+ iep_write(iep, IEP_CONFIG0,
+ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // |
+ //IEP_YUV_ENHNC_EN
+ );
+
+ /* TODO: B/S/C/H works
+ * only in 1-frame-out modes
+ iep_write(iep, IEP_ENH_YUV_CNFG_0,
+ YUV_BRIGHTNESS(0) |
+ YUV_CONTRAST(128) |
+ YUV_SATURATION(128));
+
+ iep_write(iep, IEP_ENH_YUV_CNFG_1,
+ YUV_COS_HUE(255) |
+ YUV_SIN_HUE(255));
+
+ iep_write(iep, IEP_ENH_YUV_CNFG_2,
+ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO));
+
+ */
+
+ /* reset frame counter */
+ iep_write(iep, IEP_FRM_CNT, 0);
+}
+
+static void iep_device_run(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+ struct rockchip_iep *iep = ctx->iep;
+ struct vb2_v4l2_buffer *src, *dst;
+ unsigned int dein_mode;
+ dma_addr_t addr;
+
+ if (ctx->fmt_changed)
+ iep_setup_formats(ctx);
+
+ if (ctx->prev_src_buf)
+ dein_mode = IEP_DEIN_MODE_I4O2;
+ else
+ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T;
+
+ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0,
+ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode));
+
+ /* sync RAW_xxx registers with actual used */
+ iep_write(iep, IEP_CONFIG_DONE, 1);
+
+ /* setup src buff(s)/addresses */
+ src = iep_m2m_next_src_buf(ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff),
+ addr + ctx->src_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff),
+ addr + ctx->src_fmt.uv_stride);
+
+ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4)
+ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff),
+ addr + ctx->src_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff),
+ addr + ctx->src_fmt.uv_stride);
+
+ /* setup dst buff(s)/addresses */
+ dst = iep_m2m_next_dst_buf(ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
+
+ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) {
+ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff),
+ addr + ctx->dst_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff),
+ addr + ctx->dst_fmt.uv_stride);
+
+ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ dst = iep_m2m_next_dst_buf(ctx);
+ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
+ }
+
+ v4l2_m2m_buf_copy_metadata(src, dst, true);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff),
+ addr + ctx->dst_fmt.y_stride);
+
+ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff),
+ addr + ctx->dst_fmt.uv_stride);
+
+ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN,
+ IEP_INT_FRAME_DONE_EN);
+
+ /* start HW */
+ iep_write(iep, IEP_FRM_START, 1);
+}
+
+static int iep_job_ready(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+
+ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 &&
+ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1;
+}
+
+static void iep_job_abort(void *priv)
+{
+ struct iep_ctx *ctx = priv;
+
+ /* Will cancel the transaction in the next interrupt handler */
+ ctx->job_abort = true;
+}
+
+static const struct v4l2_m2m_ops iep_m2m_ops = {
+ .device_run = iep_device_run,
+ .job_ready = iep_job_ready,
+ .job_abort = iep_job_abort,
+};
+
+static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
+ unsigned int *nplanes, unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct v4l2_pix_format *pix_fmt;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ pix_fmt = &ctx->src_fmt.pix;
+ else
+ pix_fmt = &ctx->dst_fmt.pix;
+
+ if (*nplanes) {
+ if (sizes[0] < pix_fmt->sizeimage)
+ return -EINVAL;
+ } else {
+ sizes[0] = pix_fmt->sizeimage;
+ *nplanes = 1;
+ }
+
+ return 0;
+}
+
+static int iep_buf_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct v4l2_pix_format *pix_fmt;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ pix_fmt = &ctx->src_fmt.pix;
+ else
+ pix_fmt = &ctx->dst_fmt.pix;
+
+ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)
+ return -EINVAL;
+
+ /* set bytesused for capture buffers */
+ if (!V4L2_TYPE_IS_OUTPUT(vq->type))
+ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);
+
+ return 0;
+}
+
+static void iep_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static void iep_queue_cleanup(struct vb2_queue *vq, u32 state)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct vb2_v4l2_buffer *vbuf;
+
+ do {
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ else
+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ if (vbuf)
+ v4l2_m2m_buf_done(vbuf, state);
+ } while (vbuf);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf)
+ v4l2_m2m_buf_done(ctx->prev_src_buf, state);
+ else
+ iep_m2m_dst_bufs_done(ctx, state);
+}
+
+static int iep_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+ struct device *dev = ctx->iep->dev;
+ int ret;
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable module\n");
+ goto err_runtime_get;
+ }
+
+ ctx->field_order_bff =
+ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT;
+ ctx->field_bff = ctx->field_order_bff;
+
+ ctx->src_sequence = 0;
+ ctx->dst_sequence = 0;
+
+ ctx->prev_src_buf = NULL;
+
+ ctx->dst0_buf = NULL;
+ ctx->dst1_buf = NULL;
+ ctx->dst_buffs_done = 0;
+
+ ctx->job_abort = false;
+
+ iep_init(ctx->iep);
+ //if (ctx->src_fmt.pix.field != ctx->src_fmt.pix.field)
+ iep_dein_init(ctx->iep);
+ }
+
+ return 0;
+
+err_runtime_get:
+ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);
+
+ return ret;
+}
+
+static void iep_stop_streaming(struct vb2_queue *vq)
+{
+ struct iep_ctx *ctx = vb2_get_drv_priv(vq);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
+ pm_runtime_mark_last_busy(ctx->iep->dev);
+ pm_runtime_put_autosuspend(ctx->iep->dev);
+ }
+
+ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops iep_qops = {
+ .queue_setup = iep_queue_setup,
+ .buf_prepare = iep_buf_prepare,
+ .buf_queue = iep_buf_queue,
+ .start_streaming = iep_start_streaming,
+ .stop_streaming = iep_stop_streaming,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+};
+
+static int iep_queue_init(void *priv, struct vb2_queue *src_vq,
+ struct vb2_queue *dst_vq)
+{
+ struct iep_ctx *ctx = priv;
+ int ret;
+
+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
+ DMA_ATTR_NO_KERNEL_MAPPING;
+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ src_vq->drv_priv = ctx;
+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ src_vq->min_buffers_needed = 1;
+ src_vq->ops = &iep_qops;
+ src_vq->mem_ops = &vb2_dma_contig_memops;
+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ src_vq->lock = &ctx->iep->mutex;
+ src_vq->dev = ctx->iep->v4l2_dev.dev;
+
+ ret = vb2_queue_init(src_vq);
+ if (ret)
+ return ret;
+
+ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
+ DMA_ATTR_NO_KERNEL_MAPPING;
+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ dst_vq->drv_priv = ctx;
+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ dst_vq->min_buffers_needed = 2;
+ dst_vq->ops = &iep_qops;
+ dst_vq->mem_ops = &vb2_dma_contig_memops;
+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ dst_vq->lock = &ctx->iep->mutex;
+ dst_vq->dev = ctx->iep->v4l2_dev.dev;
+
+ ret = vb2_queue_init(dst_vq);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void iep_prepare_format(struct v4l2_pix_format *pix_fmt)
+{
+ unsigned int height = pix_fmt->height;
+ unsigned int width = pix_fmt->width;
+ unsigned int sizeimage, bytesperline;
+
+ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt);
+
+ if (!hw_fmt) {
+ hw_fmt = &formats[0];
+ pix_fmt->pixelformat = hw_fmt->fourcc;
+ }
+
+ width = ALIGN(clamp(width, IEP_MIN_WIDTH,
+ IEP_MAX_WIDTH), 16);
+ height = ALIGN(clamp(height, IEP_MIN_HEIGHT,
+ IEP_MAX_HEIGHT), 16);
+
+ bytesperline = FMT_IS_YUV(hw_fmt->hw_format)
+ ? width : (width * hw_fmt->depth) >> 3;
+
+ sizeimage = height * (width * hw_fmt->depth) >> 3;
+
+ pix_fmt->width = width;
+ pix_fmt->height = height;
+ pix_fmt->bytesperline = bytesperline;
+ pix_fmt->sizeimage = sizeimage;
+}
+
+static int iep_open(struct file *file)
+{
+ struct rockchip_iep *iep = video_drvdata(file);
+ struct iep_ctx *ctx = NULL;
+
+ int ret;
+
+ if (mutex_lock_interruptible(&iep->mutex))
+ return -ERESTARTSYS;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx) {
+ mutex_unlock(&iep->mutex);
+ return -ENOMEM;
+ }
+
+ /* default output format */
+ ctx->src_fmt.pix.pixelformat = formats[0].fourcc;
+ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED;
+ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH;
+ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT;
+ iep_prepare_format(&ctx->src_fmt.pix);
+ ctx->src_fmt.hw_fmt = &formats[0];
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height,
+ ctx->src_fmt.hw_fmt->uv_factor);
+
+ /* default capture format */
+ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc;
+ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE;
+ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH;
+ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT;
+ iep_prepare_format(&ctx->dst_fmt.pix);
+ ctx->dst_fmt.hw_fmt = &formats[0];
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+ /* ensure fmts are written to HW */
+ ctx->fmt_changed = true;
+
+ v4l2_fh_init(&ctx->fh, video_devdata(file));
+ file->private_data = &ctx->fh;
+ ctx->iep = iep;
+
+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx,
+ &iep_queue_init);
+
+ if (IS_ERR(ctx->fh.m2m_ctx)) {
+ ret = PTR_ERR(ctx->fh.m2m_ctx);
+ goto err_free;
+ }
+
+ v4l2_fh_add(&ctx->fh);
+
+ mutex_unlock(&iep->mutex);
+
+ return 0;
+
+err_free:
+ kfree(ctx);
+ mutex_unlock(&iep->mutex);
+
+ return ret;
+}
+
+static int iep_release(struct file *file)
+{
+ struct rockchip_iep *iep = video_drvdata(file);
+ struct iep_ctx *ctx = container_of(file->private_data,
+ struct iep_ctx, fh);
+
+ mutex_lock(&iep->mutex);
+
+ v4l2_fh_del(&ctx->fh);
+ v4l2_fh_exit(&ctx->fh);
+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+ kfree(ctx);
+
+ mutex_unlock(&iep->mutex);
+ return 0;
+}
+
+static const struct v4l2_file_operations iep_fops = {
+ .owner = THIS_MODULE,
+ .open = iep_open,
+ .release = iep_release,
+ .poll = v4l2_m2m_fop_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = v4l2_m2m_fop_mmap,
+};
+
+static int iep_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver));
+ strscpy(cap->card, IEP_NAME, sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info),
+ "platform:%s", IEP_NAME);
+
+ return 0;
+}
+
+static int iep_enum_fmt(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct iep_fmt *fmt;
+
+ if (f->index < ARRAY_SIZE(formats)) {
+ fmt = &formats[f->index];
+ f->pixelformat = fmt->fourcc;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int iep_enum_framesizes(struct file *file, void *priv,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index != 0)
+ return -EINVAL;
+
+ if (!iep_check_pix_format(fsize->pixel_format))
+ return -EINVAL;
+
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+
+ fsize->stepwise.min_width = IEP_MIN_WIDTH;
+ fsize->stepwise.max_width = IEP_MAX_WIDTH;
+ fsize->stepwise.step_width = 16;
+
+ fsize->stepwise.min_height = IEP_MIN_HEIGHT;
+ fsize->stepwise.max_height = IEP_MAX_HEIGHT;
+ fsize->stepwise.step_height = 16;
+
+ return 0;
+}
+
+static inline struct iep_ctx *iep_file2ctx(struct file *file)
+{
+ return container_of(file->private_data, struct iep_ctx, fh);
+}
+
+static int iep_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+
+ f->fmt.pix = ctx->dst_fmt.pix;
+
+ return 0;
+}
+
+static int iep_g_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+
+ f->fmt.pix = ctx->src_fmt.pix;
+
+ return 0;
+}
+
+static int iep_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ f->fmt.pix.field = V4L2_FIELD_NONE;
+ iep_prepare_format(&f->fmt.pix);
+
+ return 0;
+}
+
+static int iep_try_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
+ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
+ f->fmt.pix.field != V4L2_FIELD_INTERLACED)
+ f->fmt.pix.field = V4L2_FIELD_INTERLACED;
+
+ iep_prepare_format(&f->fmt.pix);
+
+ return 0;
+}
+
+static int iep_s_fmt_vid_out(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+ struct vb2_queue *vq;
+
+ int ret;
+
+ ret = iep_try_fmt_vid_out(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ ctx->src_fmt.pix = f->fmt.pix;
+ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
+ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->src_fmt.hw_fmt->uv_factor);
+
+ /* Propagate colorspace information to capture. */
+ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace;
+ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func;
+ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc;
+ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization;
+
+ /* scaling is not supported */
+ ctx->dst_fmt.pix.width = f->fmt.pix.width;
+ ctx->dst_fmt.pix.height = f->fmt.pix.height;
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+
+ ctx->fmt_changed = true;
+
+ return 0;
+}
+
+static int iep_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct iep_ctx *ctx = iep_file2ctx(file);
+ struct vb2_queue *vq;
+ int ret;
+
+ ret = iep_try_fmt_vid_cap(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ /* scaling is not supported */
+ f->fmt.pix.width = ctx->src_fmt.pix.width;
+ f->fmt.pix.height = ctx->src_fmt.pix.height;
+
+ ctx->dst_fmt.pix = f->fmt.pix;
+ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix);
+
+ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height);
+ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height,
+ ctx->dst_fmt.hw_fmt->uv_factor);
+
+ ctx->fmt_changed = true;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops iep_ioctl_ops = {
+ .vidioc_querycap = iep_querycap,
+
+ .vidioc_enum_framesizes = iep_enum_framesizes,
+
+ .vidioc_enum_fmt_vid_cap = iep_enum_fmt,
+ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap,
+
+ .vidioc_enum_fmt_vid_out = iep_enum_fmt,
+ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out,
+ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out,
+ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out,
+
+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+
+ .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+};
+
+static const struct video_device iep_video_device = {
+ .name = IEP_NAME,
+ .vfl_dir = VFL_DIR_M2M,
+ .fops = &iep_fops,
+ .ioctl_ops = &iep_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release_empty,
+ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
+};
+
+static int iep_parse_dt(struct rockchip_iep *iep)
+{
+ int ret = 0;
+
+ iep->resets = devm_reset_control_array_get(iep->dev, false, true);
+ if (IS_ERR(iep->resets)) {
+ dev_err(iep->dev, "getting resets failed %ld\n", PTR_ERR(iep->resets));
+ return PTR_ERR(iep->resets);
+ }
+
+ iep->axi_clk = devm_clk_get(iep->dev, "axi");
+ if (IS_ERR(iep->axi_clk)) {
+ dev_err(iep->dev, "failed to get aclk clock\n");
+ return PTR_ERR(iep->axi_clk);
+ }
+
+ iep->ahb_clk = devm_clk_get(iep->dev, "ahb");
+ if (IS_ERR(iep->ahb_clk)) {
+ dev_err(iep->dev, "failed to get hclk clock\n");
+ return PTR_ERR(iep->ahb_clk);
+ }
+
+ ret = clk_set_rate(iep->axi_clk, 300000000);
+
+ if (ret)
+ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n");
+
+ return ret;
+}
+
+static irqreturn_t iep_isr(int irq, void *prv)
+{
+ struct rockchip_iep *iep = prv;
+ struct iep_ctx *ctx;
+ u32 val;
+ enum vb2_buffer_state state = VB2_BUF_STATE_DONE;
+
+ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev);
+ if (!ctx) {
+ v4l2_err(&iep->v4l2_dev,
+ "Instance released before the end of transaction\n");
+ return IRQ_NONE;
+ }
+
+ /*
+ * The irq is shared with the iommu. If the runtime-pm state of the
+ * iep-device is disabled or the interrupt status doesn't match the
+ * expeceted mask the irq has been targeted to the iommu.
+ */
+
+ if (!pm_runtime_active(iep->dev) ||
+ !(iep_read(iep, IEP_INT) & IEP_INT_MASK))
+ return IRQ_NONE;
+
+ /* disable interrupt - will be re-enabled at next iep_device_run */
+ iep_mod(ctx->iep, IEP_INT,
+ IEP_INT_FRAME_DONE_EN, 0);
+
+ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR,
+ IEP_INT_FRAME_DONE_CLR);
+
+ /* wait for all status regs to show "idle" */
+ val = readl_poll_timeout(iep->regs + IEP_STATUS, val,
+ (val == 0), 100, IEP_TIMEOUT);
+
+ if (val) {
+ dev_err(iep->dev,
+ "Failed to wait for job to finish: status: %u\n", val);
+ state = VB2_BUF_STATE_ERROR;
+ ctx->job_abort = true;
+ }
+
+ iep_m2m_dst_bufs_done(ctx, state);
+
+ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0)
+ ? ctx->field_order_bff : !ctx->field_order_bff;
+
+ if (ctx->dst_buffs_done == 2 || ctx->job_abort) {
+ if (ctx->prev_src_buf)
+ v4l2_m2m_buf_done(ctx->prev_src_buf, state);
+
+ /* current src buff will be next prev */
+ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+
+ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx);
+ ctx->dst_buffs_done = 0;
+
+ } else {
+ iep_device_run(ctx);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int iep_probe(struct platform_device *pdev)
+{
+ struct rockchip_iep *iep;
+ struct video_device *vfd;
+ struct resource *res;
+ int ret = 0;
+ int irq;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL);
+ if (!iep)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, iep);
+ iep->dev = &pdev->dev;
+ iep->vfd = iep_video_device;
+
+ ret = iep_parse_dt(iep);
+ if (ret)
+ dev_err(&pdev->dev, "Unable to parse OF data\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ iep->regs = devm_ioremap_resource(iep->dev, res);
+ if (IS_ERR(iep->regs)) {
+ ret = PTR_ERR(iep->regs);
+ goto err_put_clk;
+ }
+
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret) {
+ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n");
+ goto err_put_clk;
+ }
+
+ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = irq;
+ goto err_put_clk;
+ }
+
+ /* IRQ is shared with IOMMU */
+ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED,
+ dev_name(iep->dev), iep);
+ if (ret < 0) {
+ dev_err(iep->dev, "failed to request irq\n");
+ goto err_put_clk;
+ }
+
+ mutex_init(&iep->mutex);
+
+ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev);
+ if (ret) {
+ dev_err(iep->dev, "Failed to register V4L2 device\n");
+
+ return ret;
+ }
+
+ vfd = &iep->vfd;
+ vfd->lock = &iep->mutex;
+ vfd->v4l2_dev = &iep->v4l2_dev;
+
+ snprintf(vfd->name, sizeof(vfd->name), "%s",
+ iep_video_device.name);
+
+ video_set_drvdata(vfd, iep);
+
+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
+ if (ret) {
+ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n");
+
+ goto err_v4l2;
+ }
+
+ v4l2_info(&iep->v4l2_dev,
+ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num);
+
+ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops);
+ if (IS_ERR(iep->m2m_dev)) {
+ v4l2_err(&iep->v4l2_dev,
+ "Failed to initialize V4L2 M2M device\n");
+ ret = PTR_ERR(iep->m2m_dev);
+
+ goto err_video;
+ }
+
+ /*
+ * needs to be done here, doing it any later, i.e. after
+ * the clocks are enabled, will make the device no more
+ * working (HW bug?)
+ */
+ reset_control_assert(iep->resets);
+ udelay(1);
+ reset_control_deassert(iep->resets);
+ udelay(1);
+
+ pm_runtime_set_autosuspend_delay(iep->dev, 100);
+ pm_runtime_use_autosuspend(iep->dev);
+ pm_runtime_enable(iep->dev);
+
+ return ret;
+
+err_video:
+ video_unregister_device(&iep->vfd);
+err_v4l2:
+ v4l2_device_unregister(&iep->v4l2_dev);
+err_put_clk:
+ pm_runtime_dont_use_autosuspend(iep->dev);
+ pm_runtime_disable(iep->dev);
+
+return ret;
+}
+
+static int iep_remove(struct platform_device *pdev)
+{
+ struct rockchip_iep *iep = platform_get_drvdata(pdev);
+
+ pm_runtime_dont_use_autosuspend(iep->dev);
+ pm_runtime_disable(iep->dev);
+
+ v4l2_m2m_release(iep->m2m_dev);
+ video_unregister_device(&iep->vfd);
+ v4l2_device_unregister(&iep->v4l2_dev);
+
+ return 0;
+}
+
+static int __maybe_unused iep_runtime_suspend(struct device *dev)
+{
+ struct rockchip_iep *iep = dev_get_drvdata(dev);
+
+ dev_info(iep->dev, "%s\n", __func__);
+
+ clk_disable_unprepare(iep->ahb_clk);
+ clk_disable_unprepare(iep->axi_clk);
+
+ return 0;
+}
+
+static int __maybe_unused iep_runtime_resume(struct device *dev)
+{
+ struct rockchip_iep *iep;
+ int ret = 0;
+
+ iep = dev_get_drvdata(dev);
+
+ dev_info(iep->dev, "%s\n", __func__);
+
+ ret = clk_prepare_enable(iep->axi_clk);
+ if (ret) {
+ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(iep->ahb_clk);
+ if (ret) {
+ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret);
+ goto err_disable_axi_clk;
+ }
+
+ return ret;
+
+err_disable_axi_clk:
+ clk_disable_unprepare(iep->axi_clk);
+ return ret;
+}
+
+static const struct dev_pm_ops iep_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(iep_runtime_suspend,
+ iep_runtime_resume, NULL)
+};
+
+static const struct of_device_id rockchip_iep_match[] = {
+ {
+ .compatible = "rockchip,rk3228-iep",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_iep_match);
+
+static struct platform_driver iep_pdrv = {
+ .probe = iep_probe,
+ .remove = iep_remove,
+ .driver = {
+ .name = IEP_NAME,
+ .pm = &iep_pm_ops,
+ .of_match_table = rockchip_iep_match,
+ },
+};
+
+module_platform_driver(iep_pdrv);
+
+MODULE_AUTHOR("Alex Bee <knaerzche@gmail.com>");
+MODULE_DESCRIPTION("Rockchip Image Enhancement Processor");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h
new file mode 100644
index 000000000000..6f525f23627b
--- /dev/null
+++ b/drivers/media/platform/rockchip/iep/iep.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Rockchip Image Enhancement Processor (IEP) driver
+ *
+ * Copyright (C) 2020 Alex Bee <knaerzche@gmail.com>
+ *
+ */
+#ifndef __IEP_H__
+#define __IEP_H__
+
+#include <linux/platform_device.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+
+#define IEP_NAME "rockchip-iep"
+
+/* Hardware limits */
+#define IEP_MIN_WIDTH 320U
+#define IEP_MAX_WIDTH 1920U
+
+#define IEP_MIN_HEIGHT 240U
+#define IEP_MAX_HEIGHT 1088U
+
+/* Hardware defaults */
+#define IEP_DEFAULT_WIDTH 320U
+#define IEP_DEFAULT_HEIGHT 240U
+
+//ns
+#define IEP_TIMEOUT 250000
+
+struct iep_fmt {
+ u32 fourcc;
+ u8 depth;
+ u8 uv_factor;
+ u8 color_swap;
+ u8 hw_format;
+};
+
+struct iep_frm_fmt {
+ struct iep_fmt *hw_fmt;
+ struct v4l2_pix_format pix;
+
+ unsigned int y_stride;
+ unsigned int uv_stride;
+};
+
+struct iep_ctx {
+ struct v4l2_fh fh;
+ struct rockchip_iep *iep;
+
+ struct iep_frm_fmt src_fmt;
+ struct iep_frm_fmt dst_fmt;
+
+ struct vb2_v4l2_buffer *prev_src_buf;
+ struct vb2_v4l2_buffer *dst0_buf;
+ struct vb2_v4l2_buffer *dst1_buf;
+
+ u32 dst_sequence;
+ u32 src_sequence;
+
+ /* bff = bottom field first */
+ bool field_order_bff;
+ bool field_bff;
+
+ unsigned int dst_buffs_done;
+
+ bool fmt_changed;
+ bool job_abort;
+};
+
+struct rockchip_iep {
+ struct v4l2_device v4l2_dev;
+ struct v4l2_m2m_dev *m2m_dev;
+ struct video_device vfd;
+
+ struct device *dev;
+
+ void __iomem *regs;
+
+ struct clk *axi_clk;
+ struct clk *ahb_clk;
+
+ struct reset_control *resets;
+
+ /* vfd lock */
+ struct mutex mutex;
+};
+
+static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value)
+{
+ writel(value, iep->regs + reg);
+};
+
+static inline u32 iep_read(struct rockchip_iep *iep, u32 reg)
+{
+ return readl(iep->regs + reg);
+};
+
+static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg,
+ u32 shadow_reg, u32 mask, u32 val)
+{
+ u32 temp = iep_read(iep, shadow_reg) & ~(mask);
+
+ temp |= val & mask;
+ iep_write(iep, reg, temp);
+};
+
+static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val)
+{
+ iep_shadow_mod(iep, reg, reg, mask, val);
+};
+
+#endif
From e9d4e43dc5a6fbcdff3be92e4ec40c7bb787a897 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 11 Oct 2020 14:48:44 +0200
Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK322x
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rk322x.dtsi | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index de5727e0bc94..a2012a44421d 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -781,6 +781,21 @@ rga: rga@20060000 {
power-domains = <&power RK3228_PD_VIO>;
};
+ iep: iep@20070000 {
+ compatible = "rockchip,rk3228-iep";
+ reg = <0x20070000 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_IEP_A>,
+ <&cru SRST_IEP_H>;
+ reset-names = "axi", "ahb";
+ power-domains = <&power RK3228_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
From e01ddeae4d23380545603195f72054a604ef45f4 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:22:38 +0200
Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328
while at that also add the iep mmu and powerdomain nodes
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 9a7a5c1adaa8..9fce8036df9b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -336,6 +336,12 @@ pd_vpu@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
};
+ pd_vio@RK3328_PD_VIO {
+ reg = <RK3328_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ pm_qos = <&qos_vio>;
+ };
};
reboot-mode {
@@ -740,6 +746,33 @@ vop_mmu: iommu@ff373f00 {
status = "disabled";
};
+ iep: iep@ff3a0000 {
+ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff3a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_IEP_A>,
+ <&cru SRST_IEP_H>;
+ reset-names = "axi", "ahb";
+ power-domains = <&power RK3328_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
+ iep_mmu: iommu@ff3a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff3a0800 0x0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3328_PD_VIO>;
+ #iommu-cells = <0>;
+ };
+
hdmi: hdmi@ff3c0000 {
compatible = "rockchip,rk3328-dw-hdmi";
reg = <0x0 0xff3c0000 0x0 0x20000>;
@@ -1046,6 +1079,11 @@ sdmmc_ext: dwmmc@ff5f0000 {
status = "disabled";
};
+ qos_vio: qos@ff760080 {
+ compatible = "syscon";
+ reg = <0x0 0xff760080 0x0 0x20>;
+ };
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
From d2753e5742ac64bd8969b69ad74b1eb95f61e885 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:43:12 +0200
Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 81b4b8714e3f..910cc877e23f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1302,6 +1302,21 @@ vdec_mmu: iommu@ff660480 {
#iommu-cells = <0>;
};
+ iep: iep@ff670000 {
+ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_A_IEP>,
+ <&cru SRST_H_IEP>;
+ reset-names = "axi", "ahb";
+ power-domains = <&power RK3399_PD_IEP>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff670800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
@@ -1309,8 +1324,8 @@ iep_mmu: iommu@ff670800 {
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3399_PD_IEP>;
#iommu-cells = <0>;
- status = "disabled";
};
rga: rga@ff680000 {
From ce22eb2d667873d807131360f33980e5c7459f00 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:51:04 +0200
Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3368
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3746f23dc3df..9403135881e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -714,6 +714,20 @@ i2s_8ch: i2s-8ch@ff898000 {
status = "disabled";
};
+ iep: iep@ff900000 {
+ compatible = "rockchip,rk3368-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_IEP_AXI>,
+ <&cru SRST_IEP_AHB>;
+ reset-names = "axi", "ahb";
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x100>;
@@ -722,7 +736,6 @@ iep_mmu: iommu@ff900800 {
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
};
isp_mmu: iommu@ff914000 {
From 8a9cf089ef1310522371ada40d1aa6ff6ba41da5 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Wed, 14 Oct 2020 20:53:56 +0200
Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm/boot/dts/rk3288.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 9757976d6e8a..d7aa05d7dee7 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1002,6 +1002,21 @@ crypto: cypto-controller@ff8a0000 {
status = "okay";
};
+ iep: iep@ff90000 {
+ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep";
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep";
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ clock-names = "axi", "ahb";
+ resets = <&cru SRST_IEP_AXI>,
+ <&cru SRST_IEP_AHB>;
+ reset-names = "axi", "ahb";
+ power-domains = <&power RK3288_PD_VIO>;
+ iommus = <&iep_mmu>;
+ };
+
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x40>;
@@ -1009,8 +1024,8 @@ iep_mmu: iommu@ff900800 {
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
};
isp_mmu: iommu@ff914000 {
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 6b2d9ce24..2297b43bf 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -770,7 +770,7 @@ vpu_mmu: iommu@20020800 {
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VPU>;
};
vdec: video-codec@20030000 {
@@ -801,7 +801,7 @@ vdec_mmu: iommu@20030480 {
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_RKVDEC>;
};
vop: vop@20050000 {
@@ -871,7 +871,7 @@ iep_mmu: iommu@20070800 {
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VIO>;
};
hdmi: hdmi@200a0000 {
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