235 lines
7.2 KiB
Diff
235 lines
7.2 KiB
Diff
From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Tue, 6 Jul 2021 14:21:52 +0000
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Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls
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---
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drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++++
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drivers/clk/rockchip/clk-rk3228.c | 14 ++--
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drivers/clk/rockchip/clk-rk3328.c | 7 +-
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drivers/clk/rockchip/clk.h | 3 +-
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4 files changed, 143 insertions(+), 11 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
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index 86718c54e..b16b3795f 100644
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--- a/drivers/clk/rockchip/clk-ddr.c
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+++ b/drivers/clk/rockchip/clk-ddr.c
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@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
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.get_parent = rockchip_ddrclk_get_parent,
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};
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+/* See v4.4/include/dt-bindings/display/rk_fb.h */
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+#define SCREEN_NULL 0
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+#define SCREEN_HDMI 6
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+
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+static inline int rk_drm_get_lcdc_type(void)
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+{
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+ return SCREEN_NULL;
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+}
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+
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+struct share_params {
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+ u32 hz;
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+ u32 lcdc_type;
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+ u32 vop;
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+ u32 vop_dclk_mode;
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+ u32 sr_idle_en;
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+ u32 addr_mcu_el3;
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+ /*
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+ * 1: need to wait flag1
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+ * 0: never wait flag1
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+ */
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+ u32 wait_flag1;
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+ /*
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+ * 1: need to wait flag1
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+ * 0: never wait flag1
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+ */
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+ u32 wait_flag0;
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+ u32 complt_hwirq;
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+ /* if need, add parameter after */
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+};
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+
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+struct rockchip_ddrclk_data {
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+ u32 inited_flag;
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+ void __iomem *share_memory;
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+};
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+
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+static struct rockchip_ddrclk_data ddr_data;
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+
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+static void rockchip_ddrclk_data_init(void)
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+{
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+ struct arm_smccc_res res;
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+
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+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
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+ 1, SHARE_PAGE_TYPE_DDR, 0,
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+ 0, 0, 0, 0, &res);
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+
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+ if (!res.a0) {
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+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
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+ ddr_data.inited_flag = 1;
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+ }
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+}
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+
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+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
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+ unsigned long drate,
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+ unsigned long prate)
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+{
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+ struct share_params *p;
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+ struct arm_smccc_res res;
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+
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+ if (!ddr_data.inited_flag)
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+ rockchip_ddrclk_data_init();
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+
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+ p = (struct share_params *)ddr_data.share_memory;
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+
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+ p->hz = drate;
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+ p->lcdc_type = rk_drm_get_lcdc_type();
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+ p->wait_flag1 = 1;
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+ p->wait_flag0 = 1;
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+
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+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
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+ SHARE_PAGE_TYPE_DDR, 0,
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+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
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+ 0, 0, 0, 0, &res);
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+
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+ if ((int)res.a1 == -6) {
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+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
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+ /* TODO: rockchip_dmcfreq_wait_complete(); */
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+ }
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+
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+ return res.a0;
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+}
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+
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+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
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+ (struct clk_hw *hw, unsigned long parent_rate)
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+{
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+ struct arm_smccc_res res;
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+
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+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
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+ SHARE_PAGE_TYPE_DDR, 0,
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+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
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+ 0, 0, 0, 0, &res);
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+ if (!res.a0)
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+ return res.a1;
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+ else
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+ return 0;
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+}
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+
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+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
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+ unsigned long rate,
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+ unsigned long *prate)
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+{
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+ struct share_params *p;
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+ struct arm_smccc_res res;
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+
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+ if (!ddr_data.inited_flag)
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+ rockchip_ddrclk_data_init();
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+
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+ p = (struct share_params *)ddr_data.share_memory;
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+
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+ p->hz = rate;
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+
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+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
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+ SHARE_PAGE_TYPE_DDR, 0,
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+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
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+ 0, 0, 0, 0, &res);
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+ if (!res.a0)
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+ return res.a1;
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+ else
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+ return 0;
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+}
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+
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+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
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+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
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+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
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+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
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+ .get_parent = rockchip_ddrclk_get_parent,
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+};
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+
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struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
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const char *const *parent_names,
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u8 num_parents, int mux_offset,
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@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
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case ROCKCHIP_DDRCLK_SIP:
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init.ops = &rockchip_ddrclk_sip_ops;
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break;
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+ case ROCKCHIP_DDRCLK_SIP_V2:
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+ init.ops = &rockchip_ddrclk_sip_ops_v2;
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+ break;
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default:
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pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
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kfree(ddrclk);
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 1f9176a5c..96393aa16 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
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/* PD_DDR */
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- COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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- RK2928_CLKGATE_CON(0), 2, GFLAGS),
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+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
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+ RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
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+ ROCKCHIP_DDRCLK_SIP_V2),
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GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(7), 1, GFLAGS),
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FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
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@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
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GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
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- GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
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- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
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+ GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
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+ GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
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GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
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GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
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@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = {
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"sclk_initmem_mbist",
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"aclk_initmem",
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"hclk_rom",
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- "pclk_ddrupctl",
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- "pclk_ddrmon",
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+ "pclk_ddr_upctl",
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+ "pclk_ddr_mon",
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"pclk_msch_noc",
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"pclk_stimer",
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"pclk_ddrphy",
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diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
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index cc18dbc18..5fdd611bb 100644
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--- a/drivers/clk/rockchip/clk-rk3328.c
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+++ b/drivers/clk/rockchip/clk-rk3328.c
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@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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RK3328_CLKGATE_CON(14), 1, GFLAGS),
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/* PD_DDR */
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- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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- RK3328_CLKGATE_CON(0), 4, GFLAGS),
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+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
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+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
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+ ROCKCHIP_DDRCLK_SIP_V2),
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+
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GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(18), 6, GFLAGS),
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GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
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diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
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index ae059b774..fdaa81ebb 100644
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--- a/drivers/clk/rockchip/clk.h
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+++ b/drivers/clk/rockchip/clk.h
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@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
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* DDRCLK flags, including method of setting the rate
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* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
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*/
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-#define ROCKCHIP_DDRCLK_SIP BIT(0)
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+#define ROCKCHIP_DDRCLK_SIP 0x01
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+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
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struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
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const char *const *parent_names,
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--
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2.25.1
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