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build/patch/kernel/archive/rockchip64-5.10/add-board-rk3328-orangepi-r1-plus-lts.patch

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From 37bcdd3295fc3ad2cb611b567aeef6ebfaf73987 Mon Sep 17 00:00:00 2001
From: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
Date: Tue, 15 Feb 2022 13:50:58 +1300
Subject: [PATCH] rk3328-orangepi-r1-plus-lts-kernel
Signed-off-by: schwar3kat <61094841+schwar3kat@users.noreply.github.com>
---
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 2997 +++++++++++++++++
2 files changed, 2998 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 000000000..9075c8f14
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,3079 @@
+/dts-v1/;
+
+/ {
+ ddr_timing: ddr_timing {
+ compatible = "rockchip,ddr-timing";
+ ddr3_speed_bin = <(21)>;
+ ddr4_speed_bin = <(12)>;
+ pd_idle = <0>;
+ sr_idle = <0>;
+ sr_mc_gate_idle = <0>;
+ srpd_lite_idle = <0>;
+ standby_idle = <0>;
+
+ auto_pd_dis_freq = <1066>;
+ auto_sr_dis_freq = <800>;
+ ddr3_dll_dis_freq = <300>;
+ ddr4_dll_dis_freq = <625>;
+ phy_dll_dis_freq = <400>;
+
+ ddr3_odt_dis_freq = <100>;
+ phy_ddr3_odt_dis_freq = <100>;
+ ddr3_drv = <(40)>;
+ ddr3_odt = <(120)>;
+ phy_ddr3_ca_drv = <(21)>;
+ phy_ddr3_ck_drv = <(18)>;
+ phy_ddr3_dq_drv = <(21)>;
+ phy_ddr3_odt = <(2)>;
+
+ lpddr3_odt_dis_freq = <666>;
+ phy_lpddr3_odt_dis_freq = <666>;
+ lpddr3_drv = <(40)>;
+ lpddr3_odt = <(240)>;
+ phy_lpddr3_ca_drv = <(22)>;
+ phy_lpddr3_ck_drv = <(19)>;
+ phy_lpddr3_dq_drv = <(22)>;
+ phy_lpddr3_odt = <(2)>;
+
+ lpddr4_odt_dis_freq = <800>;
+ phy_lpddr4_odt_dis_freq = <800>;
+ lpddr4_drv = <(60)>;
+ lpddr4_dq_odt = <(40)>;
+ lpddr4_ca_odt = <(40)>;
+ phy_lpddr4_ca_drv = <(20)>;
+ phy_lpddr4_ck_cs_drv = <(6)>;
+ phy_lpddr4_dq_drv = <(6)>;
+ phy_lpddr4_odt = <(16)>;
+
+ ddr4_odt_dis_freq = <666>;
+ phy_ddr4_odt_dis_freq = <666>;
+ ddr4_drv = <(34)>;
+ ddr4_odt = <(240)>;
+ phy_ddr4_ca_drv = <(22)>;
+ phy_ddr4_ck_drv = <(19)>;
+ phy_ddr4_dq_drv = <(22)>;
+ phy_ddr4_odt = <(2)>;
+
+
+ ddr3a1_ddr4a9_de-skew = <7>;
+ ddr3a0_ddr4a10_de-skew = <7>;
+ ddr3a3_ddr4a6_de-skew = <8>;
+ ddr3a2_ddr4a4_de-skew = <8>;
+ ddr3a5_ddr4a8_de-skew = <7>;
+ ddr3a4_ddr4a5_de-skew = <9>;
+ ddr3a7_ddr4a11_de-skew = <7>;
+ ddr3a6_ddr4a7_de-skew = <9>;
+ ddr3a9_ddr4a0_de-skew = <8>;
+ ddr3a8_ddr4a13_de-skew = <7>;
+ ddr3a11_ddr4a3_de-skew = <9>;
+ ddr3a10_ddr4cs0_de-skew = <7>;
+ ddr3a13_ddr4a2_de-skew = <8>;
+ ddr3a12_ddr4ba1_de-skew = <7>;
+ ddr3a15_ddr4odt0_de-skew = <7>;
+ ddr3a14_ddr4a1_de-skew = <8>;
+ ddr3ba1_ddr4a15_de-skew = <7>;
+ ddr3ba0_ddr4bg0_de-skew = <7>;
+ ddr3ras_ddr4cke_de-skew = <7>;
+ ddr3ba2_ddr4ba0_de-skew = <8>;
+ ddr3we_ddr4bg1_de-skew = <8>;
+ ddr3cas_ddr4a12_de-skew = <7>;
+ ddr3ckn_ddr4ckn_de-skew = <8>;
+ ddr3ckp_ddr4ckp_de-skew = <8>;
+ ddr3cke_ddr4a16_de-skew = <8>;
+ ddr3odt0_ddr4a14_de-skew = <7>;
+ ddr3cs0_ddr4act_de-skew = <8>;
+ ddr3reset_ddr4reset_de-skew = <7>;
+ ddr3cs1_ddr4cs1_de-skew = <7>;
+ ddr3odt1_ddr4odt1_de-skew = <7>;
+
+
+
+
+
+ cs0_dm0_rx_de-skew = <7>;
+ cs0_dm0_tx_de-skew = <8>;
+ cs0_dq0_rx_de-skew = <7>;
+ cs0_dq0_tx_de-skew = <8>;
+ cs0_dq1_rx_de-skew = <7>;
+ cs0_dq1_tx_de-skew = <8>;
+ cs0_dq2_rx_de-skew = <7>;
+ cs0_dq2_tx_de-skew = <8>;
+ cs0_dq3_rx_de-skew = <7>;
+ cs0_dq3_tx_de-skew = <8>;
+ cs0_dq4_rx_de-skew = <7>;
+ cs0_dq4_tx_de-skew = <8>;
+ cs0_dq5_rx_de-skew = <7>;
+ cs0_dq5_tx_de-skew = <8>;
+ cs0_dq6_rx_de-skew = <7>;
+ cs0_dq6_tx_de-skew = <8>;
+ cs0_dq7_rx_de-skew = <7>;
+ cs0_dq7_tx_de-skew = <8>;
+ cs0_dqs0_rx_de-skew = <6>;
+ cs0_dqs0p_tx_de-skew = <9>;
+ cs0_dqs0n_tx_de-skew = <9>;
+
+ cs0_dm1_rx_de-skew = <7>;
+ cs0_dm1_tx_de-skew = <7>;
+ cs0_dq8_rx_de-skew = <7>;
+ cs0_dq8_tx_de-skew = <8>;
+ cs0_dq9_rx_de-skew = <7>;
+ cs0_dq9_tx_de-skew = <7>;
+ cs0_dq10_rx_de-skew = <7>;
+ cs0_dq10_tx_de-skew = <8>;
+ cs0_dq11_rx_de-skew = <7>;
+ cs0_dq11_tx_de-skew = <7>;
+ cs0_dq12_rx_de-skew = <7>;
+ cs0_dq12_tx_de-skew = <8>;
+ cs0_dq13_rx_de-skew = <7>;
+ cs0_dq13_tx_de-skew = <7>;
+ cs0_dq14_rx_de-skew = <7>;
+ cs0_dq14_tx_de-skew = <8>;
+ cs0_dq15_rx_de-skew = <7>;
+ cs0_dq15_tx_de-skew = <7>;
+ cs0_dqs1_rx_de-skew = <7>;
+ cs0_dqs1p_tx_de-skew = <9>;
+ cs0_dqs1n_tx_de-skew = <9>;
+
+ cs0_dm2_rx_de-skew = <7>;
+ cs0_dm2_tx_de-skew = <8>;
+ cs0_dq16_rx_de-skew = <7>;
+ cs0_dq16_tx_de-skew = <8>;
+ cs0_dq17_rx_de-skew = <7>;
+ cs0_dq17_tx_de-skew = <8>;
+ cs0_dq18_rx_de-skew = <7>;
+ cs0_dq18_tx_de-skew = <8>;
+ cs0_dq19_rx_de-skew = <7>;
+ cs0_dq19_tx_de-skew = <8>;
+ cs0_dq20_rx_de-skew = <7>;
+ cs0_dq20_tx_de-skew = <8>;
+ cs0_dq21_rx_de-skew = <7>;
+ cs0_dq21_tx_de-skew = <8>;
+ cs0_dq22_rx_de-skew = <7>;
+ cs0_dq22_tx_de-skew = <8>;
+ cs0_dq23_rx_de-skew = <7>;
+ cs0_dq23_tx_de-skew = <8>;
+ cs0_dqs2_rx_de-skew = <6>;
+ cs0_dqs2p_tx_de-skew = <9>;
+ cs0_dqs2n_tx_de-skew = <9>;
+
+ cs0_dm3_rx_de-skew = <7>;
+ cs0_dm3_tx_de-skew = <7>;
+ cs0_dq24_rx_de-skew = <7>;
+ cs0_dq24_tx_de-skew = <8>;
+ cs0_dq25_rx_de-skew = <7>;
+ cs0_dq25_tx_de-skew = <7>;
+ cs0_dq26_rx_de-skew = <7>;
+ cs0_dq26_tx_de-skew = <7>;
+ cs0_dq27_rx_de-skew = <7>;
+ cs0_dq27_tx_de-skew = <7>;
+ cs0_dq28_rx_de-skew = <7>;
+ cs0_dq28_tx_de-skew = <7>;
+ cs0_dq29_rx_de-skew = <7>;
+ cs0_dq29_tx_de-skew = <7>;
+ cs0_dq30_rx_de-skew = <7>;
+ cs0_dq30_tx_de-skew = <7>;
+ cs0_dq31_rx_de-skew = <7>;
+ cs0_dq31_tx_de-skew = <7>;
+ cs0_dqs3_rx_de-skew = <7>;
+ cs0_dqs3p_tx_de-skew = <9>;
+ cs0_dqs3n_tx_de-skew = <9>;
+
+ cs1_dm0_rx_de-skew = <7>;
+ cs1_dm0_tx_de-skew = <8>;
+ cs1_dq0_rx_de-skew = <7>;
+ cs1_dq0_tx_de-skew = <8>;
+ cs1_dq1_rx_de-skew = <7>;
+ cs1_dq1_tx_de-skew = <8>;
+ cs1_dq2_rx_de-skew = <7>;
+ cs1_dq2_tx_de-skew = <8>;
+ cs1_dq3_rx_de-skew = <7>;
+ cs1_dq3_tx_de-skew = <8>;
+ cs1_dq4_rx_de-skew = <7>;
+ cs1_dq4_tx_de-skew = <8>;
+ cs1_dq5_rx_de-skew = <7>;
+ cs1_dq5_tx_de-skew = <8>;
+ cs1_dq6_rx_de-skew = <7>;
+ cs1_dq6_tx_de-skew = <8>;
+ cs1_dq7_rx_de-skew = <7>;
+ cs1_dq7_tx_de-skew = <8>;
+ cs1_dqs0_rx_de-skew = <6>;
+ cs1_dqs0p_tx_de-skew = <9>;
+ cs1_dqs0n_tx_de-skew = <9>;
+
+ cs1_dm1_rx_de-skew = <7>;
+ cs1_dm1_tx_de-skew = <7>;
+ cs1_dq8_rx_de-skew = <7>;
+ cs1_dq8_tx_de-skew = <8>;
+ cs1_dq9_rx_de-skew = <7>;
+ cs1_dq9_tx_de-skew = <7>;
+ cs1_dq10_rx_de-skew = <7>;
+ cs1_dq10_tx_de-skew = <8>;
+ cs1_dq11_rx_de-skew = <7>;
+ cs1_dq11_tx_de-skew = <7>;
+ cs1_dq12_rx_de-skew = <7>;
+ cs1_dq12_tx_de-skew = <8>;
+ cs1_dq13_rx_de-skew = <7>;
+ cs1_dq13_tx_de-skew = <7>;
+ cs1_dq14_rx_de-skew = <7>;
+ cs1_dq14_tx_de-skew = <8>;
+ cs1_dq15_rx_de-skew = <7>;
+ cs1_dq15_tx_de-skew = <7>;
+ cs1_dqs1_rx_de-skew = <7>;
+ cs1_dqs1p_tx_de-skew = <9>;
+ cs1_dqs1n_tx_de-skew = <9>;
+
+ cs1_dm2_rx_de-skew = <7>;
+ cs1_dm2_tx_de-skew = <8>;
+ cs1_dq16_rx_de-skew = <7>;
+ cs1_dq16_tx_de-skew = <8>;
+ cs1_dq17_rx_de-skew = <7>;
+ cs1_dq17_tx_de-skew = <8>;
+ cs1_dq18_rx_de-skew = <7>;
+ cs1_dq18_tx_de-skew = <8>;
+ cs1_dq19_rx_de-skew = <7>;
+ cs1_dq19_tx_de-skew = <8>;
+ cs1_dq20_rx_de-skew = <7>;
+ cs1_dq20_tx_de-skew = <8>;
+ cs1_dq21_rx_de-skew = <7>;
+ cs1_dq21_tx_de-skew = <8>;
+ cs1_dq22_rx_de-skew = <7>;
+ cs1_dq22_tx_de-skew = <8>;
+ cs1_dq23_rx_de-skew = <7>;
+ cs1_dq23_tx_de-skew = <8>;
+ cs1_dqs2_rx_de-skew = <6>;
+ cs1_dqs2p_tx_de-skew = <9>;
+ cs1_dqs2n_tx_de-skew = <9>;
+
+ cs1_dm3_rx_de-skew = <7>;
+ cs1_dm3_tx_de-skew = <7>;
+ cs1_dq24_rx_de-skew = <7>;
+ cs1_dq24_tx_de-skew = <8>;
+ cs1_dq25_rx_de-skew = <7>;
+ cs1_dq25_tx_de-skew = <7>;
+ cs1_dq26_rx_de-skew = <7>;
+ cs1_dq26_tx_de-skew = <7>;
+ cs1_dq27_rx_de-skew = <7>;
+ cs1_dq27_tx_de-skew = <7>;
+ cs1_dq28_rx_de-skew = <7>;
+ cs1_dq28_tx_de-skew = <7>;
+ cs1_dq29_rx_de-skew = <7>;
+ cs1_dq29_tx_de-skew = <7>;
+ cs1_dq30_rx_de-skew = <7>;
+ cs1_dq30_tx_de-skew = <7>;
+ cs1_dq31_rx_de-skew = <7>;
+ cs1_dq31_tx_de-skew = <7>;
+ cs1_dqs3_rx_de-skew = <7>;
+ cs1_dqs3p_tx_de-skew = <9>;
+ cs1_dqs3n_tx_de-skew = <9>;
+ };
+};
+
+/ {
+ compatible = "rockchip,rk3328";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&cru 6>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&cru 6>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&cru 6>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&cru 6>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <975000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
+
+ amba: bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dmac: dmac@ff1f0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff1f0000 0x0 0x4000>;
+ interrupts = <0 0 4>,
+ <0 1 4>;
+ arm,pl330-periph-burst;
+ clocks = <&cru 134>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+ };
+
+ analog_sound: analog-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "Analog";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <0 100 4>,
+ <0 101 4>,
+ <0 102 4>,
+ <0 103 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "HDMI";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ spdif_out: spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 8)>,
+ <1 14 ((((1 << (4)) - 1) << 8) | 8)>,
+ <1 11 ((((1 << (4)) - 1) << 8) | 8)>,
+ <1 10 ((((1 << (4)) - 1) << 8) | 8)>;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ i2s0: i2s@ff000000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff000000 0x0 0x1000>;
+ interrupts = <0 26 4>;
+ clocks = <&cru 41>, <&cru 311>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 11>, <&dmac 12>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s1: i2s@ff010000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff010000 0x0 0x1000>;
+ interrupts = <0 27 4>;
+ clocks = <&cru 42>, <&cru 312>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 14>, <&dmac 15>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s2: i2s@ff020000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff020000 0x0 0x1000>;
+ interrupts = <0 28 4>;
+ clocks = <&cru 43>, <&cru 313>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 0>, <&dmac 1>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif: spdif@ff030000 {
+ compatible = "rockchip,rk3328-spdif";
+ reg = <0x0 0xff030000 0x0 0x1000>;
+ interrupts = <0 29 4>;
+ clocks = <&cru 46>, <&cru 314>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 10>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm2_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm: pdm@ff040000 {
+ compatible = "rockchip,pdm";
+ reg = <0x0 0xff040000 0x0 0x1000>;
+ clocks = <&cru 61>, <&cru 338>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 16>;
+ dma-names = "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-1 = <&pdmm0_clk_sleep
+ &pdmm0_sdi0_sleep
+ &pdmm0_sdi1_sleep
+ &pdmm0_sdi2_sleep
+ &pdmm0_sdi3_sleep>;
+ status = "disabled";
+ };
+
+ grf: syscon@ff100000 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff100000 0x0 0x1000>;
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3328-io-voltage-domain";
+ status = "disabled";
+ };
+
+ grf_gpio: grf-gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ power: power-controller {
+ compatible = "rockchip,rk3328-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu@1 {
+ reg = <1>;
+ clocks = <&cru 135>;
+ };
+ pd_hevc@6 {
+ reg = <6>;
+ };
+ pd_video@5 {
+ reg = <5>;
+ clocks = <&cru 139>,
+ <&cru 322>,
+ <&cru 65>,
+ <&cru 66>;
+ };
+ pd_vpu@8 {
+ reg = <8>;
+ clocks = <&cru 143>, <&cru 326>;
+ };
+ };
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x5c8>;
+ mode-normal = <(0x5242C300 + 0)>;
+ mode-recovery = <(0x5242C300 + 3)>;
+ mode-bootloader = <(0x5242C300 + 9)>;
+ mode-loader = <(0x5242C300 + 1)>;
+ };
+ };
+
+ uart0: serial@ff110000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff110000 0x0 0x100>;
+ interrupts = <0 55 4>;
+ clocks = <&cru 38>, <&cru 210>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 2>, <&dmac 3>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff120000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff120000 0x0 0x100>;
+ interrupts = <0 56 4>;
+ clocks = <&cru 39>, <&cru 211>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 4>, <&dmac 5>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff130000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff130000 0x0 0x100>;
+ interrupts = <0 57 4>;
+ clocks = <&cru 40>, <&cru 212>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 6>, <&dmac 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@ff150000 {
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff150000 0x0 0x1000>;
+ interrupts = <0 36 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru 55>, <&cru 205>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ff160000 {
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ interrupts = <0 37 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru 56>, <&cru 206>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ff170000 {
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ interrupts = <0 38 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru 57>, <&cru 207>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ff180000 {
+ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff180000 0x0 0x1000>;
+ interrupts = <0 39 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru 58>, <&cru 208>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ status = "disabled";
+ };
+
+ spi0: spi@ff190000 {
+ compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff190000 0x0 0x1000>;
+ interrupts = <0 49 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru 32>, <&cru 209>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 8>, <&dmac 9>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@ff1a0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xff1a0000 0x0 0x100>;
+ interrupts = <0 40 4>;
+ clocks = <&cru 236>;
+ };
+
+ pwm0: pwm@ff1b0000 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0000 0x0 0x10>;
+ clocks = <&cru 60>, <&cru 214>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff1b0010 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0010 0x0 0x10>;
+ clocks = <&cru 60>, <&cru 214>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff1b0020 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0020 0x0 0x10>;
+ clocks = <&cru 60>, <&cru 214>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff1b0030 {
+ compatible = "rockchip,rk3328-pwm";
+ reg = <0x0 0xff1b0030 0x0 0x10>;
+ interrupts = <0 50 4>;
+ clocks = <&cru 60>, <&cru 214>;
+ clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmir_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>;
+ polling-delay = <1000>;
+ sustainable-power = <1000>;
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ target: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ soc_crit: soc-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 (~0) (~0)>,
+ <&cpu1 (~0) (~0)>,
+ <&cpu2 (~0) (~0)>,
+ <&cpu3 (~0) (~0)>;
+ contribution = <4096>;
+ };
+ };
+ };
+
+ };
+
+ tsadc: tsadc@ff250000 {
+ compatible = "rockchip,rk3328-tsadc";
+ reg = <0x0 0xff250000 0x0 0x100>;
+ interrupts = <0 58 4>;
+ assigned-clocks = <&cru 36>;
+ assigned-clock-rates = <50000>;
+ clocks = <&cru 36>, <&cru 213>;
+ clock-names = "tsadc", "apb_pclk";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_pin>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_pin>;
+ resets = <&cru 66>;
+ reset-names = "tsadc-apb";
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <100000>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ efuse: efuse@ff260000 {
+ compatible = "rockchip,rk3328-efuse";
+ reg = <0x0 0xff260000 0x0 0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru 62>;
+ clock-names = "pclk_efuse";
+ rockchip,efuse-size = <0x20>;
+
+
+ efuse_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ logic_leakage: logic-leakage@19 {
+ reg = <0x19 0x1>;
+ };
+ efuse_cpu_version: cpu-version@1a {
+ reg = <0x1a 0x1>;
+ bits = <3 3>;
+ };
+ };
+
+ saradc: adc@ff280000 {
+ compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
+ reg = <0x0 0xff280000 0x0 0x100>;
+ interrupts = <0 80 4>;
+ #io-channel-cells = <1>;
+ clocks = <&cru 37>, <&cru 234>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru 86>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ gpu: gpu@ff300000 {
+ compatible = "rockchip,rk3328-mali", "arm,mali-450";
+ reg = <0x0 0xff300000 0x0 0x30000>;
+ interrupts = <0 90 4>,
+ <0 87 4>,
+ <0 93 4>,
+ <0 88 4>,
+ <0 89 4>,
+ <0 91 4>,
+ <0 92 4>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = <&cru 135>, <&cru 135>;
+ clock-names = "bus", "core";
+ power-domains = <&power 1>;
+ resets = <&cru 102>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ h265e_mmu: iommu@ff330200 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff330200 0 0x100>;
+ interrupts = <0 96 4>;
+ interrupt-names = "h265e_mmu";
+ clocks = <&cru 147>, <&cru 221>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vepu_mmu: iommu@ff340800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff340800 0x0 0x40>;
+ interrupts = <0 98 4>;
+ interrupt-names = "vepu_mmu";
+ clocks = <&cru 143>, <&cru 326>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu: video-codec@ff350000 {
+ compatible = "rockchip,rk3328-vpu";
+ reg = <0x0 0xff350000 0x0 0x800>;
+ interrupts = <0 9 4>;
+ interrupt-names = "vdpu";
+ clocks = <&cru 143>, <&cru 326>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power 8>;
+ };
+
+ vpu_mmu: iommu@ff350800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff350800 0x0 0x40>;
+ interrupts = <0 11 4>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru 143>, <&cru 326>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power 8>;
+ };
+
+ rkvdec_mmu: iommu@ff360480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
+ interrupts = <0 74 4>;
+ interrupt-names = "rkvdec_mmu";
+ clocks = <&cru 139>, <&cru 322>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power 5>;
+ status = "disabled";
+ };
+
+ vop: vop@ff370000 {
+ compatible = "rockchip,rk3328-vop";
+ reg = <0x0 0xff370000 0x0 0x3efc>;
+ interrupts = <0 32 4>;
+ clocks = <&cru 145>, <&cru 120>, <&cru 315>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru 133>, <&cru 134>, <&cru 135>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@ff373f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff373f00 0x0 0x100>;
+ interrupts = <0 32 4>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru 145>, <&cru 315>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmi: hdmi@ff3c0000 {
+ compatible = "rockchip,rk3328-dw-hdmi";
+ reg = <0x0 0xff3c0000 0x0 0x20000>;
+ reg-io-width = <4>;
+ interrupts = <0 35 4>,
+ <0 71 4>;
+ clocks = <&cru 231>,
+ <&cru 70>,
+ <&cru 30>;
+ clock-names = "iahb",
+ "isfr",
+ "cec";
+ phys = <&hdmiphy>;
+ phy-names = "hdmi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+ hdmi_in: port {
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+ };
+ };
+
+ codec: codec@ff410000 {
+ compatible = "rockchip,rk3328-codec";
+ reg = <0x0 0xff410000 0x0 0x1000>;
+ clocks = <&cru 235>, <&cru 42>;
+ clock-names = "pclk", "mclk";
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmiphy: phy@ff430000 {
+ compatible = "rockchip,rk3328-hdmi-phy";
+ reg = <0x0 0xff430000 0x0 0x10000>;
+ interrupts = <0 83 4>;
+ clocks = <&cru 228>, <&xin24m>, <&cru 121>;
+ clock-names = "sysclk", "refoclk", "refpclk";
+ clock-output-names = "hdmi_phy";
+ #clock-cells = <0>;
+ nvmem-cells = <&efuse_cpu_version>;
+ nvmem-cell-names = "cpu-version";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ cru: clock-controller@ff440000 {
+ compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks =
+
+
+
+
+
+
+ <&cru 120>, <&cru 61>,
+ <&cru 30>, <&cru 38>,
+ <&cru 39>, <&cru 40>,
+ <&cru 136>, <&cru 137>,
+ <&cru 142>, <&cru 133>,
+ <&cru 131>, <&cru 138>,
+ <&cru 140>, <&cru 141>,
+ <&cru 65>, <&cru 66>,
+ <&cru 68>, <&cru 67>,
+ <&cru 34>, <&cru 92>,
+ <&cru 53>, <&cru 6>,
+ <&cru 4>, <&cru 3>,
+ <&cru 136>, <&cru 328>,
+ <&cru 216>, <&cru 137>,
+ <&cru 308>, <&cru 230>,
+ <&cru 135>,
+ <&cru 30>;
+ assigned-clock-parents =
+ <&cru 122>, <&cru 1>,
+ <&cru 4>, <&xin24m>,
+ <&xin24m>, <&xin24m>;
+ assigned-clock-rates =
+ <0>, <61440000>,
+ <0>, <24000000>,
+ <24000000>, <24000000>,
+ <15000000>, <15000000>,
+ <100000000>, <100000000>,
+ <100000000>, <100000000>,
+ <50000000>, <100000000>,
+ <100000000>, <100000000>,
+ <50000000>, <50000000>,
+ <50000000>, <50000000>,
+ <24000000>, <600000000>,
+ <491520000>, <1200000000>,
+ <150000000>, <75000000>,
+ <75000000>, <150000000>,
+ <75000000>, <75000000>,
+ <500000000>,
+ <32768>;
+ };
+
+ usb2phy_grf: syscon@ff450000 {
+ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@100 {
+ compatible = "rockchip,rk3328-usb2phy";
+ reg = <0x100 0x10>;
+ clocks = <&xin24m>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ assigned-clocks = <&cru 123>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <0 59 4>,
+ <0 60 4>,
+ <0 61 4>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <0 62 4>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+ };
+
+ usb3phy_grf: syscon@ff460000 {
+ compatible = "rockchip,usb3phy-grf", "syscon";
+ reg = <0x0 0xff460000 0x0 0x1000>;
+ };
+
+ u3phy: usb3-phy@ff470000 {
+ compatible = "rockchip,rk3328-u3phy";
+ reg = <0x0 0xff470000 0x0 0x0>;
+ rockchip,u3phygrf = <&usb3phy_grf>;
+ rockchip,grf = <&grf>;
+ interrupts = <0 77 4>;
+ interrupt-names = "linestate";
+ clocks = <&cru 224>, <&cru 225>;
+ clock-names = "u3phy-otg", "u3phy-pipe";
+ resets = <&cru 125>,
+ <&cru 126>,
+ <&cru 127>,
+ <&cru 124>,
+ <&cru 158>,
+ <&cru 159>;
+ reset-names = "u3phy-u2-por", "u3phy-u3-por",
+ "u3phy-pipe-mac", "u3phy-utmi-mac",
+ "u3phy-utmi-apb", "u3phy-pipe-apb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u3phy_utmi: utmi@ff470000 {
+ reg = <0x0 0xff470000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy_pipe: pipe@ff478000 {
+ reg = <0x0 0xff478000 0x0 0x8000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ sdmmc: mmc@ff500000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff500000 0x0 0x4000>;
+ interrupts = <0 12 4>;
+ clocks = <&cru 317>, <&cru 33>,
+ <&cru 74>, <&cru 78>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru 109>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdio: mmc@ff510000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff510000 0x0 0x4000>;
+ interrupts = <0 13 4>;
+ clocks = <&cru 318>, <&cru 34>,
+ <&cru 75>, <&cru 79>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru 110>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ emmc: mmc@ff520000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff520000 0x0 0x4000>;
+ interrupts = <0 14 4>;
+ clocks = <&cru 319>, <&cru 35>,
+ <&cru 76>, <&cru 80>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru 111>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ gmac2io: ethernet@ff540000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff540000 0x0 0x10000>;
+ interrupts = <0 24 4>;
+ interrupt-names = "macirq";
+ clocks = <&cru 100>, <&cru 87>,
+ <&cru 88>, <&cru 90>,
+ <&cru 89>, <&cru 150>,
+ <&cru 223>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru 99>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,txpbl = <0x4>;
+ status = "disabled";
+ };
+
+ gmac2phy: ethernet@ff550000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff550000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <0 21 4>;
+ interrupt-names = "macirq";
+ clocks = <&cru 84>, <&cru 83>,
+ <&cru 83>, <&cru 85>,
+ <&cru 149>, <&cru 222>,
+ <&cru 86>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_macphy";
+ resets = <&cru 98>, <&cru 100>;
+ reset-names = "stmmaceth", "mac-phy";
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
+ snps,txpbl = <0x4>;
+ clock_in_out = "output";
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clocks = <&cru 86>;
+ resets = <&cru 100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
+ phy-is-integrated;
+ };
+ };
+ };
+
+ usb20_otg: usb@ff580000 {
+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <0 23 4>;
+ clocks = <&cru 333>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb@ff5c0000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff5c0000 0x0 0x10000>;
+ interrupts = <0 16 4>;
+ clocks = <&cru 334>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff5d0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff5d0000 0x0 0x10000>;
+ interrupts = <0 17 4>;
+ clocks = <&cru 334>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <0 4 4>;
+ clocks = <&cru 320>, <&cru 31>,
+ <&cru 77>, <&cru 81>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru 104>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ usbdrd3: usb@ff600000 {
+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru 96>, <&cru 97>,
+ <&cru 132>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ resets = <&cru 120>;
+ reset-names = "usb3-otg";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: dwc3@ff600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <0 67 4>;
+ clocks = <&cru 96>, <&cru 132>,
+ <&cru 97>;
+ clock-names = "ref", "bus_early", "suspend";
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@ff811000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xff811000 0 0x1000>,
+ <0x0 0xff812000 0 0x2000>,
+ <0x0 0xff814000 0 0x2000>,
+ <0x0 0xff816000 0 0x2000>;
+ interrupts = <1 9
+ ((((1 << (4)) - 1) << 8) | 4)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3328-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio0@ff210000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff210000 0x0 0x100>;
+ interrupts = <0 51 4>;
+ clocks = <&cru 200>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@ff220000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff220000 0x0 0x100>;
+ interrupts = <0 52 4>;
+ clocks = <&cru 201>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@ff230000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff230000 0x0 0x100>;
+ interrupts = <0 53 4>;
+ clocks = <&cru 202>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@ff240000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff240000 0x0 0x100>;
+ interrupts = <0 54 4>;
+ clocks = <&cru 203>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_2ma: pcfg-pull-none-2ma {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pcfg_pull_up_4ma: pcfg-pull-up-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_none_4ma: pcfg-pull-none-4ma {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ pcfg_input: pcfg-input {
+ input-enable;
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <2 24 1 &pcfg_pull_none>,
+ <2 25 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 4 2 &pcfg_pull_none>,
+ <2 5 2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 13 1 &pcfg_pull_none>,
+ <2 14 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 5 2 &pcfg_pull_none>,
+ <0 6 2 &pcfg_pull_none>;
+ };
+ i2c3_pins: i2c3-pins {
+ rockchip,pins =
+ <0 5 0 &pcfg_pull_none>,
+ <0 6 0 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_i2c {
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <0 5 1 &pcfg_pull_none>,
+ <0 6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pdm-0 {
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins = <2 18 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_fsync: pdmm0-fsync {
+ rockchip,pins = <2 23 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins = <2 19 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins = <2 20 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins = <2 21 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins = <2 22 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_clk_sleep: pdmm0-clk-sleep {
+ rockchip,pins =
+ <2 18 0 &pcfg_input_high>;
+ };
+
+ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
+ rockchip,pins =
+ <2 19 0 &pcfg_input_high>;
+ };
+
+ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
+ rockchip,pins =
+ <2 20 0 &pcfg_input_high>;
+ };
+
+ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
+ rockchip,pins =
+ <2 21 0 &pcfg_input_high>;
+ };
+
+ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
+ rockchip,pins =
+ <2 22 0 &pcfg_input_high>;
+ };
+
+ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
+ rockchip,pins =
+ <2 23 0 &pcfg_input_high>;
+ };
+ };
+
+ tsadc {
+ otp_pin: otp-pin {
+ rockchip,pins = <2 13 0 &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <2 13 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <1 9 1 &pcfg_pull_none>,
+ <1 8 1 &pcfg_pull_up>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <1 11 1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <1 10 1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_pin: uart0-rts-pin {
+ rockchip,pins = <1 10 0 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <3 4 4 &pcfg_pull_none>,
+ <3 6 4 &pcfg_pull_up>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <3 7 4 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <3 5 4 &pcfg_pull_none>;
+ };
+
+ uart1_rts_pin: uart1-rts-pin {
+ rockchip,pins = <3 5 0 &pcfg_pull_none>;
+ };
+ };
+
+ uart2-0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <1 0 2 &pcfg_pull_none>,
+ <1 1 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart2-1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <2 0 1 &pcfg_pull_none>,
+ <2 1 1 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-0 {
+ spi0m0_clk: spi0m0-clk {
+ rockchip,pins = <2 8 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins = <2 11 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_tx: spi0m0-tx {
+ rockchip,pins = <2 9 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_rx: spi0m0-rx {
+ rockchip,pins = <2 10 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins = <2 12 1 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-1 {
+ spi0m1_clk: spi0m1-clk {
+ rockchip,pins = <3 23 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins = <3 26 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_tx: spi0m1-tx {
+ rockchip,pins = <3 25 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_rx: spi0m1-rx {
+ rockchip,pins = <3 24 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs1: spi0m1-cs1 {
+ rockchip,pins = <3 27 2 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-2 {
+ spi0m2_clk: spi0m2-clk {
+ rockchip,pins = <3 0 4 &pcfg_pull_up>;
+ };
+
+ spi0m2_cs0: spi0m2-cs0 {
+ rockchip,pins = <3 8 3 &pcfg_pull_up>;
+ };
+
+ spi0m2_tx: spi0m2-tx {
+ rockchip,pins = <3 1 4 &pcfg_pull_up>;
+ };
+
+ spi0m2_rx: spi0m2-rx {
+ rockchip,pins = <3 2 4 &pcfg_pull_up>;
+ };
+ };
+
+ i2s1 {
+ i2s1_mclk: i2s1-mclk {
+ rockchip,pins = <2 15 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sclk: i2s1-sclk {
+ rockchip,pins = <2 18 1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrckrx: i2s1-lrckrx {
+ rockchip,pins = <2 16 1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrcktx: i2s1-lrcktx {
+ rockchip,pins = <2 17 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdi: i2s1-sdi {
+ rockchip,pins = <2 19 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdo: i2s1-sdo {
+ rockchip,pins = <2 23 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio1: i2s1-sdio1 {
+ rockchip,pins = <2 20 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio2: i2s1-sdio2 {
+ rockchip,pins = <2 21 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio3: i2s1-sdio3 {
+ rockchip,pins = <2 22 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sleep: i2s1-sleep {
+ rockchip,pins =
+ <2 15 0 &pcfg_input_high>,
+ <2 16 0 &pcfg_input_high>,
+ <2 17 0 &pcfg_input_high>,
+ <2 18 0 &pcfg_input_high>,
+ <2 19 0 &pcfg_input_high>,
+ <2 20 0 &pcfg_input_high>,
+ <2 21 0 &pcfg_input_high>,
+ <2 22 0 &pcfg_input_high>,
+ <2 23 0 &pcfg_input_high>;
+ };
+ };
+
+ i2s2-0 {
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins = <1 21 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins = <1 22 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrckrx: i2s2m0-lrckrx {
+ rockchip,pins = <1 26 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrcktx: i2s2m0-lrcktx {
+ rockchip,pins = <1 23 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins = <1 24 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins = <1 25 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sleep: i2s2m0-sleep {
+ rockchip,pins =
+ <1 21 0 &pcfg_input_high>,
+ <1 22 0 &pcfg_input_high>,
+ <1 26 0 &pcfg_input_high>,
+ <1 23 0 &pcfg_input_high>,
+ <1 24 0 &pcfg_input_high>,
+ <1 25 0 &pcfg_input_high>;
+ };
+ };
+
+ i2s2-1 {
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins = <1 21 1 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins = <3 0 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrckrx: i2sm1-lrckrx {
+ rockchip,pins = <3 8 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrcktx: i2s2m1-lrcktx {
+ rockchip,pins = <3 8 4 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins = <3 2 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins = <3 1 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sleep: i2s2m1-sleep {
+ rockchip,pins =
+ <1 21 0 &pcfg_input_high>,
+ <3 0 0 &pcfg_input_high>,
+ <3 8 0 &pcfg_input_high>,
+ <3 2 0 &pcfg_input_high>,
+ <3 1 0 &pcfg_input_high>;
+ };
+ };
+
+ spdif-0 {
+ spdifm0_tx: spdifm0-tx {
+ rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-1 {
+ spdifm1_tx: spdifm1-tx {
+ rockchip,pins = <2 17 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-2 {
+ spdifm2_tx: spdifm2-tx {
+ rockchip,pins = <0 2 2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0-0 {
+ sdmmc0m0_pwren: sdmmc0m0-pwren {
+ rockchip,pins = <2 7 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m0_pin: sdmmc0m0-pin {
+ rockchip,pins = <2 7 0 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0-1 {
+ sdmmc0m1_pwren: sdmmc0m1-pwren {
+ rockchip,pins = <0 30 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m1_pin: sdmmc0m1-pin {
+ rockchip,pins = <0 30 0 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 6 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 4 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_wrprt: sdmmc0-wrprt {
+ rockchip,pins = <1 7 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus1: sdmmc0-bus1 {
+ rockchip,pins = <1 0 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins = <1 0 1 &pcfg_pull_up_8ma>,
+ <1 1 1 &pcfg_pull_up_8ma>,
+ <1 2 1 &pcfg_pull_up_8ma>,
+ <1 3 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_pins: sdmmc0-pins {
+ rockchip,pins =
+ <1 6 0 &pcfg_pull_up_4ma>,
+ <1 4 0 &pcfg_pull_up_4ma>,
+ <1 5 0 &pcfg_pull_up_4ma>,
+ <1 7 0 &pcfg_pull_up_4ma>,
+ <1 3 0 &pcfg_pull_up_4ma>,
+ <1 2 0 &pcfg_pull_up_4ma>,
+ <1 1 0 &pcfg_pull_up_4ma>,
+ <1 0 0 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 2 3 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 0 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_wrprt: sdmmc0ext-wrprt {
+ rockchip,pins = <3 3 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_dectn: sdmmc0ext-dectn {
+ rockchip,pins = <3 1 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus1: sdmmc0ext-bus1 {
+ rockchip,pins = <3 4 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 4 3 &pcfg_pull_up_4ma>,
+ <3 5 3 &pcfg_pull_up_4ma>,
+ <3 6 3 &pcfg_pull_up_4ma>,
+ <3 7 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_pins: sdmmc0ext-pins {
+ rockchip,pins =
+ <3 0 0 &pcfg_pull_up_4ma>,
+ <3 1 0 &pcfg_pull_up_4ma>,
+ <3 2 0 &pcfg_pull_up_4ma>,
+ <3 3 0 &pcfg_pull_up_4ma>,
+ <3 4 0 &pcfg_pull_up_4ma>,
+ <3 5 0 &pcfg_pull_up_4ma>,
+ <3 6 0 &pcfg_pull_up_4ma>,
+ <3 7 0 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc1 {
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins = <1 12 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins = <1 13 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins = <1 18 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_wrprt: sdmmc1-wrprt {
+ rockchip,pins = <1 20 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_dectn: sdmmc1-dectn {
+ rockchip,pins = <1 19 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus1: sdmmc1-bus1 {
+ rockchip,pins = <1 14 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins = <1 14 1 &pcfg_pull_up_8ma>,
+ <1 15 1 &pcfg_pull_up_8ma>,
+ <1 16 1 &pcfg_pull_up_8ma>,
+ <1 17 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_pins: sdmmc1-pins {
+ rockchip,pins =
+ <1 12 0 &pcfg_pull_up_4ma>,
+ <1 13 0 &pcfg_pull_up_4ma>,
+ <1 14 0 &pcfg_pull_up_4ma>,
+ <1 15 0 &pcfg_pull_up_4ma>,
+ <1 16 0 &pcfg_pull_up_4ma>,
+ <1 17 0 &pcfg_pull_up_4ma>,
+ <1 18 0 &pcfg_pull_up_4ma>,
+ <1 19 0 &pcfg_pull_up_4ma>,
+ <1 20 0 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <3 21 2 &pcfg_pull_none_12ma>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <3 19 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_pwren: emmc-pwren {
+ rockchip,pins = <3 22 2 &pcfg_pull_none>;
+ };
+
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins = <3 20 2 &pcfg_pull_none>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins = <0 7 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins =
+ <0 7 2 &pcfg_pull_up_12ma>,
+ <2 28 2 &pcfg_pull_up_12ma>,
+ <2 29 2 &pcfg_pull_up_12ma>,
+ <2 30 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ <0 7 2 &pcfg_pull_up_12ma>,
+ <2 28 2 &pcfg_pull_up_12ma>,
+ <2 29 2 &pcfg_pull_up_12ma>,
+ <2 30 2 &pcfg_pull_up_12ma>,
+ <2 31 2 &pcfg_pull_up_12ma>,
+ <3 16 2 &pcfg_pull_up_12ma>,
+ <3 17 2 &pcfg_pull_up_12ma>,
+ <3 18 2 &pcfg_pull_up_12ma>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <2 4 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <2 5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <2 6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwmir {
+ pwmir_pin: pwmir-pin {
+ rockchip,pins = <2 2 1 &pcfg_pull_none>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+
+ <1 12 2 &pcfg_pull_none_8ma>,
+
+ <1 13 2 &pcfg_pull_none_4ma>,
+
+ <1 19 2 &pcfg_pull_none_4ma>,
+
+ <1 25 2 &pcfg_pull_none_8ma>,
+
+ <1 21 2 &pcfg_pull_none_4ma>,
+
+ <1 22 2 &pcfg_pull_none_4ma>,
+
+ <1 23 2 &pcfg_pull_none_4ma>,
+
+ <1 10 2 &pcfg_pull_none_4ma>,
+
+ <1 11 2 &pcfg_pull_none_4ma>,
+
+ <1 8 2 &pcfg_pull_none_8ma>,
+
+ <1 9 2 &pcfg_pull_none_8ma>,
+
+ <1 14 2 &pcfg_pull_none_4ma>,
+
+ <1 15 2 &pcfg_pull_none_4ma>,
+
+ <1 16 2 &pcfg_pull_none_8ma>,
+
+ <1 17 2 &pcfg_pull_none_8ma>,
+
+
+ <0 8 1 &pcfg_pull_none_8ma>,
+
+ <0 12 1 &pcfg_pull_none_8ma>,
+
+ <0 24 1 &pcfg_pull_none_4ma>,
+
+ <0 16 1 &pcfg_pull_none_8ma>,
+
+ <0 17 1 &pcfg_pull_none_8ma>,
+
+ <0 23 1 &pcfg_pull_none_8ma>,
+
+ <0 22 1 &pcfg_pull_none_8ma>;
+ };
+
+ rmiim1_pins: rmiim1-pins {
+ rockchip,pins =
+
+ <1 19 2 &pcfg_pull_none_2ma>,
+
+ <1 25 2 &pcfg_pull_none_12ma>,
+
+ <1 21 2 &pcfg_pull_none_2ma>,
+
+ <1 24 2 &pcfg_pull_none_2ma>,
+
+ <1 22 2 &pcfg_pull_none_2ma>,
+
+ <1 23 2 &pcfg_pull_none_2ma>,
+
+ <1 10 2 &pcfg_pull_none_2ma>,
+
+ <1 11 2 &pcfg_pull_none_2ma>,
+
+ <1 8 2 &pcfg_pull_none_12ma>,
+
+ <1 9 2 &pcfg_pull_none_12ma>,
+
+
+ <0 11 1 &pcfg_pull_none>,
+
+ <0 12 1 &pcfg_pull_none>,
+
+ <0 24 1 &pcfg_pull_none>,
+
+ <0 19 1 &pcfg_pull_none>,
+
+ <0 16 1 &pcfg_pull_none>,
+
+ <0 17 1 &pcfg_pull_none>;
+ };
+ };
+
+ gmac2phy {
+ fephyled_speed10: fephyled-speed10 {
+ rockchip,pins = <0 30 1 &pcfg_pull_none>;
+ };
+
+ fephyled_duplex: fephyled-duplex {
+ rockchip,pins = <0 30 2 &pcfg_pull_none>;
+ };
+
+ fephyled_rxm1: fephyled-rxm1 {
+ rockchip,pins = <2 25 2 &pcfg_pull_none>;
+ };
+
+ fephyled_txm1: fephyled-txm1 {
+ rockchip,pins = <2 25 3 &pcfg_pull_none>;
+ };
+
+ fephyled_linkm1: fephyled-linkm1 {
+ rockchip,pins = <2 24 2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc_pin {
+ tsadc_int: tsadc-int {
+ rockchip,pins = <2 13 2 &pcfg_pull_none>;
+ };
+ tsadc_pin: tsadc-pin {
+ rockchip,pins = <2 13 0 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_pin {
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <0 3 1 &pcfg_pull_none>;
+ };
+
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins = <0 4 1 &pcfg_pull_down>;
+ };
+ };
+
+ cif-0 {
+ dvp_d2d9_m0:dvp-d2d9-m0 {
+ rockchip,pins =
+
+ <3 4 2 &pcfg_pull_none>,
+
+ <3 5 2 &pcfg_pull_none>,
+
+ <3 6 2 &pcfg_pull_none>,
+
+ <3 7 2 &pcfg_pull_none>,
+
+ <3 8 2 &pcfg_pull_none>,
+
+ <3 9 2 &pcfg_pull_none>,
+
+ <3 10 2 &pcfg_pull_none>,
+
+ <3 11 2 &pcfg_pull_none>,
+
+ <3 1 2 &pcfg_pull_none>,
+
+ <3 0 2 &pcfg_pull_none>,
+
+ <3 3 2 &pcfg_pull_none>,
+
+ <3 2 2 &pcfg_pull_none>;
+ };
+ };
+
+ cif-1 {
+ dvp_d2d9_m1:dvp-d2d9-m1 {
+ rockchip,pins =
+
+ <3 4 2 &pcfg_pull_none>,
+
+ <3 5 2 &pcfg_pull_none>,
+
+ <3 6 2 &pcfg_pull_none>,
+
+ <3 7 2 &pcfg_pull_none>,
+
+ <3 8 2 &pcfg_pull_none>,
+
+ <2 16 4 &pcfg_pull_none>,
+
+ <2 17 4 &pcfg_pull_none>,
+
+ <2 18 4 &pcfg_pull_none>,
+
+ <3 1 2 &pcfg_pull_none>,
+
+ <3 0 2 &pcfg_pull_none>,
+
+ <2 15 4 &pcfg_pull_none>,
+
+ <3 2 2 &pcfg_pull_none>;
+ };
+ };
+ };
+};
+
+/ {
+ model = "Orange Pi boards based on Rockchip RK3328";
+ compatible = "rockchip,rk3328";
+
+ aliases {
+ ethernet1 = &r8153;
+ };
+
+ chosen {
+ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ mach: board {
+ compatible = "orangepi,board";
+ machine = "ORANGEPI-R1PLUS";
+ hwrev = <2>;
+ model = "OrangePi R1PLUS";
+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
+ nvmem-cell-names = "id", "cpu-version";
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 =<&leds_gpio>;
+ status = "disabled";
+
+ led@1 {
+ gpios = <&gpio3 21 0>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ linux,default-trigger-delay-ms = <0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk805 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ reset-gpios = <&gpio3 8 1>;
+ };
+
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru 320>, <&cru 31>,
+ <&cru 77>, <&cru 81>;
+ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <0 4 4>;
+ status = "disabled";
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 28 0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_io>;
+ startup-delay-us = <2000>;
+ regulator-settling-time-us = <5000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_host_vbus: host-vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ dfi: dfi@ff790000 {
+ reg = <0x00 0xff790000 0x00 0x400>;
+ compatible = "rockchip,rk3328-dfi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru 64>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <0>;
+ #cooling-cells = <2>;
+ status = "disabled";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru 84>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru 101>;
+ assigned-clock-parents = <&cru 84>;
+ status = "disabled";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru 100>, <&cru 102>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-handle = <&rtl8211f>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,aal;
+ snps,pbl = <0x4>;
+ snps,txpbl = <0x4>;
+ snps,rxpbl = <0x4>;
+ tx_delay = <0x24>;
+ rx_delay = <0x18>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211f: ethernet-phy@0 {
+ reg = <0>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio1 18 1>;
+ };
+ };
+};
+
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 8>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_18>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 24 0 &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 8 0 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins = <1 6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins = <1 4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins = <1 5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 0 1 &pcfg_pull_up_4ma>,
+ <1 1 1 &pcfg_pull_up_4ma>,
+ <1 2 1 &pcfg_pull_up_4ma>,
+ <1 3 1 &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins = <3 2 3 &pcfg_pull_none_2ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins = <3 0 3 &pcfg_pull_up_2ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 4 3 &pcfg_pull_up_2ma>,
+ <3 5 3 &pcfg_pull_up_2ma>,
+ <3 6 3 &pcfg_pull_up_2ma>,
+ <3 7 3 &pcfg_pull_up_2ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+
+ <1 12 2 &pcfg_pull_none_8ma>,
+
+ <1 13 2 &pcfg_pull_none>,
+
+ <1 19 2 &pcfg_pull_none_2ma>,
+
+ <1 25 2 &pcfg_pull_none_8ma>,
+
+ <1 21 2 &pcfg_pull_none_2ma>,
+
+ <1 22 2 &pcfg_pull_none>,
+
+ <1 23 2 &pcfg_pull_none_2ma>,
+
+ <1 10 2 &pcfg_pull_none>,
+
+ <1 11 2 &pcfg_pull_none>,
+
+ <1 8 2 &pcfg_pull_none_8ma>,
+
+ <1 9 2 &pcfg_pull_none_8ma>,
+
+ <1 14 2 &pcfg_pull_none>,
+
+ <1 15 2 &pcfg_pull_none>,
+
+ <1 16 2 &pcfg_pull_none_8ma>,
+
+ <1 17 2 &pcfg_pull_none_8ma>,
+
+
+ <0 8 1 &pcfg_pull_none>,
+
+ <0 12 1 &pcfg_pull_none>,
+
+ <0 24 1 &pcfg_pull_none>,
+
+ <0 16 1 &pcfg_pull_none>,
+
+ <0 17 1 &pcfg_pull_none>,
+
+ <0 23 1 &pcfg_pull_none>,
+
+ <0 22 1 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 0 0 &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <3 1 0 &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <3 21 0 &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ rockchip,default-sample-phase = <120>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio1>;
+ interrupts = <26 4>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dr_mode = "host";
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus Lts";
+ compatible = "rockchip,rk3328";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key1>;
+
+ button@0 {
+ gpios = <&gpio0 0 1>;
+ label = "reset";
+ linux,code = <0x101>;
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 22 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ off-on-delay-us = <5000>;
+ enable-active-high;
+ };
+};
+
+&mach {
+ hwrev = <2>;
+ machine = "ORANGEPI-R1PLUS-LTS";
+ model = "OrangePi R1 PLUS LTS";
+};
+
+&emmc {
+ status = "disabled";
+};
+
+&leds {
+ status = "okay";
+
+ led@2 {
+ gpios = <&gpio2 15 0>;
+ label = "lan_led";
+ };
+
+ led@3 {
+ gpios = <&gpio2 18 0>;
+ label = "wan_led";
+ linux,default-trigger = "stmmac-0:00:link";
+ };
+
+};
+
+&rk805 {
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 8>;
+};
+
+&vccio_sd {
+ status = "okay";
+};
+
+&io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc_ext {
+ status = "disabled";
+};
+
+&sdio_pwrseq {
+ status = "disabled";
+};
+
+&spi0 {
+ max-freq = <48000000>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+/delete-node/ &rtl8211f;
+&gmac2io {
+ phy-handle = <&ethphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x19>;
+ rx_delay = <0x05>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy3: ethernet-phy@0 {
+ reg = <0x0>;
+
+
+ keep-clkout-on;
+ reset-gpios = <&gpio1 18 1>;
+ };
+ };
+};
+
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 24 0 &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ gpio_key1: gpio-key1 {
+ rockchip,pins = <0 0 0 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <1 26 0 &pcfg_pull_none>;
+ };
+
+ usb30_en_drv: usb30-en-drv {
+ rockchip,pins = <2 22 0 &pcfg_pull_none>;
+ };
+ };
+};
+
+&dmc_opp_table {
+ opp-1056000000 {
+ status = "disabled";
+ };
+ opp-924000000 {
+ status = "disabled";
+ };
+ opp-840000000 {
+ status = "disabled";
+ };
+ opp-798000000 {
+ status = "disabled";
+ };
+};
--
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