96 lines
2.3 KiB
Diff
96 lines
2.3 KiB
Diff
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
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new file mode 100644
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index 000000000000..6322f59939b8
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
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@@ -0,0 +1,89 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyarm.com)
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+ */
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+
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+/dts-v1/;
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+
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+#include "rk3328-nanopi-r2-rev00.dts"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R2C";
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+ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
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+};
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+
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+&mach {
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+ hwrev = <6>;
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+ model = "NanoPi R2C";
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+};
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+
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+&rgmiim1_pins {
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+ rockchip,pins =
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+ /* mac_txclk */
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+ <1 RK_PB4 2 &pcfg_pull_none_8ma>,
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+ /* mac_rxclk */
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+ <1 RK_PB5 2 &pcfg_pull_none>,
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+ /* mac_mdio */
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+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
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+ /* mac_txen */
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+ <1 RK_PD1 2 &pcfg_pull_none_8ma>,
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+ /* mac_clk */
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+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
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+ /* mac_rxdv */
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+ <1 RK_PC6 2 &pcfg_pull_none>,
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+ /* mac_mdc */
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+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
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+ /* mac_rxd1 */
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+ <1 RK_PB2 2 &pcfg_pull_none>,
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+ /* mac_rxd0 */
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+ <1 RK_PB3 2 &pcfg_pull_none>,
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+ /* mac_txd1 */
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+ <1 RK_PB0 2 &pcfg_pull_none_8ma>,
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+ /* mac_txd0 */
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+ <1 RK_PB1 2 &pcfg_pull_none_8ma>,
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+ /* mac_rxd3 */
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+ <1 RK_PB6 2 &pcfg_pull_none>,
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+ /* mac_rxd2 */
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+ <1 RK_PB7 2 &pcfg_pull_none>,
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+ /* mac_txd3 */
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+ <1 RK_PC0 2 &pcfg_pull_none_8ma>,
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+ /* mac_txd2 */
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+ <1 RK_PC1 2 &pcfg_pull_none_8ma>,
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+
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+ /* mac_txclk */
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+ <0 RK_PB0 1 &pcfg_pull_none>,
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+ /* mac_txen */
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+ <0 RK_PB4 1 &pcfg_pull_none>,
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+ /* mac_clk */
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+ <0 RK_PD0 1 &pcfg_pull_none>,
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+ /* mac_txd1 */
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+ <0 RK_PC0 1 &pcfg_pull_none>,
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+ /* mac_txd0 */
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+ <0 RK_PC1 1 &pcfg_pull_none>,
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+ /* mac_txd3 */
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+ <0 RK_PC7 1 &pcfg_pull_none>,
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+ /* mac_txd2 */
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+ <0 RK_PC6 1 &pcfg_pull_none>;
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+};
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+
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+/delete-node/ &rtl8211e;
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+
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+&gmac2io {
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+ phy-handle = <ðphy3>;
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+ snps,reset-delays-us = <0 15000 50000>;
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+ tx_delay = <0x22>;
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+ rx_delay = <0x12>;
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+ mdio {
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+
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+ ethphy3: ethernet-phy@3 {
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+ compatible = "ethernet-phy-id0000.011a",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+ interrupt-parent = <&gpio2>;
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+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
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+ //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ keep-clkout-on;
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+ };
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+ };
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+};
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