164 lines
4.4 KiB
Diff
164 lines
4.4 KiB
Diff
From 918d83519ccba3e540f6a9e0c201fcccf106988f Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Sat, 17 Apr 2021 16:30:58 +0000
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Subject: [PATCH 4/4] rk3318-box: add device tree overlay to support AP6334 and
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clones
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---
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arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
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.../rockchip/overlay/README.rockchip-overlays | 5 +++
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.../rockchip-rk3318-box-wlan-ap6334.dts | 31 +++++++++++++++++++
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3 files changed, 38 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
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index 565ef20ac..be038cc38 100644
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--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
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@@ -12,7 +12,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
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rockchip-dwc3-0-host.dtbo \
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rockchip-w1-gpio.dtbo \
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rockchip-rk3318-box-led-conf1.dtbo \
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- rockchip-rk3318-box-emmc-ddr.dtbo
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+ rockchip-rk3318-box-emmc-ddr.dtbo \
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+ rockchip-rk3318-box-wlan-ap6334.dtbo
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scr-$(CONFIG_ARCH_ROCKCHIP) += \
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rockchip-fixup.scr
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
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index 01fa6f4ee..0e7eaeea2 100644
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--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
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+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
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@@ -129,3 +129,8 @@ YX_RK3328 and clones
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Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
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nowadays support DDR mode, but its reliability heavily depends upon the quality
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of board wiring
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+
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+### rk3318-box-wlan-ap6334
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+
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+Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
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+wifi chip and clones
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
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new file mode 100644
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index 000000000..b7befaaeb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
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@@ -0,0 +1,117 @@
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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+#include <dt-bindings/interrupt-controller/irq.h>
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+
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+/ {
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+
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+ fragment@0 {
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+ target = <&sdio>;
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+ __overlay__ {
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ sd-uhs-sdr12;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr104;
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+ //sd-uhs-ddr50;
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+
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+ brcmf_sdio: wifi@1 {
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+ reg = <1>;
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+ compatible = "brcm,bcm4329-fmac";
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+ //brcm,drive-strength = <4>;
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+ interrupt-parent = <&gpio1>;
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+ interrupt-names = "host_wake";
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+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio_host_wake>;
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+ };
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+
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&sdio_ext>;
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+ __overlay__ {
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ sd-uhs-sdr12;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr104;
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+ //sd-uhs-ddr50;
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+
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+ brcmf_ext: wifi@1 {
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+ reg = <1>;
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+ compatible = "brcm,bcm4329-fmac";
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+ //brcm,drive-strength = <8>;
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+ interrupt-parent = <&gpio3>;
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+ interrupt-names = "host_wake";
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+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio_host_wake_ext>;
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+ };
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+
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&uart0>;
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+ __overlay__ {
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
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+
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+ bluetooth {
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+ compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt";
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+ max-speed = <4000000>;
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+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
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+ device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
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+ //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
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+ vbat-supply = <&vcc_io>;
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+ vddio-supply = <&vcc_18>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
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+ /*
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+ interrupt-names = "host-wakeup";
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <RK_PD2 IRQ_TYPE_NONE>;
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+ */
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+ brcm,bt-pcm-int-params = [01 02 00 01 01];
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+ };
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+
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+ };
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+
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+ };
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+
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+ fragment@3 {
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+ target = <&pinctrl>;
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+ __overlay__ {
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+
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+ bluetooth {
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+
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+
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+ bt_reg_on_h: bt-enable {
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+ rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>;
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+ };
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+
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+ bt_device_wake_l: bt-device-wake {
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+ rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
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+ };
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+
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+ bt_host_wake_l: bt-host-wake {
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+ rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
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+ };
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+
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+ };
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+
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+ };
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+ };
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+
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+};
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