56 lines
1.5 KiB
Groff
56 lines
1.5 KiB
Groff
From ccc7d2a5f907e060a1ed4b6b8f447b0721f36543 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sat, 23 Dec 2017 10:40:13 +0800
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Subject: [PATCH 15/35] arm64: allwinner: h6: add R_I2C controller
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Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
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are used in the reference design to connect AXP805 PMIC.
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Add support for it.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index 0ff9406..f3ca411 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -6,7 +6,9 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -261,6 +263,22 @@
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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+
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+ r_i2c_pins: r-i2c {
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+ pins = "PL0", "PL1";
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+ function = "s_i2c";
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+ };
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+ };
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+
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+ r_i2c: i2c@7081400 {
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+ compatible = "allwinner,sun6i-a31-i2c";
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+ reg = <0x07081400 0x400>;
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+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&r_ccu CLK_R_APB2_I2C>;
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+ resets = <&r_ccu RST_R_APB2_I2C>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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};
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};
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};
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--
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2.7.4
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