132 lines
4.6 KiB
Diff
132 lines
4.6 KiB
Diff
From 6110dbc7e6659d308d1593a1bd86c0045047a1f4 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Wed, 14 Oct 2020 01:19:27 -0500
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Subject: [PATCH 300/351] ASoC: sun8i-codec: Enable all supported clock
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inversions
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When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports
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independent BCLK and LRCK inversion control. When using DSP_A or DSP_B,
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LRCK inversion is not supported. The register bit is repurposed to
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select between DSP_A and DSP_B. Extend the driver to support this.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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Acked-by: Maxime Ripard <mripard@kernel.org>
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Link: https://lore.kernel.org/r/20201014061941.4306-4-samuel@sholland.org
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/sunxi/sun8i-codec.c | 61 ++++++++++++++++++++++-------------
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1 file changed, 39 insertions(+), 22 deletions(-)
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diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
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index 53c9289a4249..77eb0fd01e3d 100644
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--- a/sound/soc/sunxi/sun8i-codec.c
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+++ b/sound/soc/sunxi/sun8i-codec.c
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@@ -44,8 +44,7 @@
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#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
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#define SUN8I_AIF1CLK_CTRL 0x040
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#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
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-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
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-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
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+#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
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@@ -90,6 +89,7 @@
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#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
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#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
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#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
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+#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13)
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#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
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#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
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@@ -173,7 +173,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
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static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
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- u32 format, value;
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+ u32 dsp_format, format, invert, value;
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/* clock masters */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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@@ -202,8 +202,12 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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format = 0x2;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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+ format = 0x3;
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+ dsp_format = 0x0; /* Set LRCK_INV to 0 */
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+ break;
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case SND_SOC_DAIFMT_DSP_B:
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format = 0x3;
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+ dsp_format = 0x1; /* Set LRCK_INV to 1 */
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break;
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default:
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return -EINVAL;
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@@ -215,32 +219,45 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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/* clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF: /* Normal */
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- value = 0x0;
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+ invert = 0x0;
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break;
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- case SND_SOC_DAIFMT_IB_IF: /* Inversion */
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- value = 0x1;
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+ case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */
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+ invert = 0x1;
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+ break;
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+ case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */
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+ invert = 0x2;
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+ break;
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+ case SND_SOC_DAIFMT_IB_IF: /* Both inverted */
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+ invert = 0x3;
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break;
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default:
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return -EINVAL;
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}
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
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- value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
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- /*
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- * It appears that the DAI and the codec in the A33 SoC don't
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- * share the same polarity for the LRCK signal when they mean
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- * 'normal' and 'inverted' in the datasheet.
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- *
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- * Since the DAI here is our regular i2s driver that have been
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- * tested with way more codecs than just this one, it means
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- * that the codec probably gets it backward, and we have to
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- * invert the value here.
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- */
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- value ^= scodec->quirks->lrck_inversion;
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+ if (format == 0x3) {
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+ /* Inverted LRCK is not available in DSP mode. */
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+ if (invert & BIT(0))
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+ return -EINVAL;
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+
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+ /* Instead, the bit selects between DSP A/B formats. */
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+ invert |= dsp_format;
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+ } else {
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+ /*
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+ * It appears that the DAI and the codec in the A33 SoC don't
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+ * share the same polarity for the LRCK signal when they mean
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+ * 'normal' and 'inverted' in the datasheet.
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+ *
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+ * Since the DAI here is our regular i2s driver that have been
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+ * tested with way more codecs than just this one, it means
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+ * that the codec probably gets it backward, and we have to
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+ * invert the value here.
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+ */
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+ invert ^= scodec->quirks->lrck_inversion;
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+ }
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+
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regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
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- value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
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+ SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK,
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+ invert << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);
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return 0;
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}
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--
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2.34.0
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