142 lines
5.6 KiB
Diff
142 lines
5.6 KiB
Diff
From ee35368e8c51b8c22b64873419f61f23fb994d8d Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Wed, 14 Oct 2020 01:19:39 -0500
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Subject: [PATCH 312/351] ASoC: sun8i-codec: Generalize AIF clock control
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The AIF clock control register has the same layout for all three AIFs.
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The only difference between them is that AIF3 is missing some fields. We
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can reuse the same register field definitions for all three registers,
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and use the DAI ID to select the correct register address.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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Acked-by: Maxime Ripard <mripard@kernel.org>
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Link: https://lore.kernel.org/r/20201014061941.4306-16-samuel@sholland.org
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/sunxi/sun8i-codec.c | 62 ++++++++++++++++++-----------------
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1 file changed, 32 insertions(+), 30 deletions(-)
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diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
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index e3abf8363d9b..6aa8751f7fa0 100644
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--- a/sound/soc/sunxi/sun8i-codec.c
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+++ b/sound/soc/sunxi/sun8i-codec.c
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@@ -42,13 +42,13 @@
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#define SUN8I_SYS_SR_CTRL 0x018
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#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
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#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
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-#define SUN8I_AIF1CLK_CTRL 0x040
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-#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
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-#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13
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-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
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-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
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-#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
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-#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
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+#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n)))
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+#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15
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+#define SUN8I_AIF_CLK_CTRL_CLK_INV 13
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+#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9
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+#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6
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+#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4
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+#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2
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#define SUN8I_AIF1_ADCDAT_CTRL 0x044
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14
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@@ -88,11 +88,11 @@
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#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
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#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
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#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
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-#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13)
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-#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
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-#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
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-#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
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-#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
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+#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)
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+#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)
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+#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)
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+#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)
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+#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
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#define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
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@@ -241,9 +241,10 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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default:
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return -EINVAL;
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}
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
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- value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
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+
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
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+ value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
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/* DAI format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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@@ -267,9 +268,10 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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default:
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return -EINVAL;
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}
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK,
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- format << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
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+
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK,
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+ format << SUN8I_AIF_CLK_CTRL_DATA_FMT);
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/* clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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@@ -310,9 +312,9 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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invert ^= scodec->quirks->lrck_inversion;
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}
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK,
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- invert << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ SUN8I_AIF_CLK_CTRL_CLK_INV_MASK,
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+ invert << SUN8I_AIF_CLK_CTRL_CLK_INV);
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return 0;
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}
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@@ -459,27 +461,27 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
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- word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK,
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+ word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
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/* LRCK divider (BCLK/LRCK ratio) */
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lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width);
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if (lrck_div_order < 0)
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return lrck_div_order;
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
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- (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK,
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+ (lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV);
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/* BCLK divider (SYSCLK/BCLK ratio) */
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bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate);
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if (bclk_div < 0)
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return bclk_div;
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- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
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- SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
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- bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
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+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
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+ SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
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+ bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
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/*
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* SYSCLK rate
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--
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2.34.0
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